JPH0816429A - Parallel program generation supporting device, parallel program generating method, and parallel program executing device - Google Patents

Abstract

PURPOSE:To provide a parallel program generating method and its generation supporting device which facilitate the test debugging of parallel programs and make the development of the parallel programs efficient, and the parallel program executing device which makes possible partial execution guaranteeing effective test debugging and reproducibility. CONSTITUTION:These devices are equipped with a sequencing means 12 which converts a 1st parallel program having parallel structure into a sequentially executable sequential program, a test debugging means 16 which performs the test debugging of the sequential program and generates test debugging information, a parallelizing means 18 which converts the sequential program after the test debugging into a 2nd parallel program by parallelizing the program based on the test debugging information. Further, the test debugging means 16 includes a means for introducing information regarding parallelism in the sequential program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating a parallel program, a creation support apparatus therefor, and a parallel program execution apparatus.

[0002]

2. Description of the Related Art Recent advances in semiconductor integrated circuit technology have made it possible to realize complex processors and large-capacity memories at a small size and at low cost, and to put parallel processing systems and distributed processing systems consisting of a large number of processors into practical use. Has been done. For such hardware, a dedicated program, that is, a parallel program, a distributed processing program, or the like (hereinafter referred to as "parallel program") must be used. Therefore, how to develop a parallel program efficiently is as important as the case of examining a good algorithm.

By the way, in developing a program, it is necessary to find and fix a bug in the program (ie,
A development process called debugging greatly affects the efficiency of program development. However, in the development of concurrent programs, it is necessary to consider the problems peculiar to concurrent programs that are not encountered in the development of sequential programs. The problem peculiar to the concurrent program is that the processes constituting the concurrent program may behave differently depending on the timing of interaction between the processes, and thus the entire concurrent program does not operate correctly. This problem is based on the nature of concurrent programs and is commonly called "non-deterministic".

For example, consider the concurrent program shown in FIG. In FIG. 116 (a), the process P1 is
A process for initializing (init) the shared memory M,
The process P2 reads from the shared memory M (rea
A process for performing d), process P3, is a process for performing writing in the shared memory M. When these processes are operated by a parallel processing system or the like in which they are executed by different processors, there are a total of 6 combinations of operations (see FIG. 116 (b)). Normally, the system starts the process with the initial settings, so now the process P1 (init) → P2 (read)
→ P3 (write) or P1 (init) → P3 (w
If a correct result is obtained when the program operates in the order of write) → P2 (read), the remaining four ways (for example, P2 → P3 → P1) are not initialized first. It is clear that the correct result cannot be obtained.

As described above, the non-determinism regarding the behavior of the process has different results each time the concurrent program is operated, depending on the state of the system at that time. Therefore, unless this problem of non-determinism is solved, there is no guarantee that the concurrent program will always work, even if it works fine in testing.

Also, bugs related to non-determinism are generally
More difficult than finding bugs in a sequential program. Because, in a sequential program, the operation can be confirmed by executing all the paths in the program at the time of test / debug, whereas in the parallel program, all the combinatorial paths (that is,
This is because not only all the paths in each process, but also the behaviors among the processes must be taken into consideration when executing the paths. When the number of processes is small as in the above example, it is relatively easy to enumerate all the behaviors between each process, but in actual program development, the number becomes enormous. With so many combinations, it is no longer possible to understand all the behavior.

[0007]

As described above, the test / debug in the concurrent program development is very difficult as compared with the test / debug in the sequential program development. In particular, today, when the program itself has become huge, this test / debug becomes more difficult.

Further, since the reproducibility is not guaranteed by the nondeterminism which is a problem peculiar to a concurrent program, the test
There are problems that debugging becomes difficult and an unexpected error appears.

An object of the present invention is to provide a method for creating a parallel program and a creation support device for the parallel program, which can easily test / debug the parallel program and can efficiently develop the parallel program.

Another object of the present invention is to ensure reproducibility by sequentially executing a parallel program, to enable effective test / debug, and to parallelize a part after the test / debug. It is to provide a concurrent program execution device capable of safely executing a concurrent program by eliminating an unexpected error due to nondeterminism.

The present invention once serializes a concurrent program,
The main idea is to perform test / debug on the serialized program and restore the concurrency of the program when the test / debug is completed.

[0012]

The present invention has taken the following means in order to solve the above problems. The difficulty of programming a concurrent program is that "human thinking is inherently sequential, and it is difficult to logically recognize what moves in parallel as it is." Therefore,
According to the present invention, a parallel program is serialized once, and programming, testing and debugging are performed on the serialized program. This is the same level of difficulty as conventional sequential programming. Then, when the test / debug is completed, the concurrency is automatically restored by using the test / debug information.

The above programming style is called "hyper sequential programming". According to this "hyper-sequential programming", the difficulty of programming in the conventional method can be solved. The basic concept of the present invention is
It consists of the following three steps (or means).

(1) A step (means) for serializing a parallel program to generate a hyper-sequential program.

(2) Work on hyper-sequential programs (programming, testing / debugging, introduction of concurrency)
Steps (means) for performing.

(3) A step (means) for parallelizing the hyper-sequential program whose work has been completed to create a parallel program.

Here, the "hyper-sequential program" refers to a program that is serialized while maintaining information about the parallel structure of the original parallel program.

The parallel program creating apparatus according to the present invention is
Serializing means for converting the first concurrent program having a parallel structure into a serial program that can be sequentially executed, test / debug means for performing test / debug of the serial program, and creating test / debug information, and after test / debug Parallelizing means for converting the serial program into a second parallel program by parallelizing the sequential program based on the test / debug information. In addition, the method of creating a concurrent program according to the present invention includes a first step of converting a first concurrent program having a concurrent structure into a sequentially executable sequential program, and a test / debug of the sequential program to obtain test / debug information. And a third step of converting the serial program after the test and debug into a second parallel program by parallelizing the serial program based on the test and debug information.
And a step.

The preferred embodiments of the present invention are listed below. (1) To introduce information about concurrency to the sequential program. The information about the concurrency includes, for example, information about good non-determinism described later. (2) The parallel structure of the first concurrent program is analyzed, and the parallel program is parallelized using the execution results obtained by testing this parallel structure and the sequential program.

(3) The parallel structure of the section converted into the serial program of the first parallel program and the serial structure of the section of the serial program are analyzed respectively, and the mutual relationship regarding the parallel structure of the first parallel program and the serial of the serial program are analyzed. Display the interrelationships regarding the structure as graph information. In the display of the graph information, the predetermined section group is used as a node, the mutual relationship regarding the parallel structure of the first concurrent program is referred to as the first arc, and the mutual relationship relating to the sequential structure of the sequential program is displayed as the second arc. . Then, the selected section of the sequential program is parallelized and converted into a partial sequential program having a partial sequential structure, and this partial sequential program is parallelized and converted into a second parallel program.

Here, in the step of converting the first concurrent program into a sequential program, a test of the sequential program is performed until a desired execution result of the sequential program is obtained.
Including the step of performing debugging, or in the step of converting the sequential program into the partial sequential program, including the step of testing and debugging the partial sequential program until the desired execution result is obtained, or both of these tests -A debug step may be included.

Further, the step of converting the sequential program into the partial sequential program includes the step of analyzing the sequential structure of the partial sequential program, and then displaying the graph information, selecting the parallelization section, and displaying the partial sequential program. The conversion step may be repeated a predetermined number of times.

(4) At the time of serialization for converting the first concurrent program into a sequential program, the first concurrent program is executed and the execution log resulting therefrom is saved, and
The saved execution log and the first parallel program are analyzed, and the saved execution logs are rearranged based on the analysis result. In the analysis of the execution log and the first concurrent program, for example, the preceding relation of the process is extracted from the saved execution log and the first concurrent program, and this is stored as the preceding relation information.

(5) When introducing information about concurrency for a serial program, the process flow of the serial program is converted into a field consisting of constraints and transition conditions,
This is done by tuning this field.
Further, field data representing this field is displayed.

(6) A process group that is a candidate for parallelization is designated for the sequential program, the execution order of the process group is changed, and the sequential program is converted into a plurality of parallel simulation programs. The program is partially converted into one partial sequential program having a sequential structure, and this partial sequential program is parallelized and converted into a second concurrent program.

Here, in the step of converting the first concurrent program into a sequential program, a step of testing and debugging the sequential program is included until a desired execution result of the sequential program is obtained, or a plurality of parallel simulations are performed. In the step of converting the program group into one partial sequential program, test / debug of a plurality of parallel simulated programs is performed until a desired execution result of the parallel simulated program group is obtained, or both of these test programs are tested.
Debug steps may be included. Further, when designating a process group that is a candidate for parallelization with respect to a sequential program, the first concurrent program may be analyzed and the process group that is a candidate for parallelization may be extracted from the analysis result. Also,
The step of converting the sequential program into a plurality of parallel simulation programs may include a step of removing a parallel simulation program determined to be unnecessary from a part of execution results of the plurality of parallel simulation programs. Further, in the step of converting a plurality of parallel simulation programs into one partial sequential program, a step of designating a process group that is a candidate for parallelization is included in the partial sequential program, and the sequential program is converted into a plurality of parallel simulation programs. The step of converting and the step of converting a plurality of parallel simulation programs into one partial sequential program may be repeated a predetermined number of times.

(7) When the conversion of the first concurrent program into a serial program is performed according to a predetermined serialization rule,
By modifying this serialization rule, information about concurrency is introduced into the serial program.

(8) A log which is an execution history of a process group of a parallel program in a parallel program creation support device for supporting creation of a parallel program used in an execution environment in which process groups operate in parallel while exchanging message information. Information is acquired and stored as a serialization rule, and the stored log information can be corrected. Sequential startup control of process groups based on stored log information,
Further, the stored log information is parallelized and converted into a second parallel program.

Here, the log information correction means includes a display means for displaying the log information stored in the log information storage means in time series, and a data in the log information displayed in time series by the display means. The present invention is characterized by including replacement instruction means for instructing order replacement and rewriting means for rewriting the log information stored in the log information storage means in accordance with an instruction from the replacement instruction means. Further, the log information correcting means is characterized by including non-determinism introducing means for introducing non-determinism of processing timing between processes.

(9) In a system in which the process groups operate in accordance with the execution order definition information in an execution environment in which the process groups can operate in parallel while exchanging message information, the execution order definition information is divided and the divided execution is executed. The process group is activated and controlled based on the sequence information.

In this case, it is possible to further include means for holding a division standard designating means for giving a standard for dividing the execution order defining information. Further, the history of message exchange is used as the execution order defining information, and the destination process information in the message is used as the reference for division in the division reference designating means. Further, the history of message exchange is used as execution order defining information, the destination process information in the message is used as a reference as a division criterion in the division criterion specifying means, and a process control means is provided for each process. Furthermore, the history of message exchange is used as execution order defining information, the destination process information in the message is used as a reference as a division criterion in the division criterion specifying means, and a process control means is held for each process, and an execution order. The divided execution order information storing means stores the execution order information divided by the information dividing means separately, and the process control means stores the divided execution order information stored in the divided execution order information storing means corresponding to the process. Control the process based on Further, the log information, which is the execution history information of the process group, may be used as the execution order defining information.

(10) The first parallel program is test-executed, a bug-free execution log is accumulated as a result of the test execution, and only the accumulated bug-free execution log is parallelized and converted into the second parallel program. To do. Further, as a result of the test execution, an execution log having a bug is accumulated, and the first concurrent program is modified based on the accumulated execution log having a bug.

Further, the parallel program execution device of the present invention is a program analysis means for analyzing a parallel program to extract sections and extracting rules regarding an execution order for controlling synchronization at the time of execution between the sections. Edit the rules related to the execution order to adjust the synchronization between sections at the time of execution, and mainly to improve the efficiency of execution, edit means that fuses and divides the extracted sections, and converts the sections into objects And a executing means for executing serially or in parallel in section units according to a rule regarding the execution order.

[0034]

As a result of taking the above-mentioned means, the following effects occur. According to the present invention, by serializing a concurrent program once and performing test / debug on the serialized program, it is possible to test the concurrent program with the same level of difficulty as sequential programming, which is much easier than conventional concurrent program programming. Debugging is possible.

Further, according to the present invention, since information about concurrency (good nondeterminism) can be intentionally introduced into a program that has been once serialized, a bug caused by unintended concurrency (bad nondeterminism). Can be avoided and high reliability can be achieved.

By presenting parallelization and serialization information to the user at the same time by the above graph information,
The user considers the parallel structure of the first concurrent program,
You will be able to specify good non-deterministic parts. In addition, it is possible to specify and cancel the good non-deterministic part for the graph information instead of specifying and canceling the good non-deterministic part at the concurrent program description level. , Will be able to easily develop concurrent programs.

When the first concurrent program is converted into the sequential program, the first concurrent program and its execution log are analyzed, and the execution logs are sorted based on the analysis result. By displaying it and presenting it to the user, it becomes easy to understand the execution process of the concurrent program, and the efficiency of test / debug is improved. When introducing information about concurrency into a serial program, the process flow of the serial program is converted into a field consisting of constraints and transition conditions, and the field data is displayed to edit the field interactively and visually. This effectively introduces information about concurrency and effectively creates bug-free concurrent programs.

After a process group that is a candidate for parallelization is designated for the serialized program serialized from the first concurrent program and the execution order of this process group is exchanged to convert the sequential program into a plurality of parallel simulated programs. , A plurality of parallel simulation programs are partially converted into one partial sequential program having a sequential structure, and the partial sequential program is parallelized and converted into a second parallel program, thereby making The operation can be fully confirmed. Further, by designating a process group that is a candidate for parallelization with respect to the partial sequential program, the sequential structure program can be gradually converted into a parallel program. Furthermore, by introducing information about concurrency that allows only nondeterminism that is confirmed to operate correctly by sequential execution based on the parallel simulated operation sequence, a parallel program that operates correctly can be obtained. These facilitate testing and debugging of concurrent programs.

In a parallel program creation support device that supports creation of a parallel program used in an execution environment in which process groups operate in parallel while exchanging message information, log information that is the execution history of the process group of the first parallel program Is acquired as a serialization rule and stored, the log information can be corrected, and the process group is sequentially activated based on the stored log information, and the stored log information is stored. By parallelizing and converting to the second parallel program, it is possible to solve the problem caused by the nondeterminism of the processing timing by modifying the log information without modifying the parallel program as the source program. This facilitates the development of parallel / parallel / distributed programs with inherent non-deterministic processing timing.
Further, since only good nondeterminism intended by the user can be easily introduced, it is possible to maintain flexibility, reusability, and extensibility as a concurrent program.

In a system in which the process groups operate according to the execution order defining information in an execution environment in which the process groups can operate in parallel while exchanging message information, the execution order defining information is divided, that is, a parallel program is serialized. By dividing the centralized log information of all the processes for each process and controlling the activation of the process group based on this divided execution order information, harmless nondeterminism is naturally introduced, and the sequential log information is used. It is possible to obtain the same result as when the program is executed with high processing efficiency.

As a result of the test execution of the first concurrent program, a bug-free execution log, which is one of them, is accumulated, and only the accumulated bug-free execution log is parallelized to generate a second concurrent program. By converting to, the program moves so that only the timing passed in the test is allowed, so it is possible to avoid falling into the bug that remained due to not testing, and improve the reliability.

According to the parallel program execution apparatus of the present invention, since it is possible to execute a serial or partial parallel execution of a parallel program, reproducibility can be guaranteed as in the conventional serial program, and it is effective and stable. You can perform the test / debug that you have done. Moreover, since it is possible to easily switch from serial execution to partial parallel execution, it is possible to safely execute parallel execution of a program that has been serialized and tested and debugged without being affected by nondeterminism. In addition, by editing the rules regarding the execution order of the sections and controlling the synchronization between the sections at the time of execution, it is possible to perform effective test / debug and also to guide the efficiency of the program.

Furthermore, the parallel program execution device of the present invention can be used in combination with the parallel program creation support device or creation method of the present invention. In this case,
The parallel program execution device functions as an execution unit of the first parallel program (source program). Furthermore, the parallel program execution device can also be used for verification of a parallel program created by the parallel program creation support device or creation method of the present invention.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. Before describing the embodiments of the present invention, the terms used in the present invention are defined as follows.

Concurrent system: A system with logical concurrency. A system in which a concurrent program works is a concurrent system. Parallel computers and distributed processing systems are parallel systems.

Concurrent program (CP): A program written based on a model that logically moves in parallel. Multiple C
A program (parallel program) that operates in parallel both logically and physically on a parallel computer composed of PU is included in the parallel program. Further, even if they physically move sequentially on a single CPU, if they are logically parallel as in a multi-task system, they are included in a parallel program.

Sequential program: A program written based on a model that logically moves sequentially.

Hyper Sequential Program (HSP): A program that is made to run sequentially by adding meta level (execution management level) control to a concurrent program. For example, a program written as a concurrent program
A program that is made to run sequentially by adding a scheduler of the execution management level is a hyper sequential program. Since the hyper-sequential program does not have the nondeterminism described later, its behavior will always be reproducible if the input from the outside is the same. In addition, concurrency (nondeterminism) can be partially introduced in the hyper sequential program. A hyper-sequential program with partial concurrency (non-determinism) introduced is called a partial hyper-sequential program (PHSP), and a fully serialized program with no concurrency (non-determinism) is called a full hyper-sequential program. Sometimes called.

Nondeterminism: The behavior of the system changes depending on the timing of processing even though the inputs are the same.
Non-determinism is an essential aspect of the execution of concurrent programs. In a sense, non-deterministic programs are logically equivalent to sequential programs.

Good non-determinism: The non-determinism intended by the user, that is, the non-determinism included in the user's specifications and other realization requirements. This nondeterminism allows appropriate response to nondeterministic input from the outside (environment).

Bad non-determinism: Non-determinism that the user did not expect. Since the user's thinking circuit is sequential, there are many cases in the actual execution of concurrent programs that were not intended during design.

Harmless nondeterminism: The choice of nondeterministic options does not affect the final outcome. In the "hyper-sequential programming" parallelization device, the object to be parallelized includes this "harmless nondeterminism".

Default serialization: Perform serialization control at the execution management level.

Parallel simulation program: In a hyper sequential program, a set of parallel simulation operation sequences generated for a specific range that is a candidate for parallelization.

Concurrent simulation operation sequence: In order to simulate the operation of a parallel program on a sequential program in a specific range that is a candidate for parallelization in a hyper sequential program, the order of sequential execution is arbitrarily or intentionally changed. One motion sequence generated by In general, since a plurality of parallel simulation operation sequences are generated in one parallelization range, the whole is called one parallel simulation program. Multiple parallel simulation programs are generated in the entire hyper-sequential program.

FIG. 1 is a diagram showing an example of the configuration of a computer system for realizing the parallel program creation support apparatus according to the present invention. In FIG. 1, N processors 1
-1, 1-2, ..., 1-N can execute parallel programs at the same time, and can access the shared memory 3 and peripheral devices via the I / O interface 2. The peripheral device includes an input device 4, an output device 5, and an external storage device 6. The input device 4 includes a keyboard and a pointing device, and is used to input various commands and data. The output device 5 is C
It consists of an RT display, etc., and presents it to the user by displaying text or graphic information on the source program and the test / debug status. The user can interactively operate the computer by using the input device 4 and the output device 5.

The external storage device 6 is composed of a magnetic disk, a magneto-optical disk, or the like, and is capable of writing or reading the source program and information regarding the test / debug state.

The configuration of the computer system described above does not have to be particular about this. For example, a so-called distributed network in which a plurality of computers are connected via a network may be used.

In the computer system configured as described above, the creation of the parallel program according to the present invention is realized as follows.

(Embodiment 1) In Embodiment 1, test / debug is performed on a partial hyper-sequential program, and as a preferred embodiment, good nondeterminism is introduced to the hyper-sequential program. It should be noted that although an example in which good nondeterminism is introduced will be described in the following embodiments, good nondeterminism may not necessarily be introduced.

FIG. 2 is a diagram showing a schematic configuration of the parallel program creation support apparatus according to the first embodiment. The concurrent program creation support device according to the first embodiment includes a serialization device 12, a test execution device 15, a debug device 16, a nondeterminism introduction device 17, and a parallelization device 18.

The serialization device 12 uses the source program stored in the first CP file storage unit 11 (hereinafter referred to as “first parallel program”) based on the serialization rules stored in the serialization rule storage unit 13. It is converted into a hyper sequential program and the result is stored in the HSP file storage unit 14. The first CP file storage unit 11 stores a first parallel program modeled and described in a parallel programming language. In this first concurrent program,
There may be a bug. Concurrent programming languages for describing the first concurrent program include, for example, the following. (A) Concurrent PASCAL (b) ADA (c) GHC (d) Modula3 (e) Occam (f) cooC The test execution device 15 and the debug device 16 respectively store the hyper sequential programs stored in the HSP file storage unit 14. Test and debug.

The nondeterminism introducing device 17 introduces good nondeterminism when converting the first concurrent program into a hyper sequential program.

The parallelizing device 18 parallelizes the hyper sequential program based on the test / debug information of the hyper sequential program stored in the HSP file storage unit 14,
Generate a concurrent program. This second parallel program is stored in the second CP file storage unit 19.

FIG. 3 is a flowchart showing a schematic procedure of the parallel program creating method according to the first embodiment.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Moreover, each process structure of the parallel system is determined. Further, a parallel program having a parallel structure is described as a source program by programming in each process using a parallel program or the like. It should be noted that "having a parallel structure" generally means that a parallel program does not consist entirely of a parallel structure, and if modeling using sequentiality is more natural, This is because that part may be a sequential structure. Note that there is a potential bug in this source program.

(2) Step A2: Serialization By default serialization, the first concurrent program is converted into a hyperserial program having a sequential structure. In this embodiment, the sequentiality is introduced at the meta level. Here, the meta level does not mean the level of the source program (that is, the first concurrent program) itself, but the level of managing the execution of the source program. For example, a source program written in a parallel program is converted into a source program of a program guaranteed to be sequentially executed by a scheduler managed separately from the source program.

(3) Step A3: Test / debug of hyper sequential program Test / debug of hyper sequential program. Based on the result of test execution of the hyper sequential program by the test execution device, the debug device removes a bug from the hyper sequential program. The test / debug here can be performed in the same manner as the normal test / debug method in the sequential program. Test and debug until the super sequential program is guaranteed to operate normally.

(4) Step A4: Introduction of Good Nondeterminism to Hypersequential Program Information on good nondeterminism (information about concurrency) for hyperserial programs that have been tested and debugged.
give. As a result, the hyper-sequential program becomes a partial hyper-sequential program by partially having information about nondeterminism. The method of introducing information about good nondeterminism will be described later.

(5) Step A5: Test / Debug of Partial Hyper-Sequential Program The partial hyper-sequential program obtained in Step A4 is tested / debugged. That is, step A4
Test and debug hyper-sequential programs with information about good nondeterminism introduced in.

(6) Step A6: Introduction / Expansion of Good Nondeterminism for Partial Hypersequential Program Information about good nondeterminism is added to the partial hypersequential program tested and debugged in step A5. Steps A5 to A6 are repeated a predetermined number of times to gradually expand the good nondeterminism.

(7) Step A7: Parallelization Compile A partial hyper-sequential program is extracted by extracting a harmless non-deterministic part from the partial hyper-sequential program in which information on good non-determinism is introduced and parallelizing the part. The whole is restored to the concurrent program (that is, the second concurrent program). That is, regarding the part where the information about the parallelization is not introduced, the seriality given by the default serialization is reflected in the parallel program (for example, embedded in the source program itself), and the default seriality at the meta level is canceled. .

The present invention will be described more specifically with reference to FIGS.

FIG. 4 is a diagram showing an example of a simple parallel program.

The parallel program of FIG. 4 is composed of a process P1 and a process P2. These processes are realized only when the execution module generated by compiling the source code of the parallel program is executed on the computer, and the parallel programs corresponding to the processes P1 and P2 are It does not necessarily have to be physically stored in another storage medium. Further, the memory M is a shared memory (sha
red memory), and access such as writing / reading can be performed by the access instruction of the parallel program. In FIG. 4, solid arrows indicate that access is performed to the shared memory M when the processes P1 and P2 are executed.

First stored in CP file storage unit 11
The parallel program is extracted by a user's instruction from the input device 4 and input to the serialization device 12. The first concurrent program input to the serialization device 12 follows the serialization rule stored in the serialization rule storage unit 13
By introducing default seriality at the meta level, it is converted into a hyper sequential program (HSP), and HS
It is recorded in the P file storage unit 14.

Typical serialization rules are as follows. (A) A rule that introduces priority into a process. (B) A rule for introducing a priority to a processing unit (method in object orientation) in a process. (C) A serialization rule based on a specific execution log. (D) A serialization rule that gives priority to the execution of the destination of the message. (E) A serialization rule that prioritizes the execution of the message sender.

"P1 >>P2" described in the lower part of FIG. 4 is an example of the serialization rule for the parallel program of FIG. 4, and it is said that P1 is preferentially operated over P2 for the two processes P1 and P2. This represents giving priority. This corresponds to the rule (a) above. This serialization rule may be introduced at the beginning of the first concurrent program, for example, and may be introduced into the concurrent program by compiling with the program body.
It may be described in a file separately from the parallel program and introduced by being interpreted by the operating system or the scheduler when the parallel program is executed. In the present embodiment, the serialization rule is indicated by ">>", but the present invention is not limited to this and any symbol can be used.

FIG. 5 is a conceptual diagram of the hyper-sequential program HSP in which the default seriality is introduced at the meta level, and shows that the process P1 and the process P2 are managed by the scheduler S. In FIG. The broken line arrow indicates the serialization rule ("P1 >>" shown in FIG.
P2 ″) indicates that the scheduler S executes the process P1 and then the process P2. The conceptual diagram of this hyper-sequential program HSP is HSP = P1 | P2 | Suppose that the hyper-sequential program HSP is composed of a process P1, a process P2, and a scheduler S. Here, the serialization rule corresponds to the scheduling rule of the scheduler. .

The user can see the hyper sequential program HSP by the output device 5. This hyper-sequential program HSP is input to the test execution device 15 according to an instruction from the input device 4 by the user, and the test execution is performed. The test execution device 15 presents the result of the test execution (execution log) to the output device 5. The user sets the input device 4 to the debug device 1 based on the result of this test execution.
6 can be used to perform predetermined test / debug on the hyper sequential program HSP. Specific test / debug techniques include (a) source code tracer, (b) breakpoints, and (c) animation.

FIG. 6 is a diagram showing an image of the test / debug at this time. In FIG. 6, various windows 61 to 65 are opened and various information is displayed on the debug screen 60 on the output device 5, and these windows 61 to 65 can be appropriately opened and closed. Note that, for the test / debug here, a known debug device can be basically used, and specifically, dbxtool on a UNIX workstation is known.

The user gives a test execution instruction again from the input device 4 after performing a predetermined test / debug on the hyper sequential program HSP. This allows you to test
The debugged hyper sequential program HSP is input to the test execution device 15 and the test execution is performed again.
This test / debug is repeated until it is confirmed that the hyper sequential program HSP operates normally. When the normal operation is confirmed by the test / debug, the nondeterminism introducing device 17 partially introduces the information regarding good nondeterminism into the hyper sequential program. Information about the good nondeterminism introduced by the nondeterminism introducing device 17 is reflected in the hyper sequential program HSP,
It is recorded in the HSP file storage unit 14. The non-determinacy introducing device 17 will be described later.

FIG. 7 is a diagram showing an example of a state in which information on good nondeterminism is introduced into a hyper sequential program.
Here, when the execution unit of each process of the parallel program is called a “section”, FIG. 7 shows a process P1 divided into a section S1 and a section S2 and a section S3.
With respect to the process P2 divided into the section S4 and the section S4, the section S2 and the section S3 have the same priority, thereby showing a state in which nondeterminism is introduced.

More specifically, information about good nondeterminism is given to a predetermined part of a serialization rule that gives different priorities for each execution unit (for example, processes that want to have the same priority are designated with a mouse). By doing so, the portions have the same priority and can be executed in parallel. In the example of FIG. 7, of the four sections S1 to S4, "S2 is" write1 "and S3 is" r.
The information "ead2" has the same priority "(S2 =
S3) is introduced as a good nondeterminism. That is,
Processes with the same priority are non-deterministic because either process can be executed first.

Next, the hyper-sequential program (partial hyper-sequential program PHSP) in which the information on good non-determinism is introduced into the non-determinism introducing device 17 is test-executed by the test executing device 15 according to an instruction from the user,
Test / debugging is performed by the debug device 16.
In this case, the behavior of the partial hyper-sequential program PHSP behaves in a non-deterministic manner with respect to the portion in which the information regarding good non-determinism is introduced, and therefore it is preferable to test / debug all the behaviors. In this way, the test / debugging and the introduction of the information on the good nondeterminism are repeated, and the information on the good nondeterminism is gradually added.

The partial hyper-sequential program PHSP obtained by incrementally introducing information on good nondeterminism is input to the parallelization device 18 according to an instruction from the user. The parallelizer 18 extracts a harmless nondeterministic part of the partial hypersequential program PHSP,
Partial hyper sequential program The whole PHSP is parallelized. That is, the parallelization device 18 releases the default seriality with respect to the introduced good nondeterminism and harmless nondeterminism, and records it in the file as the parallel program CP (second parallel program). Here, except for good non-determinism and harmless non-determinism, the seriality given by default serialization must be reflected in the concurrent program CP. The user can see the second parallel program by the output device 5 and can perform final test / debug.

Although the first embodiment has shown a basic embodiment of the present invention, a more detailed embodiment will be described below.
However, in the following embodiments, portions common to or corresponding to those of the first embodiment are designated by the same reference numerals to simplify or omit the description, and different points will be mainly described.

(Embodiment 2) In Embodiment 2, as in Embodiment 1, the following parallel program is targeted. A concurrent program consists of multiple processes. A parallel program is executed by a shared memory type multiprocessor. A processor (CPU) is assigned to each process. The synchronization of each process is realized by a synchronization basic instruction and a shared memory type.

An embodiment in which the present invention is applied to the above parallel program will be described. FIG. 8 is a block diagram showing a schematic configuration of a parallel program creation support device according to the second embodiment.
FIG. 9 is a flowchart of a schematic procedure of the parallel program creating method according to the second embodiment. 8 is different from FIG. 2 in that it further includes a section setting device 7, and the test execution device 15 and the debug device 16 are specifically a test execution device 15, a correction device 9, and an analysis device 10. The point is that it has an analysis information storage unit 20 that stores the analysis information analyzed by the analysis device 10. The analysis device 10 analyzes the hyper-sequential program and extracts a preceding constraint described later as analysis information. Since the other components are the same as those in the first embodiment, the description thereof will be omitted. It should be noted that FIG.
Then, the parallelization rule storage unit 21 for storing the parallelization rule referred to when the hyperserial program is parallelized is provided.

The section setting device 7 divides each process of the first parallel program into some sections (program units).

If there is a bug as a result of the test by the test execution device 15, the correction device 9 corrects it.

The test execution unit 15 tests the hyper-sequential program as in the first embodiment.

The analysis information storage section 20 stores the information analyzed by the analysis device 10.

The operation of the second embodiment will be described with reference to the flowchart of FIG. In FIG. 9, the same operations as those in the flowchart of FIG. 3 are designated by the same reference numerals.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Moreover, each process structure of the parallel system is determined. Further, a parallel program having a parallel structure is described as a source program by programming in each process using a parallel program or the like. This source program may have potential bugs.

(2) Step B1: Section Setting By the section setting device 7, the designer divides each process of the first concurrent program into some sections (units). Here, the synchronization instruction in the first concurrent program is automatically set as a single section. Here, the section is a unit of process processing, and in the following steps, serialization and parallelization are performed in units of sections. In this case, the designer does not need to set the section. In this case, the section delimited by the synchronization command automatically becomes a section.

The section can be set by dividing the source code of the process and setting the section ID in each of the divided sections. As an example of source code division, as shown in FIG.
There is a method in which the processing from a break point to the next break point is a section. Here, as described above, the break points are automatically inserted before and after the synchronization command.

(3) Step A2: Serialization Based on the serialization rule, the serialization device serializes the first concurrent program. As an example of the serialization rule,
There is a method to introduce priority to the process. If executed based on this priority, since there is no nondeterminism at the time of execution, it can be regarded as a hyper-sequential program. A program serialized while having program information about the parallel structure in this way is called a hyper-sequential program. As an example of the serialization method, there is a method based on "process priority". According to this method, a fixed priority is set in advance for a process, and priority is given to execution of a section of a process having a high priority, whereby a sequential execution order without nondeterminism can be obtained. As an example of another serialization method, FIG.
As shown in FIG. 1, there are a "method of giving priority to execution of the synchronous instruction on the wait side (serialization rule 1)" and a "method of giving priority to execution of the synchronous instruction on the send side (serial rule 2)". Here, the hyper-sequential program is composed of three types of program information, that is, section information, program structure information, and serialization information. The section information is information on the section identifier (ID) and the source code to which the section belongs. The program structure information is information on the execution order of sections for each process in the original concurrent program, and information on data dependence between sections of different processes. The serialization information is global section execution order information by serialization, and at the same time, has information on good concurrency. As an example, there is a method of expressing serialization information by a Petri net, which is a modeling method of a parallel system.

(4) Step A3: Test / Debug of Hyper Sequential Program The hyper serial program is tested by the test execution unit 15, and if there is a bug, debug / correction is performed by the correction unit 9.
Make corrections. Further, when the modification of the program extends to the change of the parallel structure such as the synchronous instruction, the process returns to step A1, the modeling is performed by the program creating device 8, and the section setting and the serialization are performed again. Here, since the program 6 is serialized, test / debug becomes as easy as a sequential program.

(5) Step A4: Introduction of Good Nondeterminism to Hypersequential Program The nondeterminism introducing device 17 shows the structure of the hypersequential program on the output device 5. The designer can explicitly introduce good nondeterministic concurrency into the nondeterministic introducing device 17 while viewing this structure. At this time, the program information of the hyper-sequential program extracted by the analysis device 10 assists the designer in introducing good nondeterminism. If it is not necessary to introduce good nondeterminism, the process proceeds to step B2. As a method of introducing good nondeterminism, for example, when the serialization information of the hyper-sequential program is represented by a Petri net, the good nondeterminism is introduced by rewriting the Petri net within the range in which the program structure is preserved.

(6) Step A5: Test / Debug For a hyper sequential program in which good nondeterminism is introduced,
Similar to step A3, the test execution device 15 performs a test, and if there is a bug, the correction device 9 performs test / debug. Further, when the modification of the program extends to the modification of the parallel structure such as the synchronous instruction, the process returns to step A1, the modification is performed by the program creating device, and the section setting and the serialization are performed again. Here, with respect to the part in which the parallelization is introduced in the program 6, the parallel execution is performed. In this case, if the serialization information of the hyper-sequential program is represented by a Petri net, by executing the section corresponding to the place with the token using the Petri net simulator, the hyper-sequential The test execution of the program can be realized.

(7) Step A6: Introduction / Expansion of Good Nondeterminism to Partial Hyper-Sequential Program Information about good non-determinism is added to the hyper-sequential program tested and debugged in Step A5. Steps A5 to A6 are repeated a predetermined number of times to gradually expand the good nondeterminism. If it is necessary to introduce better nondeterminism, the nondeterminism introducing device 17 adds parallelism as in step A5, and the process returns to step A6. If there is no need, go to step B2.

(8) Step B2: Automatic parallelization For the hyper-sequential program for which good nondeterminism has been introduced by the designer, the parts that can be parallelized by the analysis information 12 of the hyper-sequential program extracted by the analyzer 10. Is automatically extracted, and the parallelization device 18 automatically expands the parallelism of the hyper-sequential program using the parallelization rule. The parallelization rule is as follows, for example. From the program information, the analysis apparatus 10 can extract the preceding constraint based on the data dependency and the control dependency, and can parallelize the sections having no preceding constraint. This parallelization process can be performed by applying a predetermined parallelization rule. As an example of the parallelization rule, there is a serialization information rewriting rule by a Petri net as shown in FIG. The data dependency and the control dependency are known.

(9) Step B3: Creation of Concurrent Program In the parallelizer 18, a parallel program 15 in which the program information of the hyper sequential program is reflected in the source code for the hyper sequential program whose parallelism is automatically expanded
Generate

In general, test / debug of a parallel program is a very difficult task as compared with a sequential program.
This is because, due to the non-determination of the program due to concurrency, the program may behave unintended by the designer at some timing. In testing / debugging a concurrent program, bugs due to concurrency (bad non-determinism) that the designer does not intend are found and removed one by one in the test. However, with this method, it is very difficult to completely eliminate the bug, and further labor is required.

In the hyper-sequential programming of the present invention, a concurrent program is first serialized, the concurrency intended by the designer is gradually introduced, and finally the part that can be automatically parallelized is parallelized. To restore.

That is, the hyper-sequential programming of the present invention does not remove bad non-determinism from a concurrent program, but introduces good non-determinism into a serial program. As described above, in super-sequential programming, a concurrent program is created from a sequential program in a bottom-up manner, so there is no room for bugs that occur at unexpected timings, and a very reliable program can be created. . It also makes testing and debugging much easier. In serial programming, performance deterioration due to serialization is a concern, but FORTR in the field of supercomputers etc.
Since automatic parallelization technology for sequential programs such as AN can be used, there are practically no problems in many cases. Although the basic configuration and operation of the second embodiment have been described, a specific example of the second embodiment will be shown below. (A) First Specific Example FIG. 13 shows an example of a parallel program. Here, P1 and P2 are processes that move in parallel. Also, P1 and P2
Is accessing the shared memory M.

(1) Step A1: Modeling The parallel program P is described as shown in FIG.

(2) Step B1: Setting of Section In this case, it is considered that each instruction forms one section. For simplicity, the section ID is the command itself.

(3) Step A2: Serialization The serialization is performed by introducing the process priority. Specifically, P1 >> P2 (P1 has priority over P2). At this time, the execution order of the serialized sections is
It looks like this: init1 → read1 → write1 → read2 →
The hyper2 serial program generated by the write2 serialization is composed of section information, program structure information, and hyperserialization information, as shown in FIG. Here, the serialization information is a representation of the above execution order by a Petri net.

(4) Step A3: Test / Debug of Hyper Sequential Program The hyper sequential program is executed, and if there is a bug, the source code of each section of the section or the original concurrent program is corrected. Here, it is assumed that there is no bug.

(5) Step A4: Introduction of Good Nondeterminism to Hyper-Sequential Program A Petri net of serialization information is displayed on a display device, and the serial relationship is cut to perform parallelization. Here, w
The sequential relationship between write1 and read2 is cut (FIG. 16 (a)). Since write1 and read2 have no execution order relationship in the program structure information, they can be disconnected. Here, guidance information regarding which sequential relationship should be disconnected can be provided based on analysis information 20 described later.

(6) Step A5: Test / Debug The hyper-sequential program in which concurrency is introduced is test-executed. Here, init1 → read1 → write1 → read2 →
write2 init1 → read1 → read2 → write1 →
Execution like write2 is possible. If there is a bug as a result of execution, fix it. Here, it is assumed that there is no bug.

(7) Step B2: Automatic parallelization From the data dependency relationship between the serialization information of the hyper-sequential program and the program information, the analysis information 20 provides the preceding constraint between sections. This precedence constraint is the analysis information 20. The preceding constraint is a constraint on the execution order between the sections having a data dependency relationship. That is, since the calculation result may change depending on the execution order between the sections having the data dependence, it is necessary to maintain the order defined by the serialization information. The preceding constraints here are the following three. init1 → read2 init1 → write2 read1 → write2 For example, the value read by P1 as read1 is wr of P2.
Affected by whether ite2 occurs before or after read1. For sequential information, read1 → wri
Since it is te2, this becomes the preceding constraint. The section without the preceding constraint can be parallelized and can be automatically parallelized by the parallelization rule. here,
Since read1 and read2 have no preceding constraint, parallelization rule 1 (FIG. 12) could be applied (FIG. 16 (b)).

(8) Step B3: Creation of Concurrent Program Source code of the parallel program is generated from the sequential programming with automatic parallelization. In this example, FIG.
The synchronization instructions (send, wait) for realizing the serialization information 1 and the serialization information 2 in step 1 are embedded in the source code.
The other serialization information is serialization information (execution order) held by the original parallel program. The converted program is as shown in FIG. This parallel program is executed on the parallel computer having the structure shown in FIG. (B) Second Concrete Example A second concrete example shows a procedure of hyper-sequential programming when a concurrent program has a synchronous instruction, a loop structure, and a conditional branch.

(1) Step A1: Modeling and step B2: Section setting is omitted, and a parallel program having a section execution order (program structure information) as shown in FIG. 18 is given. Here, the synchronization command (send, wait) and the data dependency (S13 and S)
22), there is a loop structure and conditional branching.

(2) Step A2: Serialization is performed by introducing a priority (P1 has a higher priority than P2; that is, P1 >> P2) into the serialization process. The result of serialization is shown in FIG. That is, the hyper-sequential program has the program structure information and the serialization information of FIGS. 18 and 19, respectively (section information is omitted). It should be noted here that the process executed by the synchronization instruction is switched. For example, wai
By the t instruction, after execution of S12 of P1, S2 of P2
1 is being executed. The loop and branch structures are also represented by Petri nets.

(3) Step A3: Test / Debug of Hyper Sequential Program The hyper sequential program is executed, and if there is a bug, the source code of each section of the section or the original concurrent program is corrected. Here, it is assumed that there is no bug.

(4) Step A4: Introduction of Good Nondeterminism to Hyper-Sequential Program A Petri net of serialization information is displayed on a display device, and the serial relationship is broken to perform parallelization. In this example,
Suppose we didn't explicitly include good nondeterminism.

(5) Step B2: Automatic parallelization The preceding constraint between sections can be obtained from the data dependency relationship between the serialization information of the hyper sequential program and the program information.
Here, the only prior constraint is S22 → S13. Here, in the loop, a loop may occur in the preceding relationship. Here, attention is paid only to the preceding relationship in one loop. A section without a preceding constraint can be parallelized and can be automatically parallelized by a parallelization rule. In this example, the preceding relationship is S22 → S13.
Only the parallelization rule 1 and parallelization rule 2 in FIG.
Thus, FIG. 20 can be finally generated.

(6) Step B3: Conversion of Parallel Program As in the first specific example, a parallel program can be generated by embedding a synchronization instruction in the remaining serialization information.

(Third Embodiment) FIG. 21 is a diagram showing a schematic configuration of a parallel program creation support apparatus according to a third embodiment, and FIG. 22 is a flow chart showing a schematic procedure of a parallel program creation method according to the present embodiment. is there.

In this embodiment, the test execution device 401 and the test case storage unit 402 constitute the serialization device 12. Unlike the above-described embodiments, the serialization device 12 has no special serialization rule, and the serialization is performed randomly. That is, the log when randomly executed is regarded as a hyper sequential program. Hereinafter, this embodiment will be specifically described.

Creation of a parallel program in this embodiment is realized by the following procedure. Here, consider a simple parallel program as the first parallel program, which is composed of two processes P1 and P2 that operate independently.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Also, each process structure is determined. Furthermore,
A parallel program having a parallel structure is described as a source program by programming in the process using a parallel program or the like. This source program contains
Potential bugs may exist. Here, two processes P1 and P2 are programmed as shown in FIG.

(2) Step C1: Test The test execution unit 401 causes the test case storage unit 40 to
CP file storage unit 1
The first concurrent program from 1 is executed, the execution result is displayed on the output device 5, and the test is performed at random. here,
The execution log is log1 = job11 → job12 → job21 → job
It is assumed that it is b22.

(3) Step C2: Bug Judgment As a result of the test in Step C1, if there is no bug, the procedure proceeds to Step C4. If there is a bug, the execution log is stored in the execution log storage unit 403 and the procedure proceeds to Step C3. Here, if there is a bug, the process proceeds to step C3, but here, since there is no bug, the process proceeds to step C4.

(4) Step C3: Test / Debug The debug device 16 uses the output device 5 to find a bug based on the execution log stored in the execution log storage unit 403 and stores it in the CP file storage unit 11. The first
Fix concurrent programs and eliminate bugs. When the test / debug is completed, the process returns to step C1.

(5) Step C4: Accumulation of Execution Log If the result of the test in Step C1 is that there is no bug in Step C2, the execution log log1 is accumulated in the execution log database 404. The execution log is a hyper sequential execution sequence, and can be regarded as a special form of the hyper sequential program.

(6) Step C5: Judgment of Presence of Remaining Test Cases It is judged whether or not there are any test cases in the test case storage unit 402, and if any, the process returns to step C1 to continue the test, and the test cases remain. If not, the process proceeds to step A7. In this step, the test is continued by returning to step C1 in order to try another test case.
In the second test, it is assumed that the following execution log log2 is saved in the execution log database 404. log2 = job11 → job21 → job12 → job
b22 (7) Step A7: Generation of Concurrent Program From the first concurrent program stored in the CP file storage unit 11 and the execution log stored in the execution log database 404, only the paths passed in the test are executed. The parallel program is generated by the parallelization device 18 and stored in the second CP file storage unit 19.

In this step, the execution log database 4
A parallel program that executes only the two execution logs log1 and log2 saved in 04 is generated by the following procedure. (A) All execution logs are merged to generate a global state transition system GTS (Global Transition System) (FIG. 24 (a)). (B) Project GTS into two processes P1 and P2.
At this time, the synchronization command (job11-ok, job21-ok, for recognizing the behavior of the process of the other party and synchronizing)
job12-ok, job22-ok) are embedded. The generated programs are designated as P1 'and P2' (Fig. 24 (b)). (C) Since the synchronous instructions of P1 'and P2' have redundancy, this redundancy is removed. The final process after removing this redundancy is P1 ″ and P2 ″ (FIG. 24).
(C)).

According to the above procedure, the two processes P
A parallel program CP ″ composed of 1 ″ and P2 ″ can be generated. With this parallel program CP ″, execution log1 and log2 that are confirmed to work correctly in the test are possible, but a case without test, for example, log3 = job21 → job11 → job12 → job
b22 is never executed.

As described above, a case that has not been tested is never executed, so it can be said that this is a very safe program.

According to the third embodiment, programming of a parallel program can be performed with the same degree of difficulty as sequential programming, so that the user can not only test efficiently but also
Since the part that is not tested does not move, a side effect that can achieve extremely high reliability can be expected.

(Fourth Embodiment) FIG. 25 is a flow chart showing a schematic procedure of a parallel program creating method in the fourth embodiment.

(1) Step A1: Modeling (2) Step A2: Serialization (3) Step A3: Test / debug of hyper-sequential program The above steps A1 to A3 are the steps A shown in FIG.
The description is omitted because it is exactly the same as 1 to A3.

(4) Step A4: Introducing a good non-deterministic portion into the hyper-sequential program The user operates the non-deterministic introduction device 17 in a non-deterministic manner with respect to the hyper-sequential program tested and debugged in step A3. Specify the part (this is called the "good nondeterministic part"). The good non-deterministic part designated by the non-deterministic introduction device 17 is reflected in the hyper-sequential program as information about the good non-determinism (information about concurrency). This makes the hypersequential program a partial hypersequential program with good nondeterministic parts. A method of specifying a good non-deterministic part will be described later.

(5) Step A5: Test / Debug of Partial Hyper-Sequential Program The partial hyper-sequential program obtained in Step A4 is tested / debugged. That is, step A4
Test and debug a partial hyper-sequential program in which a good non-deterministic part is introduced. Here, when the partial hyper-sequential program is converted into the execution format and executed, step A4
Only the good non-deterministic part introduced in (1) is converted into the execution form of the parallel structure, and the part not introduced is converted into the execution form with the original sequential structure and executed. Then, based on this execution result, the hyper sequential program is tested and debugged. When the converted executable program does not operate properly, the good nondeterministic part introduced in the serial program before conversion is considered to be the part that should not be operated nondeterministically, and the parallelization is released. (6) Step A6: Expansion of Good Nondeterministic Part in Hyper Sequential Program Information about good nondeterminism is added to the partial hypersequential program that has been tested and debugged in step A5. Steps A4 to A6 are repeated a predetermined number of times to gradually expand the good nondeterministic portion.

(7) Step A7: Parallelization Compile The default seriality of the partial hyper sequential program managed by the meta-level default seriality is canceled (for example, serial information and parallel information are directly embedded in the source program itself). At this time, for the part of the partial hyper-sequential program where information about good nondeterminism was not introduced, the harmless nondeterministic part was extracted as much as possible, and the part was attempted to be parallelized. Increase the parallelism of hyper sequential programs. For example, the dependency relationship between the processes is analyzed for the portion where the information on good nondeterminism is not introduced, and the sequentiality of the portion of the source program corresponding to the portion analyzed without the dependency relationship is released. In addition, the harmless non-determination part is extracted in step A2.
It is performed by referring to the parallel information analyzed when serializing in.

Next, details of the parallel program creating method and the creating support apparatus according to the present embodiment will be described.

The present embodiment is characterized in that the use of the hyper-sequential graph displayed on the output device 5 makes it possible to visually introduce the nondeterministic portion. A hyper-sequential graph is a transition graph that represents the process processing sequence of a hyper-sequential program in which default seriality is introduced to a parallel program having a parallel structure. The display of the hyper-sequential graph is performed based on the serialization information. The serialization information is generated when the serialization device 12 converts a parallel program into a hyper-sequential program.

More specifically, the serialization information is a data string group called a process table having a predetermined field. FIG. 26 is a diagram showing the structure of the process table.

In FIG. 26, the name field F1 is
Holds a name that identifies an individual process. The pointer field F2 holds a pointer of a called process list table (not shown) that stores a name list of processes called from the process (hereinafter, called process). This called process list table is provided separately. The priority field F3 holds the priority of the process. Based on the program having the original parallel structure, the priority of this process is determined by the serializer 12 when a plurality of processes can be executed at a certain processing point, and the result is described in the field. The value of the priority buffer field F3 is changed by the nondeterminism introducing device 17, as described later. Therefore, the priority order buffer field F4 can return to the state before the change by holding the priority order before the change. The grouping information field F5 holds information for identifying each group when a specific node group is grouped, and is a process executed first among the process groups corresponding to the grouped node group. The name of is written.

The serialization device 12 in this embodiment will be described.

It is assumed that a parallel program as shown in FIG. 27 is read by the serializer 12. The serialization device 12 is
First, the parallel structure of a parallel program is analyzed. The parallel program shown in FIG. 27 is conceptually analyzed as having a parallel structure as shown in FIG. This analysis can be realized, for example, by using a tree structure search algorithm or the like. Then, the serialization device 12 writes the analysis result in the process table. Specifically, the serialization device 12
Introduces the default sequentiality by writing the priority in the priority field F3 of the process table shown in FIG. 26, and converts it into the hyper sequential program. That is, in FIG. 28, which of the process C and the process D is processed after the process B is processed depends on the system environment at that time. In such a case, the serialization device 12 uniquely determines the priority order according to a predetermined rule (serialization rule). Note that the predetermined rule includes, for example, a rule that the process is read in the order of reading, a rule that is determined by a random number, and the like, but it can be set by the user according to various circumstances. The hyper-sequential program in this embodiment is conceptually composed of a source program and serialization information for managing it at the meta level.

For example, in the above example, when it is determined that the process C is to be processed with priority over the process D according to the predetermined rule, "1" is set in the priority field F3 of the process C in the process table. Is written, and “2” is written in the priority field F3 of the process D in the process table. Note that the priority field F3 remains "0" for the process that does not need to determine the priority. This priority determination is performed between processes having the same hierarchical level. For example, the processes C, G, and I and the processes D, H, and J in FIG. 28 are processes at the same level, but the processes E and F therein are one level lower.

In this way, the serialization device 12 analyzes the parallel structure of the parallel program, generates serialization information (process table), and records this in a file.

FIG. 29 is a diagram showing the contents of the process table created as a result of analyzing the structure of the parallel program by the serializer 12. That is, FIG. 29 shows the contents of each field in each record corresponding to process A to process K. More specifically, the process called next to the process A is the process B, and the priority of the process A is 0. Further, for example, the process B indicates that the process to be called next is the process C or the process D, which means that the process C and the process D are essentially non-deterministic. And this process C and process D
Means that the serialization device 12 assigns priorities “1” and “2” respectively, and the process C is called (executed) with priority over the process D.

Introduction of information on good non-determinism (that is, a method for designating good non-determinism) will be described.
The introduction of the good non-deterministic part is performed by the interactive operation by the user using the non-deterministic introduction device 17 shown in FIG. That is, the non-deterministic device 17 displays the hyper-sequential graph on the output device 5, and the user uses the input device 4 to introduce / cancel a good non-deterministic part to the hyper-sequential graph.

FIG. 30 is a diagram showing an example of the hyper-sequential graph. In FIG. 30, each node represents each process,
The arc indicated by the dashed arrow represents the parallel structure of the original concurrent program. Also, the solid arrow indicates the serialization device 12.
Represents the sequential structure of the process determined by the introduction of the default sequentiality, and the execution order of the processes is sequentially numbered according to the sequential structure. That is, in the original concurrent program, the process C → G → I and the process D → E → F → H → J are originally described as being processed in parallel. In the program, the process C → G → I is processed in series, and then the process D and subsequent processes are processed.

The user can visually recognize such a hyper sequential graph by the output device 5. Further, after the serial program is serialized by the serialization device 12 and the serialization information is generated, the user gives an instruction to display a hyper-sequential graph, so that the output device 5 can visually grasp at any time. can do. In the present embodiment, the display of the hyper-sequential graph is performed by the hyper-sequential graph display control unit of the nondeterminism introducing device 17. The super-sequential graph display control unit starts displaying the super-sequential graph according to a predetermined built-in program when receiving an instruction from the user to display the super-sequential graph.

FIG. 31 is a functional block diagram showing the structure of the super sequential graph display control unit. The hyper-sequential graph display control unit determines, according to the serialization information stored in the serialization information storage unit 31, a node corresponding to each process, an arc for a parallel structure and a sequential structure indicating a calling relationship between the nodes, The image data generator 35 converts these into image data necessary for displaying on the output device 5.

The serialization information reading unit 32 reads the serialization information from the serialization information storage unit 31, and the parallel structure analysis unit 33
And to the sequential structure analysis unit 34.

Concurrent structure analysis unit 33 and sequential structure analysis unit 3
4 analyzes the parallel structure with reference to the serialization information. Specifically, the parallel structure analysis unit 33 uses the pointer field F
By referring to the called process list table designated by 2, the calling relationship between the process names that can be called by the process described in the name field F1 is specified. The sequential structure analyzing unit 34 specifies the sequential structure by referring to the priority described in the priority field F3 in addition to these fields. The analysis results by the parallel structure analysis unit 33 and the sequential structure analysis unit 34 are sent to the image data generation unit 35. Image data generator 35
Is based on these input analysis results, image data for displaying the node corresponding to each process, and two arcs for connecting the calling relationship between the processes (that is, arcs for the parallel structure and Image data for displaying the arc corresponding to the sequential structure is generated and sent to the output device 5. The output device 5 displays a transition graph (that is, a hyper sequential graph) based on these image data.

When the hyper sequential graph is displayed, each node of the sequential structure subordinately analyzed by the sequential structure analysis unit 34 is subordinate to the connection relation between the nodes of the parallel structure analyzed by the parallel structure analysis unit 33. It is desirable to generate image data by adding a connection relationship between them. In other words, the hyper-sequential graph is preferably a hyper-sequential graph that retains the parallel structure of the original concurrent program. As a result, the user can introduce a good nondeterministic portion into the serialized processing flow (process) while being aware of the parallel structure that the original concurrent program originally has.

When the hyper-sequential graph is displayed on the output device 5, the nondeterminism introducing device 17 in FIG. 2 is in a state of waiting for the input of a good nondeterminism part by the user. (Part) Since the nondeterministic part is not introduced at the beginning of the test / debug of the hyper sequential program, the arc for the sequential structure is provided for all the nodes on the output device 5, and the parallelization information is displayed. It has not been. Here, the parallelization information is information given to a node in which a good nondeterministic part is introduced, and is visually distinguished on the screen depending on whether or not the good nondeterministic part is introduced (for example, shadows). Density, color coding, etc.) is displayed. Also, this parallelization information is
Good non-deterministic parts that are hierarchized are also visually distinguished and displayed.

The introduction of a good non-deterministic part by the user is
This is performed using the input device 4. Although a specific method for introducing good nondeterminism will be described later, in brief, it is performed by cutting or connecting the connection relation (arc) of the sequential structure between the nodes using the input device 4. As a result, the serialization information changing unit 36 changes the contents of the serialization information storage unit 31. The changed contents are read again by the serialization information reading unit and displayed on the output device 5.

A specific operation example of introducing a good nondeterministic portion will be described.

FIG. 32 is a diagram for explaining a method of introducing a good nondeterministic portion.

When introducing a good nondeterminism between a plurality of processes, it is performed by successively designating a desired node corresponding to the process in the good nondeterminism introducing mode. The good non-deterministic introduction mode is selected by, for example, an instruction operation menu or the like, and shifts to the mode.

In FIG. 32, when the parallelization of the processes E and F is allowed, the nodes E and F are successively designated by the cursor P operated by the input device 4. The designated node is shaded so that it can be visually distinguished from other undesignated nodes. When the designation has been completed for all the target nodes, the user gives the nondeterminism introducing device 17 the completion. As a result, the serialization information changing unit 36 causes the serialization information storage unit 31 to store the priority field F of the corresponding process in the process table.
The current value of 3 is compared with the priority buffer field F4, and the value of the priority field F3 is set to "0".
Change to

That is, in this embodiment, the processes E and F are
The values "1" and "2" of the priority field F3 are compared with the priority buffer field F4, and the value of each priority field F3 is "0".
Is changed to. After updating the serialization information storage unit 31 by the serialization information changing unit 36, the hyper-sequential graph is displayed again on the output device 5. At this time, since there is no priority between the processes E and F, the corresponding arc of the sequential structure is not displayed. That is, it is confirmed that the processes E and F operate in parallel on the output device 5.

FIG. 33 is a diagram showing an example of the hyper-sequential graph in which the good non-decision part is introduced in the above case.

The program (partial hyper-sequential program) into which the good non-deterministic part is introduced as described above is converted into the execution form by the test execution device 15 and the test is executed. The user confirms whether or not the program operates properly based on the execution result by the test execution device 15. This operation check needs to be executed for all paths based on concurrency. When the test execution unit 15 does not operate correctly, the part in which the good non-deterministic part is introduced can be regarded as the part that does not allow the parallelization, so the user specifies the parallelization to be released.

The cancellation of parallelization is performed by specifying in the nondeterministic part cancellation mode in the same manner as in the case of introducing a good nondeterministic part. As a result, the serialization information changing unit 36 returns the value stored in the priority order buffer field F4 in the process table in the serialization information storage unit 31 to the priority order field F3.

In this embodiment, when introducing a good non-deterministic part, it is possible to group by hierarchy level. For example, since the group of processes C, G, and I (referred to as group 1) and the group of processes D, H, and J (referred to as group 2) are at the same hierarchical level, they can operate in parallel with each other. Therefore, if the individual processes are operated, the operability is insufficient, so it is effective to group these processes. This grouping is performed by selecting the grouping mode. Specifically, in the grouping mode, target nodes are sequentially selected and given the fact that the target nodes have been completed, so that the target nodes are grouped and displayed as one new node.

FIG. 34 is a diagram showing an example of a hyper-sequential graph having grouped nodes.

In FIG. 34, the nodes of groups 1 and 2 are displayed in, for example, an elliptical shape so that they can be visually distinguished from other ungrouped nodes. Further, the group 2 has a lower hierarchy (processes E and F).
Because it has, it is displayed with a shadow, for example. For such hyper-sequential graphs, the user can specify good non-deterministic parts. Even if a good nondeterministic part is introduced into such a grouped hyper-sequential graph, it is sufficient to change the priority field F3 of the leading process (processes C and D).

In order to introduce a good nondeterministic part into a node of a hyper-sequential graph, the desired node is directly specified by the input device 4 as described above, but this method is not The designation may be made by enclosing a specific node group or by causing the designated area to hang on the specific node group. Since there are many processes and many nodes corresponding to them, it can be assumed that it is difficult to confirm on the output device 5. Such a case can be dealt with by displaying only the grouped nodes.

In this embodiment, the priority order among the processes determined by the serializer 12 can be changed. That is, in the priority order changing mode, the priority order among the targeted nodes is changed by designating a desired node.

With respect to the hyper-sequential graph of FIG. 32, it is assumed that the priorities of processes E and F are changed in the priority change mode. The user designates the nodes E and F by the input device 4 as described above, and gives the non-determinacy introducing device 17 the designation completion. As a result, the serialization information changing unit 36 sets the value of the priority field F3 of the process E to “2” and the value of the priority field F3 of the process F to “1” in the process table in the serialization information storage unit 31. change. As a result, a new hyper sequential graph is displayed on the output device 5. FIG. 35 shows
It is a figure which shows an example of the hyper sequential graph at this time. As shown in FIG. 35, after the priority order is changed, the arc for the sequential structure is changed.

The change of the priority order of such a process is as follows.
Since the behavior between processes intended by the user is guaranteed,
It can be useful for introducing good non-deterministic parts. That is, first, the user converts the hyper-sequential program shown in FIG. 32 into the execution format by the test execution device 15, and executes the test. Next, the user similarly performs the test execution on the hyper-sequential graph of FIG. 35 after the priority change.
If it is confirmed by this that both test execution results are intended by the user, either process E or process F can be considered to execute either one first. Therefore, a good nondeterministic part should be introduced. You can

In this embodiment, the introduction of nondeterminism between two processes has been described, but the same applies to the case of three or more processes.

FIG. 36 is a diagram for explaining the introduction of a good nondeterministic portion between the three processes. Although it is possible to allow parallelization for all of the processes B, C, and D of the parallel structure, in FIG.
The case where parallelization is allowed only between processes B and C is shown. By introducing such a good nondeterministic part, the hypersequential graph becomes as shown in FIG. That is, the hyper-sequential graph shown in FIG. 37 shows that the process D is executed after both the processes B and C are executed. As described above, according to the present embodiment, since the parallelization information and the serialization information are presented to the user at the same time by the hyper-sequential graph displayed on the output device 5, the user considers the original parallel structure. , Will be able to specify a good non-deterministic part. Also, rather than specifying / releasing a good non-deterministic part at the concurrent program description level, specifying / releasing a good non-deterministic part for a hyper-sequential graph makes it easy to use without requiring advanced parallel programming technology. You will be able to develop concurrent programs.

(Embodiment 5) FIG. 38 is a block diagram of a concurrent program generation / creating support apparatus according to this embodiment, and particularly shows the HSP file storage unit 14 and the nondeterminism introducing apparatus 17 in FIG. 2 in detail.

In FIG. 38, the CP file storage unit 11
The first concurrent program stored in is the serialization device 1
2, the serialized program is serialized as in the previous embodiment, and the obtained hyper-sequential program is stored in the serialized process list storage unit 51 in the HSP file storage unit 14. Note that, when the hyper-sequential program is stored in the serialization process list storage unit 51 by a debug device (not shown in FIG. 38), bugs in the serialized state have been removed.

The hyper-sequential program (serialization process) generated here is converted into field data by the field data generation unit 53, and the field data storage unit 5
Stored in 2. These serialization process list storage unit 5
1 and the information in the field data storage unit 52 are stored in the HSP file storage unit 14 which is an intermediate file. The field data from the field data storage unit 52 is used for editing by the field editor 55 via the field tuning unit 54.

The non-determinism introducing device 17 is composed of a field data generating section 53, a field tuning section 54 and a field editor 55. The field data edited by the field editor 55 is converted into a parallel program corrected by the parallelization device 18 (field data conversion unit) and stored in the second CP file storage unit 19.

FIG. 39 shows an example of the first parallel program stored in the CP file storage unit 11 in FIG. 38, and bugs are intentionally included for convenience of explanation. Here, as a bug, it is assumed that the parallel execution of the processes P4 and P5 is incorrect, and conversely, the processes P2 and P6 can be executed in parallel, and the correct parallel program is shown in FIG. 66 described later. FIG. 40 is a diagram imagining the flow of processes executed by the first parallel program of FIG. 39, in which processes P4 and P5 and processes P7 and P8 are executed in parallel. FIG. 41 is an example of the serialization process stored in the serialization process list storage unit 51 in FIG. 38. In the serialization device 12, a certain order is assigned to the parallel part in the first concurrent program of FIG. 39. Has been serialized in.

Further, FIG. 42 is a diagram imagining the flow of the process executed in FIG. In this example, P
Since it is serialized in the order of 4, P5, the bug related to this point has been removed. If the serialization was performed in the order of P5 and P4, the above bug should be detected by the conventional debug method, and the wrong parallelization (bad nondeterminism) should be removed at the time of serialization. You can

FIG. 43 is a flow chart showing the flow of processing executed by the field data generator 53 shown in FIG. Here, the process progressing from one process to another process is regarded as a range (area) where certain constraints and transition conditions exist, and a hyper-sequential program (serialization process) is converted into field data. As shown in FIG. 43, a start area is generated in step D1, and steps D3 to D9 are repeatedly executed until the final process comes. Then, when the final process comes, the processes of steps E10 to E12 are performed and the process ends. FIG.
4 shows a general area data structure generated by the processing shown in FIG. A field is formed as an overall structure composed of connections in this area.

The following information is described in area A (i). (1) As long as you are in area A (i), there are constraints described in "constraint". (For example, P (x1) is P
(Executed before (x2)) (2) The transition condition for moving from area A (i) to another area is described in "transition". (For example,
(P (z1) can be completed and transit to A (j)) (3) The area that can be transited from area A (i) is A (j). (4) The state before moving to area A (i) is area A
(K).

FIG. 45 is obtained by the processing shown in FIG.
1 shows a state in which the program described in 1 is converted into a field composed of a set of areas.

This field has the strongest constraint on the processing order relation. The introduction of non-determinism can change this constraint,
It can be done by losing it. In other words, introduce nondeterminism by performing field tuning,
Parallelization can be achieved. Note that since the tuning is generally performed by constraints, the constraints and transition conditions are displayed to the user.

FIG. 46 is a flowchart of the processing executed by the field tuning unit 54 shown in FIG.

In the field data selected in step E1, the connection information between the areas is analyzed in step E2 to visually generate a field, which is displayed in the field editor 55. The user can tune the field by inputting a command in step E3 while looking at the screen of the field editor 55.

At step E5, the field being edited can be saved, and if the editing is completed, the process goes to step E17 and ends. Incidentally, in steps E14 to E16, the contradiction of the constraint due to the editing is detected.

Step E9 is a subroutine relating to constraint rewriting processing. Further, step E11 is a subroutine relating to the process of adding a constraint. Then, step E13 is a subroutine relating to the constraint deletion processing.

FIG. 47 is a subroutine for performing the processing of step E9 in FIG.

Regarding the constraint edited in step E9-1, it is checked in step E9-2 whether or not there is a trivial constraint, and if there is a trivial constraint, the user is informed that there is an error in rewriting the constraint in step E9-2. In step E9-10, rewriting is invalidated. If there is no obvious constraint, the field is rewritten as in step E9-4. Then, steps E9-5 to E9-8
Check the field with.

FIG. 48 is a diagram showing field changes caused by the constraint modification operation algorithm of step E9-4 in FIG. This is "before Pi Pj"
Shows the situation when is changed to "before Pl Pj",
The field changes from (a) to (b) in FIG.
Here, the area of A (y) is "next" of area A (a).
, And the attributes of each area change accordingly.

FIG. 49 shows a subroutine for performing the process of step E11 in FIG. Step E11-1
With respect to the constraint edited in step E11-2, it is checked in step E11-2 whether or not there is a trivial constraint, and if there is a trivial constraint,
At step E11-9, the user is informed that there is an error in rewriting the constraint, and the addition is invalidated at step E11-10. If there is no obvious constraint, the field is rewritten as in step E11-4. And
Field check is performed in steps E11-5 to E11-8.

FIG. 50 shows step E11- in FIG.
It is the figure which showed the change of the field which arises by the algorithm of the addition operation of the restrictions of 4. Area A here
FIG. 50 shows a state in which "before Pj Pk" is added to (y), and the field changes from FIG. 50 (a) to (b). Here, the area A (y) is newly added to area A.
It is added to the next of (x2), and the attribute of each area changes accordingly.

FIG. 51 is a subroutine for performing the processing of step E13 in FIG.

Since at least one constraint is required for the area, area A specified in step E13-1
Check the number of constraints of (y), and if there is one, step E1
An error message is displayed in 3-8 and the process ends. if,
If there are multiple constraints, delete the constraint specified by the user,
The field is rewritten as in step E13-3.
Then, the fields are checked in steps E13-4 to E11-7 to prevent the occurrence of obvious restrictions.

FIG. 52 shows a step E13 in FIG.
FIG. 6 is a diagram showing a change in a field caused by an algorithm of a constraint deletion operation of (1).

This shows a state in which "before Pj Pk" is deleted, and the field changes from FIG. 52 (a) to (b). Here, the area of A (x2) is connected to the "pre" of the area A (z), and the attribute of each area changes accordingly.

FIG. 53 is a process for detecting a trivial constraint that causes a contradiction in a field. E9-2 and E in FIG.
9-5, E11-2 and E12-5 of FIG. 49, and E of FIG.
13-4 is a subroutine commonly executed. Here, for example, even if "before AB" and "before BC" exist, an obvious constraint such as "before AC" is detected.

In FIG. 53, the trivial constraint is generated by repeating E9-3 to E9-2-6, and it is realized by searching the common element with the constraint set at E9-2-7. For example, assuming a field including the obvious constraint “before AD” as shown in FIG.
The processing is executed in the order of the temporary set (a), the temporary set (b), and the temporary set (c) of No. 5, and the common element "before AD" can be detected.

FIG. 56 shows a display screen of the field editor 55. In the field editor 55, reading, saving, constraint editing, change of display mode, etc. of fields can be performed by designating the menu 71. When an area 72 represented by a square is selected, an editing screen 73 appears. FIG. 57 shows a display example of fields when “2D display mode” is selected as the display mode. In this mode,
The field is displayed in a plane. FIG. 58 shows a display example of fields when “3D display mode” is selected as the display mode. In this mode, the fields are displayed three-dimensionally, and it is possible to make it easy to overlook the whole even when the whole becomes large or there are many parallel processing parts.

59 to 66 show how the field data shown in FIG. 44 is tuned by the algorithm shown in FIG. 46.

In FIG. 59, for example, it is assumed that the user has no causal relationship between P5 and P6, and that P6 does not make a bad non-deterministic movement that becomes a bug even after P2. in this case,
When editing is performed to rewrite the constraint as shown in FIG. 59, the display is as shown in FIG. In FIG. 60, it is assumed that there is no causal relationship between P6 and P4, for example, and it is determined that P4 and P3 have the correct order. In this case,
When editing is performed to delete a certain constraint ("before P6 P4") as shown in 0, the display is as shown in FIG. Similarly, when the user examines the restrictions in the area and gradually edits the field data, the field data will be changed from FIG. 62 to FIG. 63.
→→ Changes as shown in FIG. 66.

FIG. 67 is a flow chart showing the process executed by the parallelization device (field data conversion unit) 18 in FIG. As shown in FIG. 67, the parallelization device 18 reads field data from the field data storage unit 52 (step F1), analyzes the graph structure between the areas, and generates a process flow (step F).
2) Further, the process flow is analyzed to generate a source of the parallel program in a form in which only nondeterminism is introduced (S step F3), and the source is stored in the second CP file storage unit 19 (step F4).

FIG. 68 shows a parallel program obtained by analyzing and converting the field in the state of FIG. 66 by the parallelization device 18. As shown in FIG. 68, the parallel execution of the bugs P4 and P5 assumed in the first concurrent program of FIG. 39 is corrected, and conversely, P3 and P6 of good nondeterminism are fixed.
Parallelization is being done.

Further, FIG. 69 is an image showing the flow of processes executed by the parallel program of FIG.

According to this embodiment, the process flow of a serialized concurrent program is regarded as a concept of a field consisting of constraints and transition conditions, and this field is tuned to introduce good nondeterminism. It is possible to efficiently generate high-quality concurrent programs without bugs. Further, in this embodiment, when the serialized program removes the constraint and the parallelization progresses, the graphically long and narrow field grows in the vertical direction, which is intuitive and easy to understand. There is an advantage that it becomes easy.

(Sixth Embodiment) In the parallel program creation method and creation support apparatus according to the present embodiment, the test / debug is performed on the hyper sequential program. We also introduce information about good nondeterminism into hypersequential programs.

FIG. 70 is a diagram showing a schematic configuration of a parallel program creation support apparatus according to the sixth embodiment. In FIG. 70, the first parallel program stored in the CP file storage unit 11 is extracted by a user's instruction from the input device 4 and input to the serialization device 12. Serialization device 1
The first parallel program input to 2 is converted into a complete hyper-sequential program HSP according to the serialization rule stored in the serialization rule storage unit 13, and stored in the HSP file storage unit 14 capable of storing a plurality of complete hyper-sequential programs. Will be recorded.

A test is executed by the test execution unit 15 on the completely hyper sequential program HSP. here,
If there is a bug, the complete hyper sequential program H stored in the HSP file storage unit 14 using the debug device 16
Modify SP. Once the test debug is complete,
Complete hyper sequential program HSP HSP file storage unit 1
Save to 4.

Next, the nondeterministic introduction device 17 changes the change device 2
The execution order of the perfect hyper-sequential program HSP is changed via 5 to generate another perfect hyper-sequential program HSP. While repeating the same test and debug for this complete hyper sequential program HSP, complete hyper sequential program HSP
The SP is accumulated in the HSP file storage unit 14. That is, instead of expressing good nondeterminism as one partial hypersequential program, it is expressed as a plurality of complete hypersequential programs. When the good non-deterministic introduction is completed by the non-deterministic introduction device 17, the complete hyper-sequential program HS finally stored in the HSP file storage unit 14 is completed.
A parallel program is generated from the set of P by the parallelization device 18 and stored in the second CP file storage unit 19.

(Seventh Embodiment) In the present embodiment, the configuration of the parallel program creation support device is the same as that of the sixth embodiment (FIG. 70), and the parallel program creation procedure is different, so that the illustration is omitted. FIG. 71 is a flow chart for explaining the outline procedure of the parallel program creating method in the present embodiment.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Also, each process structure is determined. Furthermore,
A parallel program having a parallel structure is described as a source program by programming in the process using a parallel program or the like. This source program contains
Potential bugs may exist. (2) Step A2: Serialization A default program is introduced to convert a parallel program into a hyperstructured program with a sequential structure. In this example, default seriality is introduced at the meta level. Here, the meta level does not mean the level of the source program itself, but the level of managing the execution of the source program. For example, a source program written in a parallel program is converted into a source program of a program guaranteed to be sequentially executed by a scheduler managed separately from the source program.

(3) Step A3: Test / Debug of Hyper Sequential Program For the hyper sequential program converted in Step A2,
Test and debug. That is, based on the result of test execution of sequential programs by the test execution device,
The debugging device removes bugs from the hyper sequential program. The test / debug here can be performed in the same manner as the normal test / debug method in the sequential program. This test and debug is performed until it is guaranteed that the hyper sequential program operates normally.

(4) Step G1: Parallel Simulated Program Creation A process group that is a candidate for parallelization is introduced into the hyper sequential program that has been tested and debugged in Step A3, and a plurality of parallel simulated operations are performed by the change device 20. Generate a series. In this embodiment, a parallel simulated operation sequence is introduced at the meta level.

(5) Step G2: Execution / Confirmation of Parallel Simulated Operation Sequence The parallel simulated operation sequence obtained in Step G1 is processed in Step A.
Execute using the hyper-sequential program that was tested and debugged in 3 and confirm the execution result. This execution simulates the situation in which the programs operate in parallel on the hyper sequential program. The user records in the parallel simulation execution device whether or not each operation result is correct.

(6) Step G3: Partial serialization by selection of good non-determinism From the execution result of step G2, a non-determined process that allows a correctly executed parallel simulated motion sequence and excludes an incorrectly executed parallel simulated motion sequence Introduce sex and register as good nondeterminism. The processes of steps G1 to G3 are repeated a predetermined number of times to gradually expand the range of good nondeterminism.

(7) Step A7: Parallelization Compile A harmless nondeterministic part is extracted from the partial hypersequential program with good nondeterminism introduced, and the part is parallelized to generate the partial hypersequential program as a whole. Convert to a concurrent program. That is, with respect to the portion where the information about parallelization is not introduced, the default seriality is reflected in the concurrent program (for example, embedded in the source program itself) to cancel the meta-level default seriality.

FIG. 72 shows an example of a concurrent program model which the user has assumed. Here, P1, P2, P3, etc. represent units in which the program is executed, and these are called processes. In the example shown in the figure, the processes P3, P4, and P5 are executed in parallel as intended by the user, and the process P
7, P8 and P9 indicate that they are sequentially executed. Furthermore, the process group including the processes P2, P3, P4, P5, and P6 and the process group including the processes P7, P8, and P9 can be executed in parallel.

The hyper-sequential program HSP is the serialization device 1
According to 2, all processes can be obtained by arranging them in a line so long as the context of the processes in the parallel model is not broken.

FIG. 73 shows an example in which the execution sequence of the hyper sequential program HSP obtained from the parallel program of FIG. 72 is modeled. In this way, in the serialization model, the processes P3, P4, P5, etc. that are executed in parallel are placed in an arbitrary order and in some cases separated positions, but the processes P1, P2 to be executed earlier than these are , Processes P3, P
Processes P6 and P10 which are to be placed before any of P4 and P5 and to be executed after these are
It is placed after any of 3, P4, and P5. Similarly,
When the program group including the processes P2, P3, P4, P5, and P6 and the program group including the processes P7, P8, and P9 are serialized, the context between the groups is arbitrary, and in some cases, the processes of both groups are processed. May appear alternately on the model.

The super-sequential program HSP is input to the test execution device 15 according to an instruction from the input device 4 by the user, and the test execution is performed. Test execution device 15
Presents the result of the test execution on the output device. The user can perform a predetermined test / debug using the input device 4 on the hyper sequential program HSP based on the result of the test execution. Further, the user gives a test execution instruction from the input device 4 again after performing a predetermined test / debug on the hyper sequential program HSP. As a result, the hyper-sequential program HSP subjected to the test / debug is input to the test execution device 15 and the test execution is performed again. This test / debug is repeated until it is confirmed that the program HSP operates normally.

When the normal operation is confirmed by the test / debug, the non-deterministic input device 17 converts the hyper sequential program into a partial sequential program. First,
Converts a hyper sequential program into multiple concurrent simulation programs and accumulates information about good nondeterminism from the execution results of the concurrent simulation programs. This procedure is shown in FIG. 75 to 78 show specific examples of the process of converting the sequential model of FIG. 73 into a parallel simulation model and obtaining a partial sequential model according to the procedure shown in FIG. 74.

The procedure of this example will be described below.

In FIG. 75 (a), P3, P4, and P5 are selected as parallel simulation ranges by a pointing device or the like (step H1). Further, each process is independently designated as a parallelization unit (step H2). Fig. 75
Then, the parallelization units are distinguished by the difference in color. In the hyper sequential program, the processes are executed in the order of P3, P4, and P5 within this parallel simulation range.

In FIG. 75 (b), P4 and P5 are replaced as replacement of the parallelization unit (step H3), and one parallel simulated motion sequence is obtained. In this parallel simulation operation sequence, the processes are P3, P within the parallel simulation range.
5 and P4 are executed in this order. When this program is executed and the execution result is guaranteed (step H4), FIG.
A program like (c) is obtained (step H
5). In this partial sequential program, after the process P3 is executed within the parallel simulation range, P4 and P5 are executed in parallel.

Further, when the user instructs the expansion of nondeterminism within the same range (step H6), FIG.
In (a), a single process P3 and a set P of two processes P
4 & P5 is replaced (step H3), and another parallel simulated motion sequence is acquired. In this parallel simulation operation sequence, the process executes P3 after P4 and P5 are executed in parallel within the parallel simulation range. When this program is executed and the correctness is confirmed (step H4), a program having nondeterminism as shown in FIG. 76 (b) is acquired (step H5). In this partial sequential program,
The processes P3, P4, and P5 are executed in parallel within the parallel simulation range. As a result, the nondeterminism within this parallel simulation range is sufficient, so that the process proceeds from step H6 to step H7, and when the user instructs the expansion of the parallel range (step H7), as shown in FIGS. 77 to 78. To
Returning to step H1, the same processing is repeated.

Partial sequential program PHSP obtained by incrementally introducing information about good nondeterminism
Is input to the parallelization device 18 according to an instruction from the user. In the parallelization device 18, the partial sequential program PHSP having only good nondeterminism is recorded in the second CP file storage unit 19 as the parallel program CP. The user can see the program CP by the output device 5 and can perform final test / debug.

According to this embodiment, the operation of the parallel program can be sufficiently confirmed on the hyper sequential program.
Further, by designating a range that is a candidate for parallelization with respect to the hyper-sequential program, the hyper-sequential program can be converted into a parallel program stepwise. Furthermore, by introducing concurrency that allows only non-determinism that is confirmed to operate correctly by sequential execution based on the parallel simulated operation sequence,
You can get a concurrent program that works correctly. This has the advantage of making it easier to test and debug concurrent programs.

(Embodiment 8) In this embodiment, in the computer system configured as shown in FIG. 1, at least one process A to D is provided to each processor 1-1 to 1-N as shown in FIG. Is registered, each process is operating in parallel / parallel, and an example in which a parallel program is created in a process execution environment in which information is exchanged while exchanging messages with each other to perform processing.

In this embodiment, the test of the parallel program is performed on the hyper-sequential program. However, if there is a bug, the serial program is not modified, and the serialization rule is modified to perform the test / debug. I do.

FIG. 80 is a diagram showing the schematic structure of a parallel program creation support apparatus according to this embodiment.

In FIG. 80, the CP file storage unit 11
The first concurrent program stored in is the serialization device 1
In accordance with the serialization rule stored in the serialization rule storage unit 13 in 2, the default seriality is introduced at the meta level, so that the hyper sequential program (HSP)
And is recorded in the HSP file storage unit 14.
Here, the serialization rule becomes the execution log information obtained when the source program (CP file) is executed by the execution device 22, and the HSP file storage unit 14 is composed of a pair of the CP file and the execution log information which is the serialization rule. Become. The user can see the hyper sequential program HSP by the output device 5. This super sequential program HSP is
The user inputs an instruction from the input device 4 to the test execution device 15, and the test is executed.

The test execution device 15 presents the result of the test execution (execution log) to the output device 5. The user uses the serialization rule correction device 2 based on the result of this test execution.
6 can be used to modify the serialization rule stored in the serialization rule storage unit 13 to perform predetermined test / debug on the hyper-sequential program HSP.

By modifying the serialization rule in this way, the user can perform a predetermined test on the hyper sequential program HSP.
After performing the debugging, the test execution instruction is given again from the input device 4. As a result, the hyper-sequential program HSP subjected to the test / debug is input to the test execution device 15 and the test execution is performed again. This test / debug is repeated until it is confirmed that the hyper sequential program HSP operates normally.

Then, in the present embodiment, when it is confirmed by the test / debug that the operation is normal, the serialization rule correction device 26 corrects the serialization rule stored in the serialization rule storage unit 13. The corrected serialization rule is newly recorded in the serialization rule storage unit 13. This modification of the serialization rules partially introduces information about good nondeterminism into hypersequential programs. The hyper sequential program HSP is converted into a partial hyper sequential program PHSP.

Next, the partial hyper-sequential program PHSP is
To uncover potentially harmless concurrency,
The second parallel program 19 that divides the serialization rule in the partial hyper-sequential program PHSP into each process in the parallelization device 18 based on an instruction from the division reference designating device 23 and enables the activation order control of each process. Convert to.

FIG. 81 is a view for explaining the schematic procedure of the parallel program creating method according to the present embodiment.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Also, each process structure is determined. Furthermore,
The first parallel program having a parallel structure is described as a source program by programming in the process using a parallel program or the like. This source program may have potential bugs.

(2) Step A2: Serialization By introducing default seriality, the first concurrent program is converted into a hyperstructured program having a sequential structure. In this example, default seriality is introduced at the meta level. Here, the meta level does not mean the level of the source program itself, but the level of managing the execution of the source program. For example, it means to sequentially execute the first parallel program described in the parallel program by a scheduler managed separately from the first parallel program. That is, the term “serialization” here means associating the CP file storage unit 11 and the serialization rule storage unit 13. Therefore, the obtained hyper sequential program is the first
It consists of a pair of concurrent programs and serialization rules.

(3) Step A3: Test / Debug of Hyper Sequential Program The hyper serial program serialized in step A2 is executed and tested. The test execution at this time means operating the first concurrent program based on the serialization rule. If there is a functional bug, the first concurrent program is modified and the process returns to step A2. If there is a timing bug, the process moves to step J1. If there is no timing bug, the serialization rule is saved and the process proceeds to step A4.

(4) Step J1: Correction of Serialization Rule If there is a timing bug in step A3, the serialization rule is corrected, and then the process returns to step A2.

(5) Step A4: Introduction of Good Nondeterminism When it is necessary to add good nondeterminism, after correcting the serialization rule, the process returns to step A2. If it is not necessary to add good nondeterminism, the process proceeds to step A7.

(6) Step A7: Parallelization Compile The harmless nondeterministic part is extracted from the serialization rule saved in step A3, and the part is parallelized, whereby the entire partial hypersequential program is converted into the second parallel program. Convert to.

FIG. 82 is a diagram showing an example of log information which is an execution history as a result of execution of a parallel program with inter-process communication as shown in FIG. 79 by introducing default seriality at the meta level.

The user can see this log information by the output device 5. In FIG. 82, the vertical scroll bar is used to scroll the display information to see the log information at any time, and the horizontal scroll bar introduces a good nondeterminism, and when there are multiple feasible candidates, Used to see information. By using the vertical and horizontal scroll bars in this way, it is possible to see an arbitrary place in all log information. Furthermore, “order correction” and “non-determinism introduction” shown at the top of the screen are used to select and instruct processing when requesting each operation described later.

Furthermore, the user inputs an instruction via the input device 4 to the first execution program and the execution log information file saved in the HSP file storage unit 14 to the test execution device 15, and the hyper sequential program HSP
You can perform a test run as.

The test execution device 15 presents the result of the test execution to the output device 5. The user can perform predetermined test / debug on the hyper sequential program HSP using the input device 4 based on the result of the test execution. For test / debug, please refer to C for functional defects.
The first parallel program in the P-file storage unit 11 is corrected, and regarding the timing problem, the execution log information file in the serialization rule storage unit 13 is corrected, and the corrected first parallel program and execution log information are corrected again. And re-create the hyper-sequential program.

After performing the test / debug on the hyper sequential program HSP, the user again gives a test execution instruction from the input device 4. As a result, the hyper-sequential program HSP subjected to the test / debug is input to the test execution device 15 and the test execution is performed again. This test / debug is repeated until it is confirmed that the hyper sequential program HSP operates normally.

When it is confirmed by test / debug that the operation is normal, the serialization rule modification device 26 partially introduces information about good nondeterminism into the hyper-sequential program. The information about the good nondeterminism introduced by the serialization rule correction device 26 is reflected in the log information and recorded in the HSP file storage unit 14.

Next, the hyperserial program (partial hyperserial program PHSP) into which the information about good nondeterminism is introduced by the serialization rule modification device 26 is tested by the test execution device 15 according to the instruction from the user, and the test is executed. -Perform debugging. In this case, the behavior of the partial hyper-sequential program PHSP behaves in a non-deterministic manner with respect to the portion in which the information about good non-determinism is introduced, and therefore it is preferable to test / debug all the behavior. In this way, the test / debugging and the introduction of the information on the good nondeterminism are repeated, and the information on the good nondeterminism is gradually added.

Partial hyper-sequential program PHSP obtained by incrementally introducing information about good nondeterminism
Is input to the parallelization device 18 according to an instruction from the user. In the parallelization device 18, the partial hyper-sequential program P
The harmless nondeterministic part of the HSP is extracted, and the entire partial hypersequential program PHSP is parallelized. That is, the centralized log information is divided so as to define the activation order for each process, and the activation control is performed for each process, thereby canceling the default sequentiality and converting the partial hyper sequential program into a parallel program. Converted to the second CP file storage unit 1
Record at 9. The user can see this parallel program on the output device and perform final test and debug.

FIG. 83 shows an example of the structure of parts up to the formation of the partial hyper-sequential program relating to the processing of steps A2 to A4. The method of realizing the function of each component will be described below.

FIG. 84 shows the format of messages exchanged between processes. In the "destination information", information that specifies the information transmission destination such as the destination process name is set,
In the "source information", information defining the source such as the source process name is set. Data exchanged between processes is set in the "message body".

Information stored as log information is shown in FIG.
It is generated by using the destination information and the source information in the message format of. In the following description, the destination process name is used as the destination information as the log information, and only the source process name is used as the source information. Since there is no more, the sender information can be expanded to include {process name and process activation count}. Furthermore, when a message is sent multiple times during one start of a process, the sender information is specified as {process name, number of process starts,
Message transmission count}. Furthermore, if each process has multiple processing units (hereinafter referred to as a method), add that information and make the sender information {process name, method name, method invocation count, message transmission count}. You can also

Further, the destination information can be not only the destination process name but also the destination method name to be {destination process name and method name}. Of course, since the destination information and the source information can be combined according to the execution mode, there are a total of eight combinations.

First, the execution unit 22 will be described in detail. As described above, the first concurrent program is randomly executed. Since the execution log at that time is used as the serialization rule, in the present embodiment, all communication between processes is once sent to the process group control unit 203 and stored in the process waiting message storage unit 204 as the serialization rule. Process group control unit 203
Sequentially retrieves the messages from the pending message storage unit 204 and sends them again to the original destination. Therefore, since the process group control unit 203 sequentially controls the activation of all processes, the first concurrent program is sequentially processed.

At this time, the messages sequentially processed by the process group control unit 203 are the log information acquisition unit 20.
2, the log information storage unit 20 as the log information in time series
Stored in 1. This log information is stored in the serialization rule storage unit 1
3, which is an execution constraint condition for subsequent sequential execution.

FIG. 85 shows how communication between processes is performed via the process group control unit 203. In this example,
When processes A and B send a message to process C, there is a good nondeterminism that either message of process A or B may reach process C first. If the process group control unit 203 stores the message before the process B, {process A → process C} is stored in the log information first, and then {process B → process C}.
Is stored. FIG. 86 shows an example of log information which is the serialization rule in that case.

Next, in the serialization device 12, the first parallel program stored in the CP file storage unit 11 is associated with the log information which is the serialization rule obtained as described above. As a result, the first parallel program having parallelism is converted into a hyper sequential program to which serialization information is added.

Next, in the test / debug stage of the test execution apparatus 15, the process group control unit 203 once receives messages exchanged between processes, and in accordance with the order of the log information stored in the log information storage unit 201. Try to send to the original destination. For this reason, the process group control unit 203 uses the process waiting message storage unit 2
It has a mechanism for extracting and transmitting the messages from the messages stored in 04 in the order according to the log information.

As described above, by making the process group control unit 203 transmit the message transmission order in the order specified in the log information, the nondeterminism of the processing order, which is one of the difficulties of the parallel program, is eliminated. Can be resolved,
Reproducibility of processing is realized. That is, in the example of FIG. 85, the process B is the process A when a certain test is executed.
Even if the message is sent to the process C earlier, if the process group control unit 203 describes in the log information that the message from the process A is sent to the process C first as shown in FIG. The message from B is stored in the pending message storage unit 204, the message from the process A is received and transmitted to the process C, and then the message from the process B stored in the pending message storage unit 204 is stored. Send message to process C.

FIG. 87 shows a processing flow of the process group control unit 203.

In the test / debug in the hyper-sequential program whose execution order is uniquely defined according to the log information stored in the log information storage unit 201, if there is a functional defect, the source program is modified to perform the above-mentioned processing steps. It is necessary to perform again from step A2, but if there is a problem only in the timing, the test / debug can be easily performed. That is, the log information, which is the serialization rule, may be modified and the log information may be rewritten in the intended order. This rewriting is performed by the log information correction unit 205. The log information correction unit 205 in the serialization rule correction device 26 corrects the log information, which is the serialization rule, according to an instruction from the user. The log information correction unit 205 has a display unit capable of displaying the log information in the processing order (time series) as shown in FIG. Then, the user who wants to correct the timing bug activates the exchanging unit for exchanging the order of the log information, and designates the message whose processing order is to be exchanged as shown in FIG. 88. In the example of FIG. 88, the order change of two messages is instructed, but it is also possible to change the order of a plurality of messages. Of course, one or more messages can be regarded as one set and exchanged between the sets. Then, the log information correction unit 205 has a rewriting unit that rewrites the log information in the log information storage unit 201 as specified by the replacement unit, and in the case of the example of FIG. 88, it is changed as shown in FIG. 89. As a method of specifying the exchange message, there are a method of specifying the message using a pointing device, a method of specifying the line number on the screen from the keyboard, and the like.

As described above, by rearranging the log information in the intended order, the process group control unit 203 changes the order in which the received message is sent to the original destination process during the test execution. Can be easily modified.

For example, in FIG. 85, when the process C originally had to process the message from the process B before the message from the process A, the message from the process A as shown in FIG. If it is designed to process the log information, the log information may be corrected as shown in FIG. 89 according to the above procedure. As a result, the message processing order of the process group control unit 203 is changed, so that the problem of the processing timing can be solved.

By using such a timing problem solving method, it becomes possible to easily perform test / debug without modifying the source program in order to change the processing order of the process, and to improve the productivity of program development. Is improved.

Next, a method for introducing good nondeterminism will be described.

Good nondeterminism is achieved by modifying the log information by the nondeterminism introducing unit in the log information modifying unit 205. This is where the user intentionally introduces nondeterminism into a hyper-serialized program. For example, in the process shown in FIG. 85, when either process A or process B may send the message to process C first, the target log information is designated as shown in FIG. 90. As a result, the non-determinism introducing unit releases the specified order constraint of the messages, for example, as shown in FIG.
1 (a) and the log information storage unit 2 as shown in FIG. 91 (b).
The log information stored in 01 is corrected. FIG. 91 (b)
Is obtained by instructing the horizontal scroll bar to shift to the right in FIG. 91 (a). In this case, we have introduced the nondeterminism of two message orders.
If you introduce more message order nondeterminism, you can view the list by shifting to the right sequentially.

In FIG. 91, process A and process B
If the message is from the process A, the message is sent to the process C. Then, at the next timing, if the message is from the process A or the process B, the message is sent to the process C. Process group control unit 203
By interpreting the log information as described above, it becomes possible to handle good nondeterminism. This can be realized by expanding the check target of whether or not there is a match as a message transmission source from one to a plurality of items in step K3 in FIG. 87 in the process of the process group control unit 203.

However, in the above example, even if the process C continuously receives two messages from the process A and the process B, there is a problem that those messages are processed. However, this is received first. This can be easily prevented by deleting the message from the next activation candidate. In the present embodiment, the message to be deleted is shown only by the process name for the destination information for ease of explanation, but since it can be uniquely identified as described above in the description of the destination information in FIG. 84, it is unprocessed. It does not delete the information in the message.

Therefore, by introducing this good nondeterminism, it is possible to appropriately react to a nondeterministic stimulus from the outside and to realize flexibility, reusability, and expandability of the process.

In the above embodiment, the good nondeterminism is shown with respect to the arrival order of two messages, but it is also possible to give the good nondeterminism to the arrival order of two or more messages. Even in that case, the step K3 in FIG.
Since it is solved by expanding the check target for matching as the message transmission source from one to a plurality in (1), it is obvious that the operation is correct.

Next, step A7 in FIG. 81 and FIG.
The parallelization compilation phase relating to the parallelization device 18 will be described in detail. FIG. 92 shows an example of the configuration of a part related to the process of step A7. Here, the centralized log information storage unit 301 is a storage unit that stores the execution log information after the introduction of the good nondeterminism that is stored in the HSP file storage unit 14. For example, when the process group in FIG. 79 exchanges messages as shown in FIG. 93, good nondeterminism is introduced as shown in FIG. 94 from the centralized log information for hyper sequential program as shown in FIG. It is assumed that the converted log information is saved.

In the following, a procedure for dividing the centralized log information having good nondeterminism introduced into each process will be described with reference to FIGS.
4 and FIG. 95. The criterion for dividing the centralized log information is the division criterion specifying unit 30 in the division criterion specifying device 23.
Specify from 3. The reference may be, for example, a destination process name or a destination computer number, but the destination process name will be used in the following description. When a method name is also added to the destination name, {destination process name, method name} can be specified as the division criterion, and division can be made for each destination method to create a division log. The division standard designation unit 303 holds this division standard.

[0275] When an attempt is made to divide the centralized log information by an instruction from the user, the log information dividing unit 302 is activated. The log information division unit 302 divides the centralized log information according to the standard designated by the division standard designation unit 303 according to the procedure shown in FIG.

When the log information division unit 302 is activated, the division standard value is read from the division standard designation unit 303 (step L1) and the division standard is grasped. Then, one record of the log information stored in the centralized log information storage unit 301 is read (step L2), and it is checked whether it is the final record (step L3). In this example, since the first record of the centralized log information is a message from process A to process D as shown in FIG. 94, it is determined that it is not the last record, and it is applicable according to the division criterion (destination process name = process D). It is saved in the divided log information storage unit (here, referred to as the divided log information storage unit D) (step L4). This operation is repeated until the log information stored in the centralized log information storage unit 301 ends. As a result, as shown in FIG. 96, the log information divided for each destination process is stored in each of the divided log information storage units A, B, C, D.

In FIG. 96 (a), for example, the process A processes the message from the process C and then processes D
Stipulates that the message from is processed. Further, the process C in FIG. 96C is a process in which so-called good nondeterminism is introduced, and the process A or the process B is used.
It is specified that the message from process A is processed first and the message from process A or process B is processed next. In other words, this expresses the good nondeterminism that either the message from process A or the message from process B may come first. here,
Although an example in which the order constraint of two messages is released has been shown, if it is desired to remove the order constraint of more messages and introduce good nondeterminism, it is sufficient to list a desired number of messages in the same line.

Since the divided log information is divided for each destination process, the destination process name in the divided log information can be omitted.

Next, an example of a method in which each process operates in accordance with the log information thus divided for each process will be described. Each process calls the process control unit 305 before receiving the message as shown in FIG. 97 and starting the process of the actual process, and performs the process shown in FIG. 98.
Such calling of the process control unit can be performed by rewriting the source program so that the calling process is inserted at the beginning of the process of each process in the first parallel program as a part of the parallelization device 18. That is, as shown in FIG. 99, each process includes a process control unit 305, a division log information storage unit 304, and a process waiting message storage unit 306 in addition to the original processing part of the process. The process control unit 305 performs message processing by referring to the log information stored in the divided log information storage unit 304 included in the process, and when the message is not a message to be processed, stores it in the processing-waiting message storage unit 306. .

Next, the processing of the process control unit 305 will be described with reference to FIGS. 96 and 98.

For example, in the case of the flow of processing shown in FIG. 93, it is not determined which of the process C and the process D receives the message first, and there is nondeterminism in the processing timing. There is. However, here, it is specified that the message from the process C is processed first and then the message from the process D is processed based on the execution log (corresponding to FIG. 82) when the processes are executed in a super-sequential manner. Therefore, even if harmless nondeterminism is introduced, this rule of message processing order must be observed.

As a first example, the case where the process A is first activated by receiving the message from the process C is shown. When the process A receives the message from the process C and is activated, the process control unit is called to obtain the sender information of the message that activated the process (step M1). Here, the transmission source information Is = {process C}. Subsequently, the message information Ir1 that should come first is obtained from the divided log information storage unit (step M
2). Here, Ir1 = {process C}.

Next, in order to check whether the currently received message matches the order stored in the division log information,
It is checked whether Is is included in Ir1 (step M3). In this case, since both of them are the same and included in the process C, it is possible to immediately perform the processing based on the received message. Therefore, the record read from the divided log information storage unit for the next activation check is advanced by one (step M4). Then, before the processing of the process body is started, if there is an execution waiting message in the processing waiting message saving unit, it is checked whether or not the saved message can be activated. That is, the message information Ir2 to be processed next is extracted from the information stored in the divided log information storage unit (step M5),
It is checked whether or not the message included in the message is present in the pending message storage (step M6). In this case, Ir2 = {process D}, but since there is no message in the process waiting message storage unit, the process ends, and the main process based on the message from process C is performed.

Subsequently, if a message from the process D arrives at the process A, the same process as described above is performed.
Is = {process D}, Ir1 = {process D}, and the set Is is equal to or included in the set Ir1. Since Ir2 does not exist, the process is terminated without having to check the message in the process waiting message storage unit, and the process based on the message from the process D is performed.

On the contrary, the process flow when the process A receives the message first from the process D is shown. That is, when the process A first receives the message from the process D and is activated, the process control unit is called to obtain the sender information of the message that activated the process (step M1). Here, the transmission source information Is
= {Process D}. Then, the message information Ir1 that should come first is obtained from the divided log information storage unit (step M2). Here, Ir1 = {process C}.

Next, in order to check whether the currently received message matches the order stored in the divided log information, it is checked whether Is is included in Ir1 (step M3). In this case, it is determined that the message from the process D should not be processed immediately because it is not included, the message from the process D is saved in the process waiting message saving unit 306 (step M8), and the process of the process A is forced. (Step M9). That is, the process A is performed without performing the process based on the message from the process D.
Is completed.

Subsequently, if a message from the process C arrives at the process A, the same process as described above is performed.
Since Is = {process C} and Ir1 = {process C}, and Is is included in Ir1, it is permitted to immediately perform the processing based on the received message. Therefore, the record read from the divided log information storage unit for the next activation check is advanced by one (step M4). Then, before starting the processing of the process body, it is checked whether or not there is a ready-to-run execution waiting message in the processing waiting message storage. That is, the message information Ir2 to be processed next is taken out from the information stored in the divided log information storage unit (step M5), and it is checked whether the message contained therein exists in the processing waiting message storage unit (step M6). In this case, Ir2 = {process D} is satisfied, and since the corresponding message that has been stored in the processing-waiting message storage unit already exists, in order to process the executable message next time, the destination (here Then, the sender information etc. is directly sent to the process A) (in this example,
The process D remains unchanged (step M7). Then, the process A ends the process of the process control unit so as to perform the process based on the message sent from the process C as the received message.

Further, since the process A receives the message extracted from the waiting message storage section and transmitted, if the same process as above is performed, Is = {process D},
Ir1 = {process D} and Is becomes Ir1. I
Since r2 does not exist anymore, the process is terminated without checking the message in the process-waiting message storage unit, and the process based on the message from the process D is performed.

As a result, even if the order of arrival of the messages is different from the order described in the execution log, the processing is performed in the order described in the execution log, and the reproducibility of the non-deterministic processing is guaranteed.

Next, the operation of the process C will be shown as an example of the process when the better nondeterminism is introduced. When the process C first receives the message from the process A and is activated, the process control unit is called and the sender information of the message that activated the process is obtained (step M
1). Here, the transmission source information Is = {process A}. Then, the message information Ir1 that should come first is obtained from the divided log information storage unit (step M2). Here, Ir1 = {process A, process B}, and the message from process A, the message from process B, or the message from either may be used.

Next, in order to check whether the currently received message matches the order stored in the division log information,
It is checked whether Is is included in Ir1 (step M3). In this case, since the set Is is equal to or included in the set Ir1, it is possible to immediately perform the processing based on the received message. Therefore, the record read from the divided log information storage unit for the next activation check is advanced by one (step M4). Before the processing of the process body is started, if an execution waiting message exists in the processing waiting message storage unit, it is checked whether the stored message can be activated. That is, the message information Ir2 to be processed next is taken out from the information stored in the divided log information storage unit (step M5), and it is checked whether the message contained therein exists in the processing waiting message storage unit (step M6). In this case, Ir2 = {process A, process B}, but since there is no message in the process waiting message storage unit, the process is terminated and the main process based on the message from process A is performed.

Subsequently, if a message from the process B arrives at the process C, the same process as described above is performed.
Is = {process B}, Ir1 = {process A, process B}, and Is is equal to Ir1 or included in Ir1. Since Ir2 does not exist, the processing is terminated without the need to check the message in the processing waiting message storage unit.
Processing based on the message from the process B is performed.

In the above example of good non-deterministic introduction, even if the message from the process B arrives first in the state where the message arrival order is reversed, that is, in the process C, the message from the process A arrives thereafter. Obviously, the same can be done.

However, in the above example, even if the process C receives two messages in succession from the process A and the process B, there is a problem that those messages are processed. However, this is received first. This can be easily prevented by deleting the message from the next activation candidate. In the present embodiment, for the message to be deleted, the destination information is indicated only by the process name for ease of explanation, but since it can be uniquely identified as described above in the description of the destination information in FIG. It does not delete the processing message information.

As described above, by dividing the operation log information for each object and operating it, the sequentiality extracted by the hyper-sequential program can be realized while realizing the harmless nondeterminism potentially possessed by the concurrent program. Since the processing is maintained, the reproducibility of the processing is maintained, and the same result as when the hyper sequential program is executed can be realized with higher processing performance.

Further, in the above example, the good nondeterminism is shown with respect to the arrival order of two messages, but it is also possible to give the good nondeterminism to the arrival order of two or more messages. Even in that case, it is obvious that the above-mentioned processing works correctly because Ir1 and Ir2 are solved by having plural elements.

Further, in the above example, the embodiment in which the process control unit is called at the beginning of the processing of each process or each method has been described. However, the operating system of each computer has a message waiting storage unit for each destination process. It is also possible to realize the above by holding the above, and referring to the corresponding division log information each time the message is processed, activating the corresponding process or saving it in the processing waiting message saving unit.

In this case, step M7 in FIG.
Then, it is sufficient to change from the waiting state to the scheduling target as the next process that can be started without sending the next processing target message.

According to this embodiment, by rewriting the log information which is the serialization rule without modifying the source program, it is possible to easily solve the problem caused by the nondeterminism of the processing timing. As a result, parallel / parallel /
The development of distributed programs can be facilitated and productivity can be improved.

Further, in the present embodiment, since it is possible to easily introduce only the good non-determinism intended by the user, it is possible to maintain the flexibility, reusability and extensibility as a concurrent program.

Further, the centralized log information of all processes obtained by serializing the parallel program is divided into each process,
By controlling each process based on the divided log information, harmless nondeterminism can be naturally introduced, and the same result as when the hyper sequential program is executed based on the centralized log information can be obtained with high processing efficiency.

Note that the configuration of the computer system according to this embodiment is as shown in FIG. 1 in the case where (a) the shared memory 3 does not exist, (b) the I / O interface 2 is a bus and the processor 1-1 is densely arranged. In the case of a parallel computer to which 1 to N are connected, (c) in the case of a distributed network computer configuration in which I / O interfaces are loosely coupled in a communication path, (d) in the case of a single processor, And in the case of a combination thereof,

(Ninth Embodiment) A section which is a new concept used in this embodiment will be described.

The section in this embodiment refers to a program fragment having only one thread entrance and a plurality of exits. Here, a thread is a term generally used in the field of computer languages, and refers to an agent that executes a program while executing it. For example, if multiple threads run at the same time, it means parallel execution.

It is assumed that there is the following program fragment. code1 code2: branch processing 1 processing 2 Here, for simplification, it is assumed that there is no branch instruction or synchronization instruction to the outside of the section in the section from code1 to the branch instruction. When a thread processes this program fragment, code1 starts at the execution point, that is, cod.
e1 becomes the entrance of the thread. Next, the process proceeds
When it is decided whether to branch to the process 1 or proceed to the process 2 when the nch instruction is reached, depending on the processing contents up to the branch instruction, there are two threads, one for the thread to proceed to the process 1 and one for the thread to proceed to the process 2. There will be an exit. Therefore, cod
The program fragment from e1 to the branch instruction is a section having two thread exits. By the way, if there is a branch instruction from this program fragment to the outside between code1 and branch, that also becomes one of the exits of this section.

The above example shows the case where one thread selects one exit from a plurality of exits and exits. However, an example in which a thread is generated inside a program fragment next Indicates. code1 code2: fork process 1 In the above example, a fork instruction splits a thread, that is, another thread is generated. At this time, the process 1 is processed in parallel by the two split threads, but it can be regarded that each thread exits from the two exits and executes the process 1. Therefore, between code1 and fork instruction, if there is no branch instruction to the outside in this section, the section has two exits. In this way, the place where the thread is created inside the program fragment is also regarded as a kind of branch, and can be a section having a plurality of exits.

[0307] Fig. 100 is a diagram conceptually showing the above section. As shown in FIG. 100, a section consists of a sled inlet 101, a section body portion 102, and a plurality of sled outlets 103.
Hereinafter, such expressions will be used when conceptually illustrating the section.

Fusion and division of sections will be described below.
FIG. 101 is a conceptual diagram showing the fusion of sections. FIG.
01 shows an example in which two sections S11 and S12 are fused to generate a new section S13. An arrow 201 in FIG. 101 is one of the exits of S11, and connecting it to the entrance of S12 enables fusion of two sections. Although this example shows the fusion of two sections, a new section can generally be created (fused) by connecting the outlet and the inlet in a plurality of sections.

FIG. 102 is a conceptual diagram showing division of sections. FIG. 102 shows an example in which the section S21 is divided into two sections S22 and S23. Now consider the following example program fragment. code1: code2 code3: code4 However, it is assumed that code1 to code4 do not include branch instructions. When the thread processes this, code1 serves as the entry and code4 serves as the exit, so this program fragment can be regarded as a section with one exit. This program fragment is associated with section S21. Then, for example, split between code2 and code3,
code1 and code2 are section S22, code
If 3 to code4 correspond to the section S23, the section S21 becomes the section S22 and the section S23.
Will be divided into. In this way, one section can be divided into a plurality of sections.

Next, the classification of sections will be described.
Sections are classified into basic sections and group sections. The basic section is a section that does not include a branch instruction or a synchronization instruction inside. When the basic section is divided, it becomes the basic section. A group section is a section other than the basic section, and the group section can be divided into multiple basic sections.

A case where the predicted execution time is added to the section will be described. Here, it is assumed that the execution time (or average execution time) of the individual instructions making up the section is known, and this time is called the predicted execution time of each instruction.

Since the basic sections are executed in series without branching in the middle, the predicted execution time from the entry to the exit of the section is calculated by summing the predicted execution times of the instructions forming the section. It In the case of a basic section, even if there are a plurality of exits, the exit of the section is always the last branch instruction or synchronous instruction of the instruction sequence, so generally the predicted execution time from the entry to each exit is equal.

Since the group section can be decomposed into basic sections, the predicted execution time to the exit is calculated by adding the predicted execution time of the basic section passing from the entrance of the group section to each exit. That is, in the group section, the predicted execution time changes depending on the exit. Also, inside the group section, a loop whose number of times changes depending on the processing result, an infinite loop, joy
It is impossible to predict the execution time including synchronous instructions such as n and input / output instructions. At that time, the group section may be divided into a plurality of sections that do not internally include the loop, the synchronization instruction, and the input / output instruction whose execution time cannot be predicted, and the divided sections may be targeted.

After the predicted execution time to each exit of the section is calculated by the above method, the largest one among them is set as the predicted execution time of the section itself.

The predicted execution time of a section serves as a guideline when merging / dividing sections in order to improve the efficiency of section execution, and can also be used as a guideline when optimizing the program itself.

In this embodiment, for ease of synchronization and easy prediction of execution time, an instruction for generating a thread such as fork, a synchronization instruction such as join, and an input / output instruction are not included in the section. A loop that is located at the end and whose execution time is unpredictable shall not be included inside.

Example 9 will be specifically described with reference to the drawings. FIG. 103 is a diagram showing a schematic configuration of the ninth embodiment of the present invention.

The program analysis unit 411 analyzes a source program input from an input unit (not shown), divides the source program into basic sections, and extracts rules regarding the execution order of sections. The information analyzed by the program analysis unit 411 (that is, section information) is stored in the section information storage unit 412.

The section information editing unit 413 edits the section information stored in the section information storage unit 412. Specifically, the rules regarding the execution order of sections and the fusion / division of sections are performed automatically or by the user. The compiling unit 414 compiles each section, converts it into an object code, and registers the result in the section information storage unit 412.

The execution unit 415 is the section information storage unit 41.
Based on the section information stored in 2, the program is executed sequentially or in parallel for each section.
Switching between the sequential execution mode and the parallel execution mode is performed by switching between two types of modes, that is, the sequential execution mode and the parallel execution mode. Execution in the sequential execution mode can avoid the problem of reproducibility of a parallel program. That is, the same result can be obtained no matter how many times it is executed, so that effective test / debug can be performed on a parallel program. If the mode is switched to the parallel execution mode and executed in that state, the safe parallel execution can be performed by executing the sections in synchronization with each other. In addition,
If the execution unit 415 executes the program interpretively only, the compiling unit 414 can be omitted.

Each part of the ninth embodiment will be described in detail.

First, the section information storage unit 412 shown in FIG. 103 will be described in detail with a particular structure in which information regarding sections is stored. The section information is divided into information on the section itself and information (rules) on the execution order of the sections. First, how the section itself is stored will be described with reference to FIG.

FIG. 104 shows an example in which two exits have three group sections and one exit has two basic sections. As a whole, a storage method of a group section having six exits is shown. There is. The section information storage unit 412 has section management tables 501, 505, 506, and 509 as shown in FIG. In these management tables, as shown in FIG. 105, a section label, a flag indicating whether the section has been compiled, a pointer pointing to the object if the section has been compiled, and a flag indicating whether the section is a program code. A pointer that points to a parts table of a section that constitutes this section or points to a program code, a pointer that points to each exit, and an expected execution time to that exit are stored.

The section information storage unit 412 further includes the section component tables 502 and 50 shown in FIG.
3, 504. The parts table is a table that stores sections as individual parts that form a group section. Specifically, as shown in FIG. 106, the parts table stores a pointer that points to a management table of sections as parts, a pointer that points to which section each exit is connected, and the like.
In the example shown in FIG. 104, the parts table 502 has a pointer pointing to the management table 505 of another group section,
It stores pointers to the parts tables 503 and 504 of the sections to which two of the three outlets are connected.
Here, for example, the outlet 508 in the parts table is not connected to any parts table. At this time, the pointer pointing to the exit is stored in the management table 501 as the exit of the section. Further, as the management table 506 indicates the program code 507, the management table also manages the program code.

The rules regarding the execution order of sections will be described. In this case, it is assumed that thread 1 executes the following program fragment. Process 1 join Thread 2 Process 2 The above section means that after thread 1 finishes process 1, it waits for thread 2 to finish and then process 2. FIG. 107 shows the above example by replacing it with a conceptual diagram of the section. S31 is the last section among the sections constituting the above-mentioned processing 1. S32 is the first section among the sections forming the above-mentioned processing 2. S33 is the last section executed by thread 2. At this time, this joy
By the n statement, the rule of the section execution order that the execution of the section S32 is started after the execution of the section S33 in the thread 2 after the execution of the section S31 is extracted and stored in the section information storage unit 412. As described above, the rules regarding the execution order of the sections are mainly used to synchronize the sections during execution.

FIG. 108 shows the detailed structure of the program analysis unit 411 in FIG. In FIG. 108, an intermediate language conversion unit 901 converts a source program input from an input unit (not shown) into an intermediate language. The reason why the intermediate language conversion unit 901 converts the intermediate language is that the sections can be easily extracted and the execution time of each instruction can be easily predicted. The intermediate language conversion unit 901
For conversion in, the conventional compiler technology can be used as it is. The section information extraction unit 902 cuts out a basic section from the intermediate language converted by the intermediate language conversion unit 901, and extracts rules and the like regarding the execution order of the sections.

The flow of processing in the program analysis unit 411 will be described in detail with reference to the drawings. FIG. 109 is a diagram showing a flow of processing in the program analysis unit 411.

The input source code is converted into an intermediate language by the intermediate language conversion unit 901 (step N).
1). The converted intermediate language has a section information extraction unit 90.
Handed over to 2.

The section information extraction unit 902 is initialized to extract the basic section from the intermediate language and the rule of the execution order (step N2). This initialization is performed every time a new section is cut out.
In this example, while the basic section is cut out, the predicted execution time of the section is calculated at the same time, so initialization related to it is also performed.

The intermediate language is read line by line and the process is repeated. When the reading of the intermediate language is completed during this repetition (step N3), the intermediate language string read up to this point is stored as one basic section in the section information storage unit 412 (step N8), and the processing is performed. The process ends (step N9).

If the reading of the intermediate language is not completed, one line of the intermediate language is further read (step N4), and the read intermediate language is, for example, an instruction for determining the execution order rule of the join section (step N5). ), The rules determined by the section information storage unit 4
12 (step N10). If the intermediate language is a branch or synchronization instruction (step N6), that instruction is a break in the basic section, so the program fragment read after initialization is stored in the section information storage unit 412 as one basic section (step S6). N11), the process returns to step N2 to extract the next section.
If the read intermediate language instruction does not satisfy the above condition in step N4, the predicted execution time of the instruction is added to the predicted execution time of the section being cut out (step N7), and the process returns to step N3. Here, the predicted execution time of each instruction in the intermediate language may be measured in advance and stored in a table or the like. When the above procedure is completed, the original program is converted into the basic section cut out as the intermediate language sequence and the section execution order rule, and stored in the section information storage unit 412.

The section information editing unit 413 will be described in detail. The section information editing unit 413 has two main operations. One is the operation of merging and dividing the sections, and the other is the operation of editing the rule of the execution order of the sections.

The main purpose of merging / dividing sections is to make the sizes of the sections uniform so that the execution section 415 can execute the sections more efficiently. In this embodiment, the estimated execution time of the section is used for this operation. In the section information editor 413,
The sections may be fused / divided so that the predicted execution time of each section becomes almost uniform, and this can be easily automated.

Also, by editing the section execution order rules of the section information editing unit 413, it is possible to freely change the synchronization between sections at the time of execution, the execution order, etc., and effective testing / debugging is possible. And

The section information editing unit 4 will be described with reference to FIG.
A detailed configuration of 13 will be described. In FIG. 110, the section information conversion unit 1101 changes the section information stored in the section information storage unit 412 in accordance with an instruction of section fusion / division input by an input device (not shown) and a request for editing a rule of the execution order of sections. To do. This operation is mainly performed by the user, but the fusion / division of sections can be easily automated by using the estimated execution time of the sections. The section information display unit 1102 displays the section information stored in the section information storage unit 412 according to an instruction from the section information changing unit 1101.

FIG. 111 shows the detailed structure of the compiling unit 414 in FIG. In FIG. 111, the section end processing unit 1601 writes a code for registering a section to be executed next and ending the section at the end of the section. Section compiling unit 1602
Compiles the section subjected to the end processing, converts it into an object, and registers it in the section information storage unit 412.

Here, a method of processing the end of the section will be described. For example, suppose a section has the following code: Process 1 branch label Process 2 label: Process 3 The above code is a code indicating that, depending on the result of Process 1, jump to label and execute Process 3 or execute Process 2 as it is. Here, when the section located at the beginning of the process 2 is section 2 and the section located at the beginning of the process 3 is section 3, the above code is processed as follows. Process 1 branch label section-end section 2 label: FIG. 112 is a detailed block diagram of the execution unit 415 in FIG. 103. In FIG. 112, the execution section selection unit 1
The section 201 selects one or more sections to be executed next based on the section information and the information stored in the execution section candidate storage unit 1203. The execution section selection unit 1201 has two modes (sequential execution mode and parallel execution mode) that can be switched from an input unit (not shown). In the sequential execution mode, only one section is selected. In parallel execution mode, there are generally multiple section selections. The section execution unit 1202 executes the section selected by the execution section selection unit 1201. In particular, when the selected sections are plural, they are executed in parallel. Execution section candidate storage unit 1203
Stores a section that is a candidate for the next execution determined from the result executed by the section execution unit 1202.

FIG. 113 is a diagram showing the flow of processing in the execution unit 415. The program is executed in section units according to the section information stored in the section information storage unit 412 and the rules of the execution order.

The entire initialization is performed (step P
1). At this time, the execution section candidate storage unit 1203 stores the section to be executed first.

Next, a loop for executing each section is entered. At the beginning of this loop, the selection of the section to be executed next is performed in a different manner depending on the mode (step P2). In the sequential execution mode, one of the section candidates to be executed next stored in the execution section candidate storage unit 1203 that follows the rule of the execution order is selected (step P3). In general, there are several candidate sections that follow the rules. As a method of selecting one from this, for example, the one with the earliest stored time may be selected, or the fixed random number sequence may be selected. However, it is necessary to use a method that guarantees reproducibility as the selection method here. This is because one of the important motives of the present invention is that the order of selection is not changed (that is, reproducibility is guaranteed) every time the program is executed. When the mode is the parallel execution mode, all the sections that follow the rule are selected from the execution candidates (step P4). There will generally be more than one section selected.

In step P3 or step P4,
If the selection fails (step P5), the program may have ended or may have failed due to an abnormality in the rule that determines the execution order. Therefore, the candidate list is checked (step P6), and if no candidate remains, the process ends normally (step P7), and if any remains, the process ends abnormally (step P8). In the case of abnormal termination, for example, a deadlock state can be considered, and by presenting this to the user, it can be used as a guideline for testing and debugging. When the selection is successful in steps P3 and P4, the selected section is executed (step P
9).

When multiple sections are selected, they are executed in parallel. After that, the section execution unit 415 waits for the end of the execution of all the sections executed in parallel, and then proceeds to the next step.

Since the section used in this embodiment does not include a factor that makes the execution time unpredictable, such as an infinite loop, it means that the section is kept waiting forever. There is no.

When the execution is finished, the finished section is erased from the execution section candidate storage unit 1203,
Next, the section to be the next execution candidate is stored according to the execution result (step P10). "Depending on the execution result"
This means that, for example, when the end of the section is an if statement, the branch destination for the next branch, that is, the section to be executed next, changes depending on the calculation result. Also, when a section ends with an end statement,
The thread that was executing it also exits, so this thread has no next section to execute. At this time, nothing is stored in the execution section candidate storage unit 1203.

A detailed change in the stored contents in the execution section candidate storage unit 1203 will be described. FIG. 114 is a diagram showing an example of a program by using a conceptual diagram of sections. One thread executes section 1, and the fork statement in it divides into two threads, and each thread executes section 2 and section 4, and jo
An example is shown in which an in instruction is used to synchronously return to one thread, and finally section 3 is executed and terminated. Here, it is assumed that a rule regarding the execution order of the section that section 3 is executed after section 4 is extracted by the program analysis in advance in order to synchronize with the join statement.

FIG. 115 is a diagram showing changes in the execution section candidate storage unit 1203 when the above example is executed in the sequential execution mode.

In the initial state 1401, the section 1 to be executed first is stored. Therefore, section 1 is executed first. Fork when section 1 is executed
Since the thread is divided into two by the statement, two sections, section 2 and section 4, are stored as the next execution candidates (state 1402). In the parallel execution mode, section 2 and section 4 are selected and executed at the same time. However, since the sections are executed in the sequential execution mode, one of them must be selected. Therefore, assume that section 2 is selected and executed. When section 2 ends, section 3 as the next candidate is stored (state 1403).

Next, as far as the candidates are seen, it seems that either section 3 or section 4 may be selected, but the rule of the execution order shown above is that "section 3 is section 4".
Executed after "means that only Section 4 can be selected, so Section 4 will be executed. When the execution of section 4 ends, the thread that executed it ends, so that the candidate storage unit 1203 has no section following section 4 (state 14
04). Then, the section 3 is executed and all the processing is completed (state 1405).

The present invention is not limited to the above embodiments.

Although the above embodiments have been described as independent embodiments, by combining them appropriately,
It becomes possible to create more effective concurrent programs. In particular, it is possible to execute the concurrent programs created in the first to eighth embodiments by the concurrent program execution device of the ninth embodiment to verify the validity thereof, and in the ninth embodiment, the source program is used. The parallel program is executed by the parallel program execution device, and as shown in the first to eighth embodiments, the sequential program is parallelized based on the execution information (including the test / debug information), or the source program is executed. It may be converted to a parallel program without bugs.

According to the present embodiment, the execution logs can be rearranged and presented to the user in a form that is easy for the user to understand without changing the meaning. Since it is guaranteed that the meaning does not change even if rearranged, if there is a bug in the original execution log, the bug also exists in the rearranged execution log. This property has the effect of improving the efficiency of test / debug.

(Embodiment 10) In this embodiment, a concrete method of realizing the serialization device 12 of FIG. 2 will be described. FIG. 117
FIG. 3 is a block diagram showing an embodiment of the serialization device 12. The serialization device 12 includes a test execution device 121, a first execution log file storage unit 122, an analysis device 123, a preceding relationship information file 124, a rearrangement device 125, and a second execution log file storage unit 126.

FIG. 118 is a flow chart showing a schematic procedure of a parallel program creating method when the serializing device 12 of FIG. 117 is used.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Also, each process structure is determined. Furthermore,
The source program CP is described in the process by programming using a parallel program or the like. This source program may have potential bugs. FIG. 119 is a specific example of the source program CP described in this way, and programs two processes P1 and P2.

(2) Step Q1: Execution The source program CP is executed by the test execution device 121, and the execution log is stored in the first execution log file storage unit 122.
And is displayed on the output device 5 of FIG. In this example, there are many possible execution logs for the source program CP of FIG. 119, but here, FIG.
It is assumed that an execution log such as However, in this execution log, the process P1 and the process P2 are intricately intertwined with each other, and the execution process is difficult to grasp.

(3) Step Q2: Judgment of Bug If there is no bug as a result of the test, the process ends. If there is a bug as a result of the test, the execution log 3 is saved and the process proceeds to step Q3. In the case of this example, it is assumed that the value of M after execution indicated by the execution log of FIG. 120 is “M = −1”, and it is determined to be a bug (the expected value is “M = 0”).

(4) Step Q3: Analysis The analysis device 123 extracts the preceding relationship information between processes from the source program CP from the first CP file storage unit 11 and the execution log stored in the first execution log file storage unit 122. Then, it is stored in the preceding relationship information file 124. FIG. 121 shows the precedence relationship between the instructions of the two processes P1 and P2 in the execution log of FIG. 119.

(5) Step Q4: Rearrangement of Execution Logs From the execution logs and precedence relation information stored in the first execution log file storage unit 122 and precedence relation information file 124, the rearrangement device 125 makes it easy for the user to understand. The execution log sorted in order is generated and stored in the second execution log file storage unit 126. In the case of this example, the execution logs rearranged in an order that is easy for the user to understand are generated within a range that satisfies the preceding relationship in FIG. As an example of a specific rearrangement rule, (a) introducing a priority into the process,
For example, the execution logs are rearranged using the priority order, (b) the execution logs are rearranged by giving priority to the process whose waiting state has been released, and (c) the user specifies. FIG. 122 shows an execution log after rearranging the processes by introducing the priority order.

(6) Step Q5: Display of Execution Log The rearranged execution logs stored in the second execution log file storage unit 126 are sequentially output as a program, and displayed by the output device 5 to be presented to the user. .

In this example, the execution log shown in FIG. 122 is displayed on the output device 5 as shown in FIG. This execution log is collected within a range in which the instructions of the process P1 and the process P2 maintain the preceding relationship, and the user can easily understand the execution process.

(7) Step Q6: Debugging / Modifying Concurrent Program The user grasps the execution process or reproduces the execution by looking at the execution log displayed on the output device 5, and corrects the program if the cause of the bug is found. . After correcting the program, return to step Q1. In the case of this example, from the display of the execution log in FIG. 122, the user finds that the cause of the bug is “P2: read (M,
The position of the send instruction of P2 can be corrected by recognizing that the order of "Y);" and "P1: write (M, XX);" is incorrect. Figure 12 shows the modified program.
It becomes like 3. When the modified program is executed, the value of M after execution becomes “M = 0”, which indicates that the bug can be deleted.

(Embodiment 11) In this embodiment, the test execution is performed on the partial hyper-sequential program, but the source code is corrected on the original concurrent program. Information about good nondeterminism is introduced under the serialization condition, and the original concurrent program is serialized (partial serialization) every time good nondeterminism is introduced.

FIG. 124 is a diagram showing a schematic configuration of the parallel program creation support apparatus according to this embodiment. In the figure, the source program CP stored in the first CP file storage unit 11 is extracted by a user's instruction from the input device 4 and input to the serialization device 12. The source program CP input to the serialization device 12 is a hyper sequential program HSP or a partial hyper sequential program PHS according to the serialization rule stored in the serialization rule storage unit 13.
Converted to P, HSP / PHSP file storage unit 141
Recorded in.

The test execution unit 15 tests the program HSP / PHSP. here,
If there is a bug, the source program CP stored in the first CP file storage unit 11 is debugged using the debug device 16.
To fix. The modified source program CP is re-serialized to generate a hyper-sequential program (HSP) or a partial hyper-sequential program (PHSP), and HSP / PHSP is generated.
It is recorded in the file storage unit 141.

This series of cycles is repeated to
When debugging is completed, with the non-deterministic introduction device 17,
The restriction of the serialization rule stored in the serialization rule storage unit 13 is relaxed, and the partial hyper-sequential program PHSP is generated. Then, the same test / debug is repeated for this partial hyper-sequential program PHSP, and the nondeterminism introducing device 17 gradually weakens the constraint of the serialization rule. When the good non-deterministic introduction is completed in this way, a parallel program is finally generated in the parallelization device 18 and stored in the second CP file storage unit 19.

(Embodiment 12) In this embodiment, a test hyper-sequential program is tested. However, if there is a bug, the test is performed by modifying the serialization rule without modifying the concurrent program as the source code. Debug. Other parts are basically the same as those in the above-described embodiments.

Creation of a parallel program in this embodiment is realized by the following procedure. Fig. 125
3 is a flowchart showing a schematic procedure of a parallel program creating method according to the present embodiment.

(1) Step A1: Modeling Natural modeling using concurrency is performed on the target parallel system. Also, each process structure is determined. Furthermore,
A parallel program having a parallel structure is described as a source program by programming in the process using a parallel program or the like. This source program contains
Potential bugs may exist. (2) Step A2: Serialization The parallel program obtained in Step A1 is converted into a hyper-sequential program based on a predetermined serialization rule.

(3) Step A3: Test / debug The hyper-sequential program converted in step A2 is executed for testing, and if there is a functional bug, the hyper-sequential program is modified for test / debug. .

(4) Step C2: Bug Judgment If the result of the test in Step A3 shows that there is a bug in timing, the process proceeds to Step J1. If there are no bugs, save the hyper sequential program and proceed to step A4.
Move to

(5) Step J1: Modification of Serialization Rule If it is determined in step C2 that there is a bug in timing, the serialization rule is modified and the process returns to step A2.

(6) Step A4: Introduction of Good Nondeterminism If good nondeterminism needs to be added, the serialization rule is modified in step J1 to set a new serialization rule, and the process returns to step A2. If it is not necessary to add good nondeterminism, the process proceeds to step A7.

(7) Step A7: Parallelization Compilation A harmless non-deterministic part is extracted from the stored set of hyper-sequential programs and is generated as a parallel program.

FIG. 126 is a diagram showing a schematic configuration of the parallel program creation support apparatus according to this embodiment. In the figure, in the source program CP stored in the first CP file storage unit 11, the default serialization is introduced at the meta level according to the serialization rule stored in the serialization rule storage unit 13 in the serialization device 12. Is converted into a hyper sequential program (HSP) by
It is recorded in the file storage unit 14. The user can see the hyper sequential program HSP by the output device 5. This hyper-sequential program HSP is input to the test execution device 15 according to an instruction from the input device 4 by the user, and the test execution is performed.

The test execution device 15 presents the result of the test execution (execution log) to the output device 5. The user uses the serialization rule correction device 2 based on the result of this test execution.
6 can be used to modify the serialization rule stored in the serialization rule storage unit 13 to perform predetermined test / debug on the hyper-sequential program HSP.

By modifying the serialization rule in this way, the user can perform a predetermined test on the hyper-sequential program HSP.
After performing the debugging, the test execution instruction is given again from the input device 4. As a result, the hyper-sequential program HSP subjected to the test / debug is input to the test execution device 15 and the test execution is performed again. This test / debug is repeated until it is confirmed that the hyper sequential program HSP operates normally.

Then, in the present embodiment, when it is confirmed by the test / debug that the operation is normal, the serialization rule correction device 26 corrects the serialization rule stored in the serialization rule storage unit 13. The corrected serialization rule is newly recorded in the serialization rule storage unit 13. This modification of the serialization rules partially introduces information about good nondeterminism into hypersequential programs.

It is needless to say that various modifications can be made without departing from the scope of the present invention.

[0379]

According to the present invention, the following effects can be obtained.

In the present invention, a concurrent program is serialized once, and the serialized program is tested and debugged, so that the concurrent program can be executed at the same level of difficulty as the sequential programming, which is much easier than the conventional concurrent program programming. It is possible to test and debug.

By presenting parallelization and serialization information to the user at the same time by the above graph information,
The user considers the parallel structure of the first concurrent program,
You will be able to specify good non-deterministic parts. In addition, it is possible to specify and cancel the good non-deterministic part for the graph information instead of specifying and canceling the good non-deterministic part at the concurrent program description level. , Will be able to easily develop concurrent programs.

When the first concurrent program is converted into a sequential program, the first concurrent program and its execution log are analyzed, and the execution logs are sorted based on the result of this analysis. By displaying it and presenting it to the user, it becomes easy to understand the execution process of the concurrent program, and the efficiency of test / debug is improved. When introducing information about concurrency into a serial program, the process flow of the serial program is converted into a field consisting of constraints and transition conditions, and the field data is displayed to edit the field interactively and visually. This effectively introduces information about concurrency and effectively creates bug-free concurrent programs.

After a process group which is a candidate for parallelization is designated for the serialized program serialized from the first concurrent program and the execution order of this process group is exchanged to convert the sequential program into a plurality of parallel simulated programs. , A plurality of parallel simulation programs are partially converted into one partial sequential program having a sequential structure, and the partial sequential program is parallelized and converted into a second parallel program, thereby making The operation can be fully confirmed. Further, by designating a process group that is a candidate for parallelization with respect to the partial sequential program, the sequential structure program can be gradually converted into a parallel program. Furthermore, by introducing information about concurrency that allows only nondeterminism that is confirmed to operate correctly by sequential execution based on the parallel simulated operation sequence, a parallel program that operates correctly can be obtained. These facilitate testing and debugging of concurrent programs.

In a parallel program creation support device for supporting creation of a parallel program used in an execution environment in which process groups exchange message information and operate in parallel, log information which is an execution history of the process group of the first parallel program Is acquired as a serialization rule and stored, the log information can be corrected, and the process group is sequentially activated based on the stored log information, and the stored log information is stored. By parallelizing and converting to the second parallel program, it is possible to solve the problem caused by the nondeterminism of the processing timing by modifying the log information without modifying the parallel program as the source program. This facilitates the development of parallel / parallel / distributed programs with inherent non-deterministic processing timing.
Further, since only good nondeterminism intended by the user can be easily introduced, it is possible to maintain flexibility, reusability, and extensibility as a concurrent program.

In a system in which the process groups operate in accordance with the execution order specifying information in an execution environment in which the process groups can operate in parallel while exchanging message information, the execution order specifying information is divided, that is, a parallel program is serialized. By dividing the centralized log information of all the processes for each process and controlling the activation of the process group based on this divided execution order information, harmless nondeterminism is naturally introduced, and the sequential log information is used. It is possible to obtain the same result as when the program is executed with high processing efficiency.

As a result of the test execution of the first parallel program, one of them, a bug-free execution log, is accumulated, and only the accumulated bug-free execution log is parallelized to generate a second parallel program. By converting to, the program moves so that only the timing passed in the test is allowed, so it is possible to avoid falling into the bug that remained due to not testing, and improve the reliability.

According to the parallel program execution device of the present invention, since it is possible to execute a serial or partial parallel execution of a parallel program, reproducibility can be assured like a conventional serial program, and it is effective and stable. You can perform the test / debug that you have done. Moreover, since it is possible to easily switch from serial execution to partial parallel execution, it is possible to safely execute parallel execution of a program that has been serialized and tested and debugged without being affected by nondeterminism. In addition, by editing the rules regarding the execution order of the sections and controlling the synchronization between the sections at the time of execution, it is possible to perform effective test / debug and also to guide the efficiency of the program.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system for realizing a parallel program creation support device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a parallel program creation support device according to the first embodiment.

FIG. 3 is a flowchart showing a schematic procedure of a parallel program creating method according to the first embodiment.

FIG. 4 is a diagram showing an example of a parallel program and a serialization rule for explaining the operation of the first embodiment.

FIG. 5 is a conceptual diagram of a hyper-sequential program in which meta-level default seriality is introduced for explaining the operation of the first embodiment.

FIG. 6 is a diagram showing an example of a debug screen for explaining the operation of the first embodiment.

FIG. 7 is a diagram showing an example of introducing information about nondeterminism for explaining the operation of the first embodiment.

FIG. 8 is a block diagram showing a schematic configuration of a parallel program creation support device according to a second embodiment.

FIG. 9 is a flowchart showing a schematic procedure of a parallel program creating method according to the second embodiment.

FIG. 10 is a diagram showing an example of a section setting method.

FIG. 11 is a diagram showing an example of a serialization method.

FIG. 12 is a diagram showing an example of a rewriting rule of serialization information.

FIG. 13 is a diagram showing an example of a parallel program.

FIG. 14 is a diagram showing a description example of a parallel program.

FIG. 15 is a diagram showing section information, program structure information, and hyper-serialization information of a hyper-sequential program, respectively.

FIG. 16 is a diagram for explaining the introduction of good concurrency.

FIG. 17 is a diagram showing source code of a parallel program generated from sequential programming with automatic parallelization.

FIG. 18 is a diagram showing program structure information of a hyper sequential program.

FIG. 19 is a diagram showing serialization information of a hyper sequential program.

FIG. 20 is a diagram showing the flow of processing of a hyper-sequential program that is automatically parallelized.

FIG. 21 is a block diagram showing a schematic configuration of a parallel program creation support device according to a third embodiment.

FIG. 22 is a flowchart showing a schematic procedure of a parallel program creating method according to the third embodiment.

FIG. 23 is a diagram showing an example of a parallel program which is a source program for explaining the operation of the third embodiment.

FIG. 24 is a diagram showing an example of parallel program composition in the third embodiment.

FIG. 25 is a flowchart showing a schematic procedure of a parallel program creation method according to the fourth embodiment.

FIG. 26 is a diagram showing a process table used in the fourth embodiment.

FIG. 27 is a diagram showing an example of a parallel program for explaining the operation of the fourth embodiment.

28 is a conceptual diagram showing the parallel structure of the parallel program in FIG.

FIG. 29 is a diagram showing a process table created as a result of structural analysis of a parallel program used in the fourth embodiment.

FIG. 30 is a diagram showing an example of a hyper-sequential graph used in the fourth embodiment.

FIG. 31 is a diagram for explaining an operation process of the hyper-sequential graph generation device according to the fourth embodiment.

FIG. 32 is a diagram for explaining a method of designating a parallelization part according to the fourth embodiment.

FIG. 33 is a diagram showing an example of a hyper-sequential graph after designation of a parallelization part according to the fourth embodiment.

FIG. 34 is a diagram showing an example of a hyper-sequential graph having grouped nodes.

FIG. 35 is a diagram showing an example of a hyper-sequential graph after priority change.

FIG. 36 is a diagram for explaining the introduction of a good nondeterministic portion between three processes.

FIG. 37 is a diagram showing a hypersequential graph after introduction of a good nondeterministic part.

FIG. 38 is a block diagram showing a schematic configuration of a parallel program creation support device according to the fifth embodiment.

FIG. 39 is a diagram showing a parallel program which is a source program for explaining the operation of the fifth embodiment.

FIG. 40 is a diagram showing the flow of processing executed by the parallel program shown in FIG. 39.

FIG. 41 is a diagram showing an example of a serialization process stored in a serialization process file according to the fifth embodiment.

42 is a diagram showing the flow of processing executed in the serialization process of FIG. 41. FIG.

FIG. 43 is a flowchart showing the flow of processing executed by the field data generation unit according to the fifth embodiment.

FIG. 44 is a diagram showing a data structure of an area generated by the processing of FIG. 43.

FIG. 45 is a diagram showing an example of field data generated by a field data generation unit in the fifth embodiment.

FIG. 46 is a flowchart showing the flow of processing executed by the field tuning unit in the fifth embodiment.

FIG. 47 is a diagram showing a part (step E9) of FIG. 46 in detail.

FIG. 48 is a diagram showing a change in a field caused by a constraint changing operation according to the fifth embodiment.

FIG. 49 is a diagram showing another part (step E11) of FIG. 46 in detail.

FIG. 50 is a diagram showing a change in field caused by a constraint changing operation according to the fifth embodiment.

51 is a further part of FIG. 46 (step E13).
The figure which shows in detail.

FIG. 52 is a diagram showing a change in field caused by a constraint changing operation according to the fifth embodiment.

FIG. 53 is a diagram showing a process of detecting a trivial constraint that causes a contradiction in a field.

FIG. 54 is a diagram showing an example of a field including a trivial constraint.

FIG. 55 is a diagram showing an example of detecting a trivial constraint.

FIG. 56 is a diagram showing an example of a display screen of a field editor.

FIG. 57 is a diagram showing another example of the display screen of the field editor.

FIG. 58 is a diagram showing still another example of the display screen of the field editor.

FIG. 59 is a diagram showing a state of a field data tuning process according to the fifth embodiment.

FIG. 60 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 61 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 62 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 63 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 64 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 65 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 66 is a diagram showing a state of a tuning process of field data according to the fifth embodiment.

FIG. 67 is a flowchart showing processing executed by the field conversion unit according to the fifth embodiment.

FIG. 68 is a diagram showing an example of a corrected parallel program according to the fifth embodiment.

69 is a diagram imagining the flow of processes executed by the parallel program of FIG. 68.

FIG. 70 is a diagram showing a schematic configuration of a concurrent program creation support device according to the sixth embodiment.

FIG. 71 is a flowchart showing a schematic procedure of a parallel program creating method according to the seventh embodiment.

FIG. 72 is a diagram showing an example of a concurrent program model assumed by the user for explaining the operation of the seventh embodiment.

73 is a diagram showing an example in which an execution sequence of a hyper sequential program obtained from the parallel program of FIG. 72 is modeled.

FIG. 74 is a flowchart showing the procedure for converting a hyper-sequential program to a partial parallel program according to the seventh embodiment.

FIG. 75 is a diagram showing an example of conversion from a hyper sequential program to a partial parallel program in the seventh embodiment.

FIG. 76 is a diagram showing an example of conversion from a hyper sequential program to a partial parallel program in the seventh embodiment.

FIG. 77 is a diagram showing an example of conversion from a hyper sequential program to a partial parallel program in the seventh embodiment.

FIG. 78 is a diagram showing an example of conversion from a hyper sequential program to a partial parallel program according to the seventh embodiment.

FIG. 79 is a diagram showing an example of information exchange between processes according to the eighth embodiment.

FIG. 80 is a block diagram showing a schematic configuration of a parallel program creation support device according to an eighth embodiment.

FIG. 81 is a flowchart showing a schematic procedure of a parallel program creating method according to the eighth embodiment.

FIG. 82 is a diagram showing an example of log information which is an execution history of messages in the eighth embodiment.

FIG. 83 is a block diagram showing a schematic configuration of a parallel program debug device based on log information according to the eighth embodiment.

FIG. 84 is a diagram showing an example of a message format according to the eighth embodiment.

FIG. 85 is a diagram showing inter-process information exchange according to the eighth embodiment.

FIG. 86 is a diagram showing an example of log information according to the eighth embodiment.

FIG. 87 is a flowchart showing the processing procedure of the process group control unit according to the eighth embodiment.

FIG. 88 is a diagram showing an example of instructing a replacement target in order to correct the log information according to the eighth embodiment.

FIG. 89 is a diagram showing an example of corrected log information according to the eighth embodiment.

FIG. 90 is a diagram showing an example in which the target portion is specified in order to introduce good nondeterminism into the log information in the eighth embodiment.

FIG. 91 is a diagram showing an example of log information after introduction of good non-determinism in Example 8.

FIG. 92 is a diagram showing a configuration of a parallel program execution system based on log information in the eighth embodiment.

FIG. 93 is a diagram showing information exchange between tasks according to the eighth embodiment.

FIG. 94 is a diagram showing an example of log information when good nondeterminism is introduced in the eighth embodiment.

FIG. 95 is a flowchart showing the processing procedure of the task control unit according to the eighth embodiment.

FIG. 96 is a diagram showing an example of a program that is one means for activating a task control unit according to the eighth embodiment.

FIG. 97 is a diagram showing a message format according to the eighth embodiment.

FIG. 98 is a flowchart showing the processing procedure of the task control unit according to the eighth embodiment.

FIG. 99 is a diagram showing a configuration example of each task in the eighth embodiment.

FIG. 100 is a view showing the concept of sections.

101 is a conceptual diagram showing section fusion. FIG.

FIG. 102 is a conceptual diagram showing division of sections.

FIG. 103 is a diagram showing a schematic configuration of a ninth embodiment of the present invention.

FIG. 104 shows a data structure for storing sections.

FIG. 105 is a diagram showing the structure of a section management table.

FIG. 106 is a view showing the structure of a parts table.

FIG. 107 is a view for explaining the rules of the execution order of sections.

FIG. 108 is a diagram showing a detailed configuration of a program analysis unit.

FIG. 109 is a flowchart showing the flow of program analysis.

FIG. 110 is a diagram showing a detailed configuration of a section information editing unit.

FIG. 111 is a diagram showing a detailed configuration of a compiling unit.

FIG. 112 is a diagram showing a detailed configuration of an execution unit.

FIG. 113 is a flowchart showing the processing flow of the execution unit.

FIG. 114 is a diagram for explaining changes in the execution section candidate storage unit.

FIG. 115 is a diagram showing changes in the execution section candidate storage unit.

FIG. 116 is a diagram for explaining a problem of the conventional technique.

117 is a block diagram showing the configuration of the serialization device according to the tenth embodiment. FIG.

FIG. 118 is a flowchart showing a schematic procedure of a parallel program creating method according to the tenth embodiment.

FIG. 119 is a diagram showing an example of a parallel program which is a source program for explaining the operation of the tenth embodiment.

120] FIG. 119 for explaining the operation of the tenth embodiment.
Of the execution log of the concurrent program of.

FIG. 121 is a diagram showing a preceding relationship of a parallel program for explaining the operation of the tenth embodiment.

FIG. 122 is a diagram showing a state after rearranging the execution logs of the parallel program for explaining the operation of the tenth embodiment.

FIG. 123 is a diagram showing an example of a modified parallel program for explaining the operation of the tenth embodiment.

FIG. 124 is a diagram showing a schematic configuration of a concurrent program creation support device according to the eleventh embodiment.

FIG. 125 is a flowchart showing a schematic procedure of a parallel program creating method according to the twelfth embodiment.

FIG. 126 is a block diagram showing a schematic configuration of a parallel program creation support device according to the twelfth embodiment.

[Explanation of symbols]

1-1 to 1-N ... Processor 2 ... I / O interface 3 ... Shared memory 4 ... Input device 5 ... Output device 6 ... Storage device 11 ... First CP file storage unit 12 ... Serialization device 13 ... Serialization rule storage unit 14 ... HSP file storage unit 15 ... Test execution device 16 ... Debugging device 17 ... Non-deterministic introduction device 18 ... Parallelization device 19 ... Second CP file storage unit 20 ... Analysis information storage unit 21 ... Parallelization rule storage unit 22 ... Execution device 23 ... Division standard designation device 25 ... Change device 26 ... Serialization rule correction device 31 ... Serialization information storage unit 32 ... Serialization information reading unit 33 ... Parallel structure analysis unit 34 ... Sequential structure analysis unit 35 ... Image data generation unit 51 ... serialization process list storage unit 52 ... field data storage unit 53 ... field data generation unit 54 ... field tuning unit 55 Field editor 201 ... Log information storage unit 202 ... Log information acquisition unit 203 ... Process group control unit 204 ... Message storage unit 205 ... Log information correction unit 301 ... Centralized log information storage unit 302 ... Log information division unit 303 ... Division standard designation unit 304 ... Divided log information storage unit 305 ... Process control unit 306 ... Process waiting message storage unit 401 ... Test execution device 402 ... Test case storage unit 403 ... Execution log storage unit 404 ... Execution log database 411 ... Program analysis unit 412 ... Section information Storage unit 413 ... Section information editing unit 414 ... Compiling unit 415 ... Execution unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshifumi Kaban 70 Yanagicho, Sachi-ku, Kawasaki-shi, Kanagawa, Toshiba Yanagimachi Co., Ltd. (72) Inventor Yasuo Nagai 70, Yanagicho, Sachi-ku, Kawasaki, Kanagawa Toshiba Yanagimachi, Ltd. (72) Inventor Keiichi Handa 70 Yanagi-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture, Yanagimachi Plant, Toshiba Corporation (72) Inventor Satoshi Ito 70, Yanagi-cho, Sachi-ku, Kawasaki City, Kanagawa Prefecture, Yanagicho, Toshiba Corporation (72) Inventor Shinsuke Sawashima 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center (72) Inventor Yasuyuki Tahara 70, Yanagi-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Yanagi-cho Plant (72) Inventor Hideaki Shiotani 70 Yanagimachi, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Yanagimachi Factory

Claims (50)

[Claims] 1. Serializing means for converting a first parallel program having a parallel structure into a serial program that can be serially executed, and test / debug means for performing test / debug of the serial program and creating test / debug information. And a parallelizing means for converting the serial program after the test and debug into a second parallel program by parallelizing the serial program based on the test and debug information. 2. The concurrent program creation support apparatus according to claim 1, wherein the test / debug means includes means for introducing information about concurrency into the sequential program. 3. The concurrent program creation support device according to claim 1, wherein the serial program includes section information, program structure information, and serialization information. 4. The analysis means for analyzing the parallel structure of the first concurrent program is further provided, and the parallelization means is configured to analyze the sequential program tested and debugged by the test / debug means of the analysis means. 2. The parallel program creation support apparatus according to claim 1, further comprising means for parallelizing using the analysis result and converting it into a second parallel program. 5. A serialization means for converting a predetermined section group of a first concurrent program having a parallel structure into a sequentially executable serial program, and a parallel processing for analyzing a parallel structure of the predetermined section group of the first concurrent program. A structural analysis means, a sequential structure analysis means for analyzing a sequential structure of a predetermined section group of the sequential program, a mutual relation regarding the parallel structure analyzed by the parallel structure analysis means, and a sequential analyzed by the sequential structure analysis means Graph information display means for displaying the mutual relation regarding the structure as graph information, and partial serialization means for parallelizing a selected predetermined section group in the sequential program and converting it into a partial sequential program partially having a sequential structure A parallelizing means for parallelizing the partial sequential program and converting it into a second parallel program. Concurrent program creation support apparatus, characterized in that. 6. The serializing means executes means for executing the first parallel program, saving means for saving an execution log by the executing means, execution log saved by the saving means, and the first parallelism. The analysis means for analyzing a program, and the rearrangement means for rearranging the execution logs stored by the storage means based on the analysis result by the analysis means are included. The parallel program creation support device described in any one of the above. 7. The execution means is a program analysis means for analyzing the first parallel program to extract section information, a section information storage means for storing the section information, and a section information storage means for storing the section information. 7. The section information changing means for changing the section information, and the parallel program executing means for executing the parallel program based on the section information stored by the section information storage means. Parallel program creation support device. 8. The introduction means converts the process flow of the sequential program into a field consisting of constraints and transition conditions to generate field data representing the field, and field data generation means. 4. A tuning means for tuning a field represented by field data, and a display means for displaying a field represented by the field data generated by said field data generating means. Item 6. A parallel program creation support device according to any one of items 5. 9. The serializing means includes means for converting the first concurrent program into a plurality of hyper sequential programs, and the test / debug means independently tests and debugs the hyper sequential programs. 5. The concurrent program creation support device according to claim 1, further comprising: 10. A serialization means for converting a predetermined process group of a first parallel program having a parallel structure into a serial program that can be sequentially executed according to a predetermined execution order, and a candidate for parallelization of the sequential structure program. Process group designating means for designating a process group, a simulated parallel program conversion means for transposing the sequential program into a plurality of parallel simulation programs by exchanging the execution order of the process groups designated by the means, and the plurality of parallel simulation programs. A partial serializing means for converting a program into one partial sequential program having a partial serial structure, and a parallelizing means for parallelizing the partial serial program and converting it into a second parallel program. Concurrent program creation support device. 11. A serialization rule storage unit for storing a serialization rule, and a first concurrent program having a parallel structure according to the serialization rule stored in the serialization rule storage unit is converted into a serial program that can be serially executed. Serializing means, serializing rule modifying means for modifying the serializing rule stored in the serializing rule storing means to introduce information about concurrency into the serial program, and test / debug of the serial program. A test / debug means for performing the test, and information about concurrency introduced by the serialization rule modifying means and a test / debug means by the test / debug means.
A parallel program creation support device comprising: a parallelizing means for parallelizing a debugged serial program and converting it into a second parallel program. 12. The execution history of a process group of a first concurrent program in a concurrent program creation support device for supporting creation of a concurrent program used in an execution environment in which process groups exchange message information and operate in parallel. Log information acquisition means for acquiring log information as a serialization rule, log information storage means for storing the log information acquired by the log information acquisition means, and modifying the log information stored in the log information storage means Log information correction means, a process group control means for sequentially controlling activation of the process groups based on the log information stored in the log information storage means, and log information stored in the log information storage means Parallelizing means for parallelizing and converting the second parallel program to a second parallel program Assistance devices. 13. The log information correction means includes a display means for displaying the log information stored in the log information storage means in time series, and a data in the log information displayed in time series by the display means. 13. The method according to claim 12, further comprising replacement instruction means for instructing order replacement, and rewriting means for rewriting the log information stored in the log information storage means in accordance with an instruction from the replacement instruction means. Concurrent program creation support device. 14. The parallel program creation support apparatus according to claim 12, wherein the log information correction means includes non-determinism introduction means for introducing non-determinism of processing timing between processes. 15. A parallel program creation support device for supporting the creation of a parallel program in which the process groups operate according to execution order definition information in an execution environment in which the process groups can operate in parallel while exchanging message information. A parallel program creation support comprising: an execution order information dividing unit that divides information; and a process control unit that controls activation of the process based on the execution order information divided by the execution order information dividing unit. apparatus. 16. The parallel program creation support apparatus according to claim 15, further comprising means for holding a division criterion designating means for giving a criterion for dividing the execution order defining information. 17. The process control means uses log information, which is an execution history of the message exchange, as execution order defining information, and uses the destination process information in the message as a reference for division in the division reference specifying means. 16. The parallel program creation support device according to claim 15, wherein: 18. A means for holding the process control means for each process is provided.
The parallel program creation support device described. 19. The divided execution order information storage means for separately storing the execution order information divided by the execution order information division means, wherein the process control means corresponds to the divided execution order information storage means. 19. The parallel program creation support apparatus according to claim 18, further comprising means for controlling the activation of the process based on the divided execution order information stored in. 20. The parallel program creation support apparatus according to claim 15, wherein the process control means uses log information, which is an execution history of the process group, as the execution order definition information. 21. A sequential test execution means for sequentially executing a test of a first parallel program having a parallel structure, and a bug-free sequential execution result of a test execution result as a result of the test execution by the test execution means. Parallel execution means for accumulating an execution log and a parallelization means for parallelizing the sequential execution log accumulated by the execution log accumulation means and converting it into a second parallel program. Program creation support device. 22. Test execution means for performing test execution of a first parallel program having a parallel structure, first execution log storage means for storing a bug-free execution log as a result of test execution by the test execution means, and the test. Second execution log storage means for storing an execution log having a bug as a result of test execution by the execution means; and correction of the execution log stored by the second execution log storage means, and the corrected execution log is stored as the first execution log. And a parallelizing means for parallelizing the execution log accumulated by the first execution log accumulating means and converting the execution log accumulated in the first execution log accumulating means into a second parallel program. A parallel program creation support device. 23. A first step of converting a first concurrent program having a parallel structure into a sequential program that can be sequentially executed, and a second step of performing test / debug of the sequential program and creating test / debug information. And a third step of converting the serial program after the test and debug into a second parallel program by parallelizing the serial program based on the test and debug information. 24. The method according to claim 23, wherein the second step includes a sub-step of introducing information about concurrency into the sequential program. 25. The first step includes a sub-step of analyzing a parallel structure of the first concurrent program, and the third step converts the sequential program after test / debug into the parallel structure of the first concurrent program. 24. The parallel program creating method according to claim 23, further comprising a sub-step of parallelizing using the. 26. The method according to claim 23, wherein the second step includes a substep of introducing nondeterminism specified for the sequential program as information on the concurrency. The parallel program creation method described in. 27. The first step comprises: a first substep of converting a predetermined section group of the first concurrent program having a parallel structure into a sequentially executable sequential program; and a predetermined section of the first concurrent program. A second sub-step of analyzing a parallel structure of a group, a third sub-step of analyzing a sequential structure of a predetermined section group of the sequential program, an interrelationship of the parallel structure analyzed in the second sub-step, and the A fourth sub-step of displaying the mutual relationship regarding the sequential structure analyzed in the three sub-steps as graph information, and a partial sequential program having a partial sequential structure by parallelizing a predetermined group of sections selected from the sequential program A fifth sub-step of converting the partial sequential program into Go to parallel programming method of claim 23, characterized in that it comprises a sub-step of converting the second concurrent program. 28. A first step of converting a predetermined section group of the first concurrent program having a parallel structure into a sequentially executable sequential program, and analyzing a parallel structure of the predetermined section group of the first concurrent program. A second step, a third step of analyzing a sequential structure of a predetermined section group of the sequential program, a mutual relation of the parallel structure analyzed in the second step, and a mutual relation of the sequential structure analyzed in the third step. A fourth step of displaying the relationship as graph information, a fifth step of parallelizing a selected predetermined section group of the sequential program and converting it into a partial sequential program partially having a sequential structure, and the partial sequential program And a sixth step of parallelizing and converting the second parallel program into a second parallel program. Concurrent program how to create that. 29. The parallel program creation according to claim 28, wherein the first substep includes a substep of performing test / debug of the sequential program until a desired execution result of the sequential program is obtained. Method. 30. The fourth sub-step displays the graph information with the predetermined section group as a node, the mutual relationship regarding the parallel structure as a first arc, and the mutual relationship regarding the sequential structure as a second arc. 29. The method according to claim 28, further comprising substeps. 31. The parallel processing according to claim 28, wherein the fifth sub-step includes a sub-step of testing and debugging the partial sequential program until a desired execution result of the partial sequential program is obtained. How to create a program. 32. The fifth sub-step includes a sub-step of analyzing a sequential structure of a predetermined section group in the partial sequential program, and the first step includes the fourth to fifth sub-steps. 29. The concurrent program creating method according to claim 28, further comprising a sub-step of repeating the number of times. 33. The first step comprises: a first sub-step for executing the first concurrent program; a second sub-step for storing an execution log by the first sub-step; and a second sub-step. A third sub-step of analyzing the execution log and the first concurrent program, and a fourth sub-step of rearranging the execution log stored by the second sub-step based on the analysis result of the third sub-step. 3. The method according to claim 2, wherein
The parallel program creating method according to any one of claims 3 to 25, 28 or 29. 34. The third sub-step includes a sub-step of extracting a preceding relationship of processes from the execution log and the first concurrent program saved by the second sub-step and saving it as preceding relationship information. The parallel program creation method according to claim 33. 35. The second step introduces a substep of converting the process flow of the sequential program into a field consisting of constraints and transition conditions, a substep of tuning the field, and information about the concurrency. 26. The concurrent program creating method according to claim 23, further comprising a substep. 36. A first step of converting a predetermined process group of a first parallel program having a plurality of process groups and having a parallel structure into a sequential program that can be sequentially executed according to a predetermined execution order; A second step of designating a process group that is a candidate for parallelization, and a third step of exchanging the execution order of the process group designated by the second step and converting the sequential program into a plurality of parallel simulation programs, A fourth step of converting the plurality of parallel simulation programs into one partial sequential program having a partial sequential structure; and a fifth step of parallelizing the partial sequential program and converting it into a second concurrent program. A method for creating a parallel program characterized by the above. 37. The method according to claim 36, wherein the first step includes a sub-step of performing test / debug of the sequential program until a desired execution result of the sequential program is obtained. . 38. The second step includes a substep of analyzing the first concurrent program, and a substep of extracting a process group that is a candidate for the parallelization from the analysis result. The parallel program creating method according to claim 36. 39. The third step includes a sub-step of performing test / debug of the plurality of parallel simulation programs until a desired execution result of the plurality of parallel simulation programs is obtained. How to create a parallel program as described. 40. The concurrent program according to claim 36, wherein the third step includes a sub-step of removing a concurrent simulation program determined to be unnecessary from execution results of a part of the plurality of concurrent simulation programs. How to make. 41. The fourth step includes a substep of designating a process group that is a candidate for parallelization for the partial sequential program, and a step of repeating the third step to the fourth step a predetermined number of times. The parallel program creating method according to claim 36, further comprising: 42. The first step comprises: a first substep of converting the first concurrent program into the sequential program according to a serialization rule; and the serial step of introducing information about concurrency into the sequential program. A second sub-step of modifying the parallelization rule, wherein the third step parallelizes the serial program based on the test / debug information and the information about the concurrency, and converts the serial program into a second concurrent program. 24. The concurrent program creation method according to claim 23, further comprising substeps. 43. A first step of test-executing a first concurrent program having a parallel structure, a second step of accumulating a bug-free execution log as a result of the test execution by the first step, and an accumulation of the second step. A third step of parallelizing the executed execution log into a second parallel program,
A method for creating a parallel program, comprising: 44. A fourth step of accumulating an execution log having a bug as a result of the test execution by the first step, and modifying the first concurrent program based on the execution log accumulated by the fourth step, The parallel program creating method according to claim 43, further comprising a fifth step of accumulating execution logs again. 45. Program analysis means for analyzing a parallel program to extract section information, section information storage means for storing the section information, and the parallel processing based on the section information stored by the section information storage means. A parallel program execution device, comprising: a parallel program execution means for executing a program. 46. At least one of a section information editing unit that edits section information stored by the section information storage unit and a compiling unit that converts each section in the section information stored by the section information storage unit into an object. The parallel program execution device according to claim 45, further comprising: 47. The parallel program execution according to claim 45, wherein said program analysis means further includes means for converting an inputted program into an intermediate language and means for extracting a section from said intermediate language. apparatus. 48. An execution section candidate storage means for storing a candidate for a section to be executed by the execution means, and an execution section selection means for selecting a section to be executed next from the sections stored by the execution section candidate storage means. 46. The concurrent program execution device according to claim 45, further comprising: section execution means for executing the section selected by the execution section selection means. 49. The concurrent program execution device according to claim 48, wherein said execution section selection means includes a mode for selecting one executable section and a mode for selecting all the executable sections. 50. The concurrent program execution device according to claim 48, wherein said execution section execution means executes those sections in parallel when there are a plurality of sections selected by said execution section selection means.