JPH08162942A - Output circuit, input circuit and input/output interface system using them - Google Patents

Abstract

PURPOSE: To provide an output circuit, an input circuit and an input/output interface system using them capable of transmitting signals at a high speed with low power consumption. CONSTITUTION: Complementary logic signals DT and /DT outputted from an internal circuit IS1 are converted to complementary current signals IO and /IO in this output circuit OP1 and outputted to transmission lines T1 and T2 in a current mode. This input circuit IP1 converts the inputted complementary current signals IO and /IO to complementary voltage signals VO and /VO and outputs them to the internal circuit IS11 in a voltage mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit and an input circuit for transmitting data using a current mode, and an input / output interface system using these.

[0002]

2. Description of the Related Art Conventionally, as a standard for data transfer between semiconductor devices, TTL (Transistor-Transi) is used.
store Logic), LVTTL (Low Vol)
interface TTL) and other interface standards. These transmission methods are based on the voltage mode in which the amplitude of the voltage of the signal to be transmitted is changed and the change in the amplitude is detected. However, as the operating frequency of semiconductor devices increases, problems such as delay and reflection occur when signals having a frequency of 100 MHz or higher are transmitted. Therefore, G
TL (Gunning Transceiver Lo)
gic), CTT (Center Tapered Te)
, and small amplitude interface standards have been proposed. Output circuits used in these small-amplitude interface standards include push-pull type output circuits and open-drain type output circuits.

First, a push-pull type output circuit which is a conventional output circuit will be described with reference to the drawings. FIG.
2 is a block diagram showing a configuration of an input / output interface system using a conventional push-pull type output circuit.

With reference to FIG. 12, the input / output interface system includes semiconductor devices IC101 and IC111.
Including the transmission line T101. Semiconductor device IC101
Includes an internal circuit IS101 and an output circuit OP101.
The output circuit OP101 is a PMOS transistor Q10.
1, including an NMOS transistor Q102. The semiconductor device IC111 includes a resistor R101, an input circuit IP101, and an internal circuit IS111. The input circuit IP101 includes a comparator CP101.

The push-pull type output circuit OP101 is
It is composed of a pull-up PMOS transistor Q101 and a pull-down NMOS transistor Q102. PMOS transistor Q101 and NMOS
The gate of the transistor Q102 has an internal circuit IS10.
1 receives the signal output from 1. Output circuit OP101
Outputs a high-level or low-level output signal to the transmission line T101 according to the input signal. At this time, the output signal is the PMOS transistor Q101.
And a signal driven by the NMOS transistor Q102.

On the other hand, the input circuit IP101 is composed of a comparator CP101. The signal input via the transmission line T101 is input to the comparator CP101. The comparator CP101 has an input node N10.
The potential of 1 is compared with the potential of the reference potential Vref, and an output signal is output to the internal circuit IS111 according to the comparison result. Here, the terminating resistor R10 is connected to the input node N101.
1 is connected, the other end of the terminating resistor 101 is connected to a predetermined terminating potential VTT, and the potential of the input node N101 is terminated to the terminating potential VTT. Therefore, the transmission line T
The characteristic impedance of 101 and the impedance of the terminating resistor R101 are matched. With the above configuration, a signal is transmitted from the output circuit OP101 of the semiconductor device IC101 to the semiconductor device IC111 via the transmission line T101.

Next, a conventional open drain type output circuit will be described. FIG. 13 is a block diagram showing the configuration of an input / output interface system using a conventional open drain type output circuit. The difference between the input / output interface system shown in FIG. 13 and the input / output interface system shown in FIG. 12 is that the output circuit OP101 is changed to the output circuit OP102, and the other points are the same. Is omitted.

Referring to FIG. 13, semiconductor device IC 102
Includes an internal circuit IS101 and an output circuit OP102.
The output circuit OP102 is an NMOS transistor Q103.
including.

Open drain type output circuit OP102
Is composed of a pull-down NMOS transistor Q103. The gate of the NMOS transistor Q131 receives the signal output from the internal circuit IS101.
The NMOS transistor Q103 outputs a low level output signal according to the input signal. On the other hand, with respect to the high-level output, a high-level signal is transmitted by weakening the driving force of the NMOS transistor Q103 and setting the termination potential VTT higher than the reference potential Vref. By the above operation, a signal is transmitted from the output circuit OP102 of the semiconductor device IC102 to the semiconductor device IC111 via the transmission line T101.

Next, the GTL standard input / output interface system will be described. FIG. 14 is a block diagram showing the configuration of a conventional GTL standard input / output interface system.

Referring to FIG. 14, the input / output interface system includes semiconductor devices IC103 and IC112,
The transmission line T101 is included. The semiconductor device IC103 includes an internal circuit IS101, an output circuit OP103, and a terminating resistor R1.
Including 02. The output circuit OP103 is an inverter G10.
1, G102, PMOS transistor Q104, NMO
Includes S transistors Q105 to Q108. The semiconductor device IC112 includes an internal circuit IS111 and an input circuit IP10.
2 inclusive. The input circuit IP102 includes PMOS transistors Q111 to Q113 and an NMOS transistor Q11.
4, including Q115.

The GTL standard output circuit OP103 is composed of an open drain type circuit, and in order to alleviate the waveform distortion at the time of turn-off, the NMOS transistor Q1 is used.
06 and Q107 are NMOS transistors Q108
Gradually turn off. The output node N111 is terminated to the termination potential VTT via the termination resistor R102. Therefore, the characteristic impedance of the transmission line T101 and the impedance of the terminating resistor R102 are matched. NMOS transistor Q10
A low level signal is output by 8, and a high level signal is generated by weakening the driving force of the NMOS transistor Q108 and setting the termination potential VTT higher than the reference potential Vref for the high level output.

On the other hand, the input circuit IP102 is composed of a differential amplifier circuit including PMOS transistors Q111 to Q113 and NMOS transistors Q114 and Q115. The input circuit IP102 has an input node N
The potential of 112 is compared with the reference potential Vref, and the comparison result is output to the internal circuit IS111. By the above operation,
The semiconductor device I from the IC 103 via the transmission line T101.
A signal is transmitted to C112.

Next, the CTT standard input / output interface system will be described. FIG. 15 is a block diagram showing the configuration of the CTT standard input / output interface system.

Referring to FIG. 15, the input / output interface system includes semiconductor devices IC104 and IC113,
The transmission line T1 is included. The semiconductor device IC104 includes an internal circuit IS102 and an output circuit OP104. Output circuit O
P104 is a control logic circuit CL and a comparator CP10.
2, PMOS transistors Q121, Q122, NMO
It includes S transistors Q123 and Q124. The semiconductor device IC113 includes an internal circuit IS111 and an input circuit IP10.
3, including a terminating resistor R103. The input circuit IP103 is
A comparator CP103 is included.

The CTT standard output circuit OP104 is composed of two sets of output drivers. These drivers are operated simultaneously, and after the output exceeds the high-level / low-level reference potential, the output of the comparator CP102 is fed back to the control logic circuit CL to control the control logic circuit C.
It is controlled to cut off the output driver connected to L. The semiconductor device IC113 operates similarly to the semiconductor device IC111 shown in FIG. By the above operation, the transmission line T from the semiconductor device IC 104
A signal is transmitted to the semiconductor device IC 113 via 1.

[0017]

In each of the above conventional examples,
In any interface standard, signals were transmitted by voltage changes. Therefore, when the total capacitance of the board wiring is large, it is necessary to charge or discharge the capacitance. As a result, an output buffer for flowing a large current is required for signal transmission, and board wiring capacitance is charged and discharged, resulting in a large current consumption of an input circuit and an output circuit used for an input / output interface. was there. Further, due to the mismatch between the output impedance of the output circuit and the characteristic impedance of the transmission line, and the mismatch between the characteristic impedance of the transmission line and the input impedance of the input circuit, the signal is reflected and the signal cannot be transmitted at high speed. There was also.

In addition to the voltage mode input / output interface system described above, there is a current mode input / output interface system. An ECL (Emitter Coupled L) is used as a current mode interface.
known) interfaces are known. For example,
Mr. Tomoaki KAWAMURA (NTT LSI
Lab. ) Published the paper "An Extr
emery Low-power Bpolar Cu
current-mode I / O Circuit fo
r Multi-Gbit / s Interface
s ”(1994 Symposium on VlSI
Circuits Digital of Techn
ical Papers). The above paper discloses a current mode interface circuit using bipolar transistors. The output circuit of this circuit is
The input circuit is composed of a current switch driver composed of complementary bipolar transistors.
The common base bipolar transistor is configured to receive the differential current.

The use of the above output circuit and input circuit has the following problems. First, when a bipolar transistor is used, the process becomes expensive. Moreover, since a bias current is required, it is not suitable for low power consumption. Furthermore, since the output circuit and the input circuit described above are circuits that utilize the characteristics of bipolar transistors, M
Replacement with an OS transistor cannot be easily performed. Further, the above output circuit and input circuit are
Since it is a circuit in consideration of compatibility with the interface, it is difficult to replace it with an interface for a general semiconductor memory device. There were the above problems.

Other current mode ECL interfaces include an output circuit disclosed in Japanese Patent Application Laid-Open No. 4-207223, an output circuit disclosed in Japanese Patent Application Laid-Open No. 4-207224, and Japanese Patent Application Laid-Open No. 62-53518. There is an output buffer circuit for an integrated circuit disclosed in the publication. The circuits disclosed in each of these publications are based on an E using a MOS transistor.
This is a circuit for CL interface. Each of the above circuits
Since the circuit is compatible with the ECL interface, it is different from the usage environment of general devices (devices other than ultra-high speed devices, etc.), so it is difficult to apply it to general semiconductor memory device interfaces. There was a problem.

The current sense circuit may be, for example, Ever Seevinck (Senior M).
Ember, IEEE), Petrus J. et al. van
Paper "Current-Mode Tec" published by Bers, and Hans Ontrop
hnies for High-Speed VL
SI Circuits with applicat
ion to Current Sense Ampl
ifer for CMOS SRAM's ”(IE
EE JOURNAL OF SOLID-STATE
CIRCUITS, VOL. 26, NO. 4, APR
IL 1991). This circuit is used to sense and amplify the data in the memory cell array. Actually, a current of several tens of μA to several hundreds of μA is detected, the current is converted into a voltage, and a few hundred mV is converted.
Used to convert the voltage difference of. This circuit is effective when the bit line connected to the memory cell array has a relatively large capacitance. However, this circuit is used for data detection of the memory cell array, and it is difficult to apply it to the above-mentioned input / output interface.

An object of the present invention is to provide an input circuit, an output circuit, and an input / output interface system using these, which can transfer data at high speed and suppress power consumption to a low level.

Still another object of the present invention is to provide an input circuit, an output circuit, and an input / output interface system suitable for a general semiconductor memory device.

[0024]

An output circuit according to claim 1 is an output circuit for transmitting first and second complementary current signals which are complementary to each other to the outside in a current mode through a transmission line, and which are complementary to each other. Output first and second complementary current signals in current mode according to the potentials of the first and second complementary logic signals input to the input terminals and the first and second complementary logic signals. Output means for

In addition to the configuration of the output circuit according to claim 1, the output circuit according to claim 2 is connected to the terminal of the output means,
It further includes resistance means for receiving a predetermined termination potential.

In the output circuit according to a third aspect of the present invention, in addition to the configuration of the output circuit according to the second aspect, the resistance means includes first and second resistors whose one end receives a termination potential, and the output means includes a current source and a current source. , A first N having a gate for receiving a first complementary logic signal, one end of which is connected to the first resistor and the other end of which is connected to a current source
A MOS transistor and a second NMOS transistor having a gate for receiving a second complementary logic signal, one end of which is connected to the second resistor and the other end of which is connected to a current source are included.

According to a fourth aspect of the present invention, in addition to the configuration of the output circuit according to the first aspect, the output means has a gate for receiving a first complementary logic signal, and a first end receives a ground potential.
A second pull-down NMOS transistor and a gate for receiving a second complementary logic signal, and a second end for receiving a ground potential
And a pull-down NMOS transistor.

According to a fifth aspect of the present invention, in addition to the configuration of the first aspect of the output circuit, the output means has a gate for receiving a first complementary logic signal, and a first end for receiving a power supply voltage.
A second pull-up PMOS transistor, a gate for receiving a second complementary logic signal, and a second end for receiving a power supply voltage
And a pull-up PMOS transistor.

An input circuit according to a sixth aspect of the present invention is an input circuit for receiving first and second complementary current signals which are complementary to each other and which are transmitted from the outside in a current mode through a transmission line.
And an input end receiving the second complementary current signal, and a current change of the first and second complementary current signals input to the input end converted into a voltage change, and the input and the second complementary current signals corresponding to the currents of the first and second complementary current signals are mutually converted. It includes converting means for internally outputting complementary first and second complementary voltage signals in a voltage mode.

According to a seventh aspect of the present invention, in addition to the configuration of the input circuit according to the sixth aspect, the converting means includes first and second converting means.
A current-convey circuit that differentially converts the current of the complementary current signal and converts the current change into a voltage change is included.

In addition to the configuration of the input circuit according to claim 7, the input circuit according to claim 8 is characterized in that the current conveyor circuit has a first load receiving a first complementary current signal at one end and a power supply voltage at the other end. And a first P whose one end is connected to one end of the first load
A MOS transistor, a second PMOS transistor having one end connected to the other end of the first PMOS transistor and having a gate for receiving the ground potential, and a second load having one end connected to the other end of the second PMOS transistor and receiving the ground potential at the other end. A third load that receives a second complementary current signal at one end and a power supply voltage at the other end, one end that is connected to one end of the first load, and the other end that is connected to the gate of the first PMOS transistor. A third PMOS transistor having a gate for receiving the potential at the connection point of the second PMOS transistor, and one end of the third PMOS transistor and the other end of the third PMOS transistor
A fourth PMOS transistor including a fourth PMOS transistor having a gate connected to the gate of the PMOS transistor and having a ground potential, and a fourth load having one end connected to the other end of the fourth PMOS transistor and having the other end receiving the ground potential; The first complementary voltage signal is output from the connection point with the second load, and the second complementary voltage signal is output from the connection point with the fourth PMOS transistor and the fourth load.

According to a ninth aspect of the present invention, in addition to the configuration of the input circuit according to the seventh aspect, the current conveyor circuit has a first load receiving a first complementary current signal at one end and a ground potential at the other end. And a first N whose one end is connected to one end of the first load
A second load having a MOS transistor, one end of which is connected to the other end of the first NMOS transistor and having a gate for receiving a power supply voltage, and one end of which is connected to the other end of the second NMOS transistor and whose other end receives the power supply voltage. A third load that receives the second complementary current signal at one end and a ground potential at the other end, one end connected to one end of the first load, the other end connected to the gate of the first NMOS transistor, and A third NMOS transistor having a gate for receiving the potential of the connection point of the second NMOS transistor, and one end of the third NMOS transistor and the other end of the third NMOS transistor
A fourth NMOS transistor having a gate connected to the gate of the NMOS transistor and having a power supply voltage; a fourth load having one end connected to the other end of the fourth NMOS transistor and having the other end receiving the power supply voltage; The first complementary voltage signal is output from the connection point with the second load, and the second complementary voltage signal is output from the connection point with the fourth NMOS transistor and the fourth load.

In addition to the structure of the input circuit according to claim 6, the input circuit according to claim 10 has a first input terminal for receiving a first complementary voltage signal and a second input terminal for receiving a second complementary voltage signal. The input circuit includes an input terminal, one end of which is connected to the first input terminal, the other end of which is connected to the first terminating resistor that receives a predetermined terminating potential, and one end of which is connected to the second input terminal and which is connected to the other end of the predetermined input terminal. It further includes a second terminating resistor that receives a terminating potential.

The input circuit according to claim 11 is an input circuit which receives a current signal transmitted from the outside in a current mode via a transmission path, and a comparison means for comparing the potential of the current signal with a predetermined reference potential. And an output means for outputting a voltage signal corresponding to the current of the current signal to the inside in the voltage mode in accordance with the comparison result by the comparison means.

An input circuit according to claim 12 is the input circuit according to claim 11.
In addition to the configuration of the input circuit described, the comparison means includes a comparator that receives the current signal at the negative side input terminal and the reference voltage at the positive side input terminal, and the output means has a gate that receives the output signal of the comparator. , N receiving a current signal at one end
A voltage signal is output from a connection point between the NMOS transistor and the load, which includes a MOS transistor and a load having one end connected to the other end of the NMOS transistor and the other end receiving a power supply voltage.

The input circuit according to claim 13 is the same as in claim 11.
In addition to the configuration of the input circuit described, the comparison means includes a comparator that receives the current signal at the positive side input terminal and the reference potential at the negative side input terminal, and the output means has a gate that receives the output signal of the comparator. , A first PMOS transistor that receives a current signal at one end and a power supply voltage at the other end, a second PMOS transistor that has a gate that receives the output signal of the comparator, one end that receives the power supply voltage, and one end that is the other end of the second PMOS transistor A voltage signal is output from the connection point between the second PMOS transistor and the load, the load signal being connected to the second PMOS transistor and the load receiving the ground potential at the other end.

According to a fourteenth aspect of the present invention, there is provided the input circuit of the eleventh aspect.
In addition to the configuration of the input circuit described above, the comparison unit has a first NMOS transistor receiving a current signal at one end, and one end and a gate connected to the other end of the first NMOS transistor,
A first PMOS transistor receiving a power supply voltage at the other end,
One end receives the reference potential, and the other end and gate are the first NMO
A second NMOS transistor connected to the gate of the S transistor, one end of which is connected to the other end and the gate of the second NMOS transistor, and the other end of which receives the power supply voltage
A first PMOS transistor having a gate connected to the gate of the MOS transistor and a connection point between the first NMOS transistor and the first PMOS transistor, and the output means has a gate connected to the gate of the second PMOS transistor, and at one end Third receiving power supply voltage
A voltage signal is output from a connection point between the third PMOS transistor and the load, the PMOS transistor and the load including one end connected to the other end of the third PMOS transistor and receiving the ground potential at the other end.

The input circuit according to the fifteenth aspect is the eleventh aspect.
In addition to the configuration of the input circuit described, the comparison means includes a first PMOS transistor that receives a current signal at one end and a first PMOS transistor at one end.
A first NMOS transistor connected to the other end of the PMOS transistor and receiving a ground potential at the other end;
A resistor connected to the gate of the MOS transistor, the other end of which receives the reference potential, and one end of the resistor and the first PMO.
A second PMOS transistor having a gate connected to the gate of the S transistor and having a connection point between the first PMOS transistor and the first NMOS transistor; one end connected to the other end of the second PMOS transistor and the other end receiving a ground potential A second NMOS transistor having a gate connected to the other end of the second PMOS transistor and the gate of the first NMOS transistor, the output means having a gate connected to the gate of the second NMOS transistor, and the ground potential at the other end. The voltage signal is output from the connection point of the third NMOS transistor and the load, the one end of which is connected to the other end of the third NMOS transistor and the other end of which is a load receiving the power supply voltage.

According to a sixteenth aspect of the present invention, in the input / output interface system, the first and second complementary semiconductor devices in the current mode are provided from the output semiconductor device to the input semiconductor device via the transmission line.
An input / output interface system for transmitting a complementary current signal in a current mode, wherein the output semiconductor device includes an output circuit for outputting the first and second complementary current signals to a transmission line in a current mode, and the input semiconductor device is , First and second complementary voltage signals that are complementary to each other according to the currents of the first and second complementary current signals, by converting the current changes of the first and second complementary current signals input via the transmission path into voltage changes It includes an input circuit for outputting the voltage in a voltage mode.

According to a seventeenth aspect of the present invention, in addition to the configuration of the sixteenth aspect of the input / output interface system, the input semiconductor device has a first input terminal for receiving a first complementary voltage signal and a second complementary terminal. A second input end for receiving the current signal, one end connected to the first input end, a first terminating resistor for receiving a predetermined termination potential at the other end, one end connected to the second input end, and a predetermined end for the other end It further includes a second terminating resistor that receives a terminating potential.

The input / output interface system according to claim 18 is an input / output interface system for transmitting a current signal in a current mode from an output semiconductor device to an input semiconductor device via a transmission path, wherein the output semiconductor device is ,
The input semiconductor device includes an output circuit configured to include a MOS transistor and outputting a current signal to the transmission line in a current mode. The input semiconductor device converts a current change of the current signal input through the transmission line into a voltage change, and converts the current signal into a voltage change. It includes an input circuit for outputting a voltage signal according to the voltage to the inside in a voltage mode.

[0042]

In the output circuit according to any one of claims 1 to 5, the first and second complementary current signals according to the complementary first and second complementary logic signals can be output to the outside in the current mode. .

According to another aspect of the input circuit of the present invention, the first complementary signals are transmitted in the current mode.
And a current change of the second complementary current signal is converted into a voltage change, and first and second complementary voltage signals complementary to each other corresponding to the currents of the first and second complementary current signals are internally output in a voltage mode. it can.

In the input circuit according to any one of claims 11 to 15, the potential of the current signal transmitted in the current mode is compared with a predetermined reference potential, and the voltage corresponding to the current of the current signal is determined according to the comparison result. The signal can be output internally in voltage mode.

In the input / output interface system according to the sixteenth and seventeenth aspects, the first and second complementary current signals can be output from the output semiconductor device to the transmission line in the current mode, and the input semiconductor device is , Converting the current changes of the input first and second complementary current signals into voltage changes, and internally converting the complementary first and second complementary current signals corresponding to the currents of the first and second complementary current signals in the voltage mode. Can be output to.

In the input / output interface system according to the eighteenth aspect, a current signal can be output to the transmission line in the current mode from the output means constituted by the MOS transistor of the output semiconductor device, and the input semiconductor device is
The current change of the input current signal can be converted into a voltage change, and a voltage signal according to the current of the current signal can be internally output in the voltage mode.

[0047]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the input / output interface system of the first embodiment of the present invention.

Referring to FIG. 1, the input / output interface system includes semiconductor devices IC1 and IC11 and transmission lines T1 and T2. In this embodiment, complementary current signals complementary to each other in the current mode are transmitted from the semiconductor device IC1 to the semiconductor device IC11 via the transmission lines T1 and T2. As the semiconductor device IC1, a general semiconductor memory device such as a dynamic random access memory, a synchronous dynamic random access memory, or a static random access memory is used. Semiconductor device I
An arithmetic processing unit such as a microprocessor is used as C11. Conversely, an arithmetic processing unit may be used as the semiconductor device IC1 and a general semiconductor memory device may be used as the semiconductor device IC11. Furthermore, the semiconductor device I
A general semiconductor memory device may be used for both C1 and IC11, or an arithmetic processing device may be used. The same applies to each of the following embodiments.

The semiconductor device IC1 includes an internal circuit IS1 and an output circuit OP1. Output circuit OP from internal circuit IS1
Complementary logic signal D which is an internal data signal complementary to 1
T and / DT are input to the output circuit OP1.

The output circuit OP1 includes terminating resistors R1, R2,
It includes an NMOS transistor Q1Q2 and a current source I1. A predetermined termination potential VTT is supplied to one end of the termination resistor R1. The other end of the terminating resistor R1 is connected to one end of the NMOS transistor Q1. The complementary logic signal DT is supplied to the gate of the NMOS transistor Q1. The other end of the NMOS transistor Q1 is connected to one end of the current source I1. The ground potential is supplied to the other end of the current source I1. Termination resistance R2
A terminal potential VTT is supplied to one end of the. Termination resistance R2
The other end of is connected to one end of the NMOS transistor Q2. A complementary logic signal / DT is supplied to the gate of the NMOS transistor Q2. The other end of the NMOS transistor Q2 is connected to one end of the current source I1. Termination resistors R1 and N
A node N1 which is a connection point with the MOS transistor Q1 is connected to the transmission line T1. A node N2, which is a connection point between the terminating resistor R2 and the NMOS transistor Q2, is connected to the transmission line T2.

As described above, the NMOS transistor Q1
And Q2 and the current source I1 constitute a differential data output circuit. Therefore, according to the complementary logic signals DT and / DT output from the internal circuit IS1, the node N
Complementary current signals IO and / IO which are complementary to each other are output from 1 and N2 to the transmission lines T1 and T2, respectively. The terminating resistors R1 and R2 may be provided inside the semiconductor device IC1 in advance as shown in FIG.
It may be connected outside the.

The semiconductor device IC11 has an internal circuit IS1.
1, including the input circuit IP1. The input circuit IP1 has a load L
1 to L4 and PMOS transistors Q11 to Q14. The power supply voltage VCC is supplied to one end of the load L1.
The transmission line T1 and one end of the PMOS transistor Q11 are connected to the node N11 at the other end of the load L1. P
The other end of the MOS transistor Q11 is connected to one end of the PMOS transistor Q13. PMOS transistor Q
The node N16, which is the other end of 13, is connected to one end of the load L3 and the internal circuit IS11. The gate of the PMOS transistor Q13 is supplied with the ground potential via the node N15. The ground potential is supplied to the other end of the load L3. The power supply voltage VCC is supplied to one end of the load L2. Load L
2 is the other end of node N12,
It is connected to one end of MOS transistor Q12. PMO
The gate of S transistor Q12 is connected to node N13 which is a connection point of PMOS transistors Q11 and Q13. The other end of the PMOS transistor Q12 is a PMOS
It is connected to one end of the transistor Q14. A node N1 which is a connection point of the PMOS transistors Q12 and Q14
4 is connected to the gate of the PMOS transistor Q11. The gate of the PMOS transistor Q14 is the node N1.
A ground potential is supplied via 5. The node N15, which is the other end of the PMOS transistor Q14, is connected to one end of the load L4 and the internal circuit IS11. The ground potential is supplied to the other end of the load L4.

As described above, by connecting the two PMOS transistors Q11 and Q12 in a cross-couple type and connecting the PMOS transistors Q13 and Q14 to their drain terminals, respectively, a current-convey circuit is formed. Therefore, the complementary current signals IO and / IO are transmitted from the transmission lines T1 and T2 to the node N1.
1, N12. In the so-called differential mode in which the complementary current signals IO and / IO are reverse currents, the input impedance of the input circuit IP1 is small. On the contrary, in the common mode in which currents of the same magnitude and in the same direction are input, the input impedance increases. In addition, by making the sizes (for example, the gate length and the gate width) of the PMOS transistors Q11 to Q14 that form the above current-convey circuit the same and operating the PMOS transistors Q11 to Q14 in the saturation region, the transistor characteristics can be improved. Can be matched. For this reason,
The drivability of the PMOS transistors Q11 to Q14 can be made the same, and the current conveyor circuit can be effectively operated.

In the case of the above configuration, since the PMOS transistors Q11 and Q13 are connected in series and there is no other device connected to the node N13 to flow current, the PMO
The currents flowing through S transistors Q11 and Q13 are equal. In addition, as described above, the PMOS transistor Q1
Since 1 and Q13 operate in the saturation region, the voltages applied between the source and the gate become equal when equal currents flow. That is, the voltage V1 of the PMOS transistor Q11 and the voltage V3 of the PMOS transistor Q13 become equal.

Further, similarly to the above, the transistor Q12
Since the currents flowing in Q14 and Q14 are also equal, the PMOS
The voltage V2 of the transistor Q12 and the voltage V4 of the PMOS transistor Q14 become equal. As a result, V1
+ V4 = V2 + V3, and the node N11 and the node N1
6 becomes equal to the voltage between the node N12 and the node N17. This indicates that the potential levels of the node N11 and the node N12 of the input circuit IP1 are the same and there is no potential amplitude. As a result, the input circuit IP
1 can receive a signal by not receiving a potential amplitude but a current difference.

Therefore, the input complementary current signal I
The current value flowing to the current conveyor circuit changes due to the current difference between O and / IO, and the potential amplitude appears at the nodes N16 and N17 due to the current flowing into the loads L3 and L4. Complementary voltage signals V whose potential amplitudes are complementary to each other
It is output to the internal circuit IS11 as O and / VO.

By the above operation, complementary current signals IO, /
The change in the current of IO is converted into the change in the voltage of the complementary voltage signals VO and / VO and input to the internal circuit IS11. Therefore, the complementary logic signals DT and / DT which are the data signals output from the internal circuit IS1 are converted into complementary current signals IO and / IO by the output circuit OP1, and the semiconductor device IC11 via the transmission lines T1 and T2 in the current mode. Is input to. The semiconductor device IC11 receives the input complementary current signal I
O, / IO are converted to voltage mode, and complementary voltage signals VO,
/ VO is output to the internal circuit IS11.

Next, the signal waveforms of the input / output interface system shown in FIG. 1 will be described. FIG. 2 is a diagram showing signal waveforms of the input / output interface system shown in FIG. FIG. 2 shows a signal waveform when the power supply voltage VCC is 5V and the termination potential VDT is 2.8V.
The power supply voltage and the termination potential are not limited to this specific example, and may be other voltages. In addition, in FIG.
Complementary logic signals DT and / DT and complementary voltage signal VO,
/ VO indicates the potential of each signal, and the NMOS transistors Q1 and Q2, and the PMOS transistor Q
The current value is shown for each of the signals 11 and Q12.

Referring to FIG. 2, complementary logic signals DT, / D
When T changes, PMOS transistors Q1 and Q2
The current flowing through it changes. This current is input to the input circuit IP1 via the transmission lines T1 and T2, and the currents of the PMOS transistors Q11 and Q12 change. PM
When the currents of OS transistors Q11 and Q12 change, the potentials of complementary voltage signals VO and / VO change. Therefore, complementary voltage signals VO and / VO corresponding to potential changes of complementary logic signals DT and / DT are input to internal circuit IS11. Also, in the above series of processes, the nodes N1, N2, N
The potentials of 11 and N12 are almost constant.

By the above operation, the complementary current signal is transmitted from the semiconductor device IC1 to the semiconductor device IC11 in the current mode, and the potentials of the complementary current signals IO and / IO are constant, so that the board wiring capacitance is charged and discharged. It is possible to transmit signals with low power consumption.

Further, since the input circuit IP1 does not detect a voltage change but a current difference, it is not necessary to make the signal amplitude in the transmission lines T1 and T2. Therefore, the drive capability of the output circuit OP1 can be reduced, and the device size can be reduced. For example, the conventional voltage mode output circuit is about 100 ×
In the case of 200 μm ² , the output circuit of this embodiment has about 10 ×
It can be reduced to 30 μm ^2, and the device area can be reduced by about one digit.

Further, in the present embodiment, the transmission lines T1 and T2 are
The terminating resistor is not connected to the input circuit OP1 side of. The characteristic impedances of the transmission lines T1 and T2 are generally 50Ω, 120Ω, etc., whereas the input impedance of the circuit on the input side is small. Therefore, as described above, by connecting nothing to the input circuit IP1 side and suppressing the input impedance to a low level, the transmission line T1,
A signal will be received via T2. In this state,
The incident voltage does not oscillate, and the current has an amplitude twice the output amplitude of the output circuit OP1.

The reason why the double current difference can be detected without the termination resistor will be described below. Characteristic impedance of the transmission line is Z ₀ , incident wave voltage of the transmission line is e ₁ , current is i ₁ , reflected wave voltage is e ₁ ′, current is i ₁ ′, input impedance of input side is R, input side is R Where e _{2 is} the voltage and i ₂ is the current, then e ₁ + e ₁ ′ = e ₂ = Ri ₂ (1) i ₁ −i ₁ ′ = i ₂ (2) i ₁ = e ₁ / Z ₀ (3) i ₁ ′ = e ₁ ′ / Z ₀ (4) Next, from the equations (1), (3) and (4), e ₁ ′ = {(R−Z ₀ ) / (R + Z ₀ )} e ₁ (5) Next, by substituting the equation (5) into the equation (1), e ₂ = {2R / (R + Z ₀ )} e ₁ (6) Next, from equations (1), (3), and (6), i ₂ = 2i ₁ Z ₀ / (R + Z ₀ ) ... (7) Next, from the expressions (3) to (5), i ₁ ′ = {(R−Z ₀ ) / (R + Z ₀ )} i ₁ (8) When the terminal is short-circuited, the input impedance R becomes 0, and from equations (5) to (8), e ₁ ′ = −e ₁ (9) i ₁ ′ = −i ₁ (10) e ₂ = 0 ... (11) i ₂ = 2i ... (12). Therefore, the current i ₂ on the input side is twice the current i ₁ of the incident wave, and the input circuit IP1 is
It is possible to detect with a current difference of twice the output amplitude of 1, and it is possible to stably detect even a minute signal.

Further, in this embodiment, the output circuit OP1 is connected to the terminating resistors R1 and R2 and is terminated to the terminating potential VTT. The input impedance of the input circuit IP1 is actually not completely 0Ω and has a slightly low resistance value (about several Ω or less), so that a reflected wave is generated although it is slight. Therefore, the reflected voltage and the reflected current are returned via the transmission lines T1 and T2. However, as described above, the transmission lines T1, T
Since the characteristic impedance of 2 and the impedance of the output side are matched, it is possible to prevent the reflected wave from being input to the input circuit IP1 again. Therefore, it becomes possible to transmit a signal at high speed.

Further, by setting the terminating potential VTT to an appropriate potential, the input circuit IP1 can be used in a region where the sensitivity of the input circuit IP1 is high, and even a minute current can be detected stably. Become.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the input / output interface system of the second embodiment of the present invention. The difference between the input / output interface system shown in FIG. 3 and the input / output interface system shown in FIG.
And N12 to which terminating resistors R11 and R12 are added, and other points are the same as those of the input / output interface system shown in FIG. 1, and therefore detailed description thereof will be omitted below.

Referring to FIG. 3, the semiconductor device IC12 is
It further includes termination resistors R11 and R12. Termination resistor R11
Is supplied with the terminal potential VTT at one end thereof and the node N at the other end thereof.
11 is connected. Similarly, the terminating resistor R12 is also the node N1.
Connected with 2. Although the terminating resistors R11 and R12 are arranged inside the semiconductor device IC12 in FIG. 3, they may be arranged inside the input circuit IP1 or the semiconductor device IC12.
May be connected to the outside.

As described above, the terminating resistors R11 and R1
By adding 2, it is possible to match the characteristic impedances of the transmission lines T1 and T2 with the input impedance on the input side, and to eliminate reflection from the input side. Therefore, the signal can be transmitted at a higher speed.

Next, an input / output interface system according to the third embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the input / output interface system of the third embodiment of the present invention. The input / output interface system shown in FIG. 4 differs from the input / output interface system shown in FIG. 3 in that resistors R13 and R14 are added, and other points are the same as those in the input / output interface system shown in FIG. Therefore, detailed description will be omitted below.

Referring to FIG. 4, the semiconductor device IC13 is
The resistors R13 and R14 are further included. The resistor R13 is connected in series between the transmission line T1 and the node N11. The resistor R14 is connected in series between the transmission line T2 and the node N12. The resistors R11 and R12 function as protective resistors on the input side. Therefore, the transmission line T
By matching the characteristic impedance of T1 and T2 with the input impedance on the input side including the impedances of resistors R13 and R14 by terminating resistors R11 and R12, reflection is eliminated even when the input impedance on the input side becomes large. It becomes possible. Therefore, it becomes possible to transmit the signal at a higher speed even when the protective resistor is added.

Next, an input / output interface system according to the fourth embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the input / output interface system of the fourth embodiment of the present invention. The input / output interface system shown in FIG. 5 differs from the input / output interface system shown in FIG. 1 in that the output circuit OP1 is changed to the output circuit OP2, and the other points are the input / output interface system shown in FIG. Since it is the same as, the detailed description will be omitted below.

Referring to FIG. 5, semiconductor device IC2 includes an internal circuit IS1 and an output circuit OP2. Output circuit OP2
Includes NMOS transistors Q3 and Q4. NMOS
The complementary logic signal DT is input from the internal circuit IS1 to the gate of the transistor Q3. NMOS transistor Q
One end of 3 is connected to the transmission line T1, and the other end receives the ground potential. The complementary logic signal / DT is input from the internal circuit IS1 to the gate of the NMOS transistor Q4. NMO
One end of the S transistor Q4 is connected to the transmission line T2,
The other end receives the ground potential.

As described above, the output circuit OP2 is composed of the pull-down NMOS transistors Q3 and Q4. That is, since the output circuit OP2 is composed only of pull-down transistors, the size of the circuit can be made extremely small.

Further, since the output circuit OP2 is composed of only pull-down transistors, the NMOS transistor receiving the high level signal of the complementary logic signals DT and / DT output from the internal circuit IS1 draws out the current. It will be. On the other hand, in the semiconductor device IC11, the difference in current drawn by the pull-down NMOS transistors Q3 and Q4 causes a differential current in the input circuit IP1. Therefore, even in the input / output interface system of this embodiment,
Similar to the first embodiment, no voltage amplitude appears on the transmission lines T1 and T2, and a signal is transmitted by a current difference. As a result,
Even if the board wiring has a large capacity, it is not necessary to charge and discharge the capacity, and thus it is possible to transmit signals at high speed with low power consumption.

Next explained is an input / output interface system according to the fifth embodiment of the invention. FIG. 6 is a block diagram showing the configuration of the input / output interface system of the fifth embodiment of the present invention.

Referring to FIG. 6, the input / output interface system includes semiconductor devices IC3, IC12 and a transmission line T.
1, including T2. The semiconductor device IC3 has an internal circuit IS.
1, including the output circuit OP3. The output circuit OP3 is a PMO
It includes S transistors Q5 and Q6. Semiconductor device IC12
Includes an internal circuit IS11 and an input circuit IP2. The input circuit IP2 includes loads L5 to L8 and an NMOS transistor Q.
15 to Q18 are included.

Internal circuit IS1 outputs complementary logic signals DT and / DT as internal data to output circuit OP3.
The complementary logic signal DT is input to the gate of the PMOS transistor Q5. One end of the PMOS transistor Q5 receives the power supply voltage VCC, and the other end is connected to the transmission line T1. The complementary logic signal / DT is input to the gate of the PMOS transistor Q6. The power supply voltage VCC is supplied to one end of the PMOS transistor Q6, and the other end of the transmission line T
Connected with 2.

The ground potential is supplied to one end of the load L7,
The other end has a transmission line T1 and an NMOS transistor Q1.
5 is connected to one end. The other end of the NMOS transistor Q15 is connected to one end of the NMOS transistor Q17. The power supply voltage VCC is supplied to the gate of the NMOS transistor Q17 via the node N25. NMOS
The other end of the transistor Q17 is connected to one end of the load L5 and the internal circuit IS11. The power supply voltage VCC is supplied to the other end of the load L5. The ground potential is supplied to one end of the load L8, and the other end is connected to the transmission line T2 and the NMOS transistor Q16. NMOS transistor Q1
The gate of 6 has NMOS transistors Q15 and Q1
7 is connected to the node N23, which is a connection point of No.7. NMOS
The other end of the transistor Q16 has an NMOS transistor Q1.
8 is connected to one end. A node N24, which is a connection point between the NMOS transistors Q16 and Q18, is connected to the gate of the NMOS transistor Q15. The gate of NMOS transistor Q18 receives power supply voltage VCC via node N25. The other end of the NMOS transistor Q18 is connected to one end of the load L6 and the internal circuit IS11. The power supply voltage VCC is supplied to the other end of the load L6.

As described above, the input / output interface system shown in FIG. 6 is basically the same as the input / output interface system shown in FIG. 5, but the polarities and connections of the respective devices are reversed. That is, the output circuit OP3
Is composed of PMOS transistors Q5 and Q6 for pull-up, and the circuit size of the output circuit OP3 can be reduced similarly to the output circuit OP2. Further, since the output circuit OP3 is composed only of pull-up transistors, the current may be drawn out by the PMOS transistor receiving the low level signal of the complementary logic signals DT and / DT output from the internal circuit IS1. Become. The input circuit IP2 receives the current difference drawn by the pull-up PMOS transistors Q5 and Q6, and a differential current is generated in the input circuit IP2. As a result, in this embodiment as well, as in the above-described embodiments, no voltage amplitude appears on the transmission lines T1 and T2, and a signal is transmitted by a current difference. Therefore, even if the board wiring has a large capacitance, the capacitance is not charged or discharged, and thus it is possible to transmit a signal at high speed with low power consumption.

Next explained is an input / output interface system according to the sixth embodiment of the invention. FIG. 7 is a block diagram showing the configuration of the input / output interface system of the sixth embodiment of the present invention.

Referring to FIG. 7, the input / output interface system includes semiconductor devices IC4, IC14 and a transmission line T1.
including. A signal is transmitted from the semiconductor device IC4 to the IC14 in the current mode via the transmission line T1. That is, although the above embodiments have shown the examples of the differential mode output, the following embodiments show the examples of the single mode output.

The semiconductor device IC4 includes an internal circuit IS2 and an output circuit OP4. The output circuit OP4 includes an NMOS transistor Q7. The internal circuit IS2 outputs the logic signal DT which is internal data to the output circuit OP4. NMO
The logic signal DT is input to the gate of the S transistor Q7. The ground potential is supplied to one end of the NMOS transistor Q7, and the other end is connected to the transmission line T1. Therefore, since the output circuit OP4 is composed of only the pull-down NMOS transistor Q7, the NMOS transistor Q7 strongly draws the current when the logic signal DT is at the high level.

The semiconductor device IC14 has an internal circuit IS1.
2. Including an input circuit IP3. The input circuit IP3 has a load L
11, NMOS transistor Q21, comparator CP
Including 1. The power supply voltage VCC is supplied to one end of the load L11, and the other end has an internal circuit and an NMOS transistor Q.
21 is connected to one end. NMOS transistor Q21
The other end of is connected to the transmission line T1 and the negative side input terminal of the comparator CP1. The reference potential Vref is input to the positive input terminal of the comparator CP1. NMOS
The gate of the transistor Q21 has a comparator CP1
The output of is input.

With the above configuration, the comparator CP1
Compares the reference potential Vref with the potential of the node N31 to control the gate potential of the NMOS transistor Q21. As a result, when the pull-down current of the node N31 is large, the current driving capability of the NMOS transistor Q21 is increased and the potential drop of the node N31 is suppressed. vice versa,
When the pull-down current is small, the current driving capability of the NMOS transistor Q21 is suppressed and the potential drop of the node N31 is maintained. As a result, due to the pull-down current flowing through the NMOS transistor Q21 of the input circuit IP3, a current flows through the load L11 and an output potential appears at the node N32. Therefore, voltage signal VO is output from node N32 to internal circuit IS12.

With the above operation, when the logic signal DT is at the high level, the NMOS transistor Q7 strongly draws the current, so that the input circuit IP3 detects the data at the low level. At this time, no voltage amplitude appears on the transmission line T2, and the current signal IO is transmitted due to a change in current.

Next, the signal waveforms of the input / output interface system shown in FIG. 7 will be described. FIG. 8 is a diagram showing signal waveforms of the input / output interface system shown in FIG. FIG. 8 shows, as an example, the case where the power supply voltage VCC is 5V. The power supply voltage VCC is not limited to this value and may be another value. In FIG. 8, the potentials of the logic signal DT and the voltage signal VO are shown, and the current values of the signals flowing through the NMOS transistors Q7 and Q21 are shown.

First, when the potential of the logic signal DT rises,
The current flowing through the NMOS transistor Q7 increases. Next, as the current flowing through the NMOS transistor Q7 increases, the current flowing through the NMOS transistor Q21 increases. In response to this, the potential of the voltage signal VO drops. By the above process, the voltage change of the logic signal DT is converted into the current change and transmitted, and finally output as the voltage change of the voltage signal VO. In the above series of processes, the node N
The potentials of 7 and N31 are almost constant.

As described above, the voltage amplitude does not appear on the transmission line T1, and the signal is transmitted by the change in current. Therefore,
Even if the board wiring has a large capacity, the capacity is not charged or discharged, so that it is possible to transmit a signal at high speed with low power consumption. Moreover, since one signal can be transmitted by one transmission line, a small area and a small space of the system can be realized.

Next explained is an input / output interface system according to the seventh embodiment of the invention. FIG. 9 is a block diagram showing the configuration of the input / output interface system of the seventh embodiment of the present invention. The input / output interface system shown in FIG. 9 differs from the input / output interface system shown in FIG. 7 in that the input circuit IP3 is changed to the input circuit IP4, and the other points are the input / output interface system shown in FIG. Since it is the same as, the detailed description will be omitted below.

Referring to FIG. 9, the input circuit IP4 includes a comparator CP2, PMOS transistors Q22 and Q2.
3, including load L12. The reference potential Vref is input to the negative side input terminal of the comparator CP2. The positive input terminal of the comparator CP2 is connected to the transmission line T1 and one end of the PMOS transistor Q22 via the node N35. The power supply voltage VCC is supplied to the other end of the PMOS transistor Q22. NMOS transistor Q2
The output signal of the comparator CP2 is input to the gates of 2 and Q23. The power supply voltage VCC is supplied to one end of the PMOS transistor Q22. The other end of the PMOS transistor Q23 has a load L via a node N36.
12 and one end of the internal circuit IS12. The ground potential is supplied to the other end of the load L12.

With the above configuration, the comparator CP2
Compares the reference potential Vref with the potential of the node N35 and controls the gate potentials of the PMOS transistors Q22 and Q23. Therefore, when the pull-down current of the node N35 is large, the PMOS transistor Q22
The current drivability of is increased to suppress the potential drop of the node N35. Conversely, if the pull-down current is small, PM
The current drivability of the OS transistor Q22 is suppressed to keep the potential drop of the node N35. Therefore, the input circuit IP4
By controlling the gate potential of the PMOS transistor Q23 by the output potential of the comparator CP2, a current flows through the load L12 and the output potential appears at the node N36. As a result, the voltage signal VO is output from the node N36 to the internal circuit IS12.

With the above operation, when the logic signal DT is at the high level, the transistor Q7 strongly pulls the current, and the input circuit IP4 detects the data at the low level. Therefore, also in this embodiment, on the transmission line T1,
The voltage amplitude does not appear, and the signal is transmitted by the change in current. As a result, even if the board wiring has a large capacitance, the capacitance is not charged or discharged, and it is possible to transmit a signal at high speed with low power consumption.

Next explained is an input / output interface system according to the eighth embodiment of the invention. FIG. 10 is a block diagram showing the configuration of the input / output interface system of the eighth embodiment of the present invention. The input / output interface system shown in FIG. 10 differs from the input / output interface system shown in FIG. 7 in that the input circuit IP3 is the input circuit IP3.
5 and the other points are the same as those of the input / output interface system shown in FIG. 7, and therefore detailed description thereof will be omitted below.

Referring to FIG. 10, input circuit IP5 has P
It includes MOS transistors Q31 to Q33, NMOS transistors Q34 and Q35, and a load L13. One end of the PMOS transistor Q34 is connected to the transmission line T1 via the node N41. The other end of the NMOS transistor Q34 is connected to one end of the PMOS transistor Q31.
The power supply voltage VCC is applied to the other end of the PMOS transistor Q31.
Is supplied. NMOS transistor Q34 and PMOS
The node N42, which is a connection point with the transistor Q31, is
It is connected to the gates of PMOS transistors Q31 and Q32. The power supply voltage VCC is supplied to one end of the PMOS transistor Q32. PMOS transistor Q3
The other end of 2 is connected to one end of an NMOS transistor Q35. The reference potential Vref is supplied to the other end of the NMOS transistor Q35. PMOS transistor Q32
A node N43, which is a connection point between the NMOS transistor Q35 and the NMOS transistor Q35, is connected to each gate of the NMOS transistors Q34 and Q35.

The gate of the PMOS transistor Q33 is
It is connected to the gate of PMOS transistor Q32. P
The power supply voltage VCC is supplied to one end of the MOS transistor Q33. The other end of the PMOS transistor Q33 is connected to one end of the load L13 and the internal circuit I via the node N44.
It is connected to C12. The ground potential is supplied to the other end of the load L13.

With the above configuration, in the input circuit IP5,
The reference potential Vref and the potential of the node N41 are compared,
The gate potential of the PMOS transistor Q32 is controlled according to the comparison result. Therefore, when the pull-down current of node N41 is large, the potential of node N42 drops, the current driving capability of PMOS transistor Q32 increases, and the potential of node N43 rises. As a result, NM
The current drivability of the OS transistor Q34 is increased and the potential of the node N41 is increased. Therefore,
The potential amplitude of the node N41 disappears, but the current amplitude exists.

On the contrary, when the pull-down current is small,
The current driving capability of the PMOS transistor Q32 is suppressed,
The potential of the node N43 drops. As a result, NMOS
The current driving capability of the transistor Q34 is suppressed, and the node N
The potential of 41 drops. Therefore, the gate potential of the PMOS transistor Q33 is controlled by the potential of the node N42, and the current flows through the load L13, so that the output potential appears at the node N44. As a result, the voltage signal VO is output from the node N44 to the internal circuit IC12.

With the above operation, when the logic signal DT is at the high level, the pull-down NMOS transistor Q7
Strongly draws a current, and the input circuit IP5 detects low level data. Therefore, also in this embodiment, the voltage amplitude does not appear on the transmission line T1, and the signal is transmitted by the current change. As a result, even if the board wiring has a large capacitance, the capacitance is not charged or discharged, and it is possible to transmit a signal at high speed with low power consumption.

Next explained is an input / output interface system according to the ninth embodiment of the invention. FIG. 11 is a block diagram showing the configuration of the input / output interface system of the ninth embodiment of the present invention.

Referring to FIG. 11, the input / output interface system includes semiconductor devices IC5, IC17 and a transmission line T.
Including 1. The semiconductor device IC5 includes an internal circuit IS2 and an output circuit OP5. The output circuit OP5 includes a PMOS transistor Q8. The internal circuit IS2 outputs the logic signal DT which is internal data to the output circuit OP5. PMOS
The logic signal DT is input to the gate of the transistor Q8. The power supply voltage V is applied to one end of the PMOS transistor Q8.
CC is supplied to the other end of the transmission line T via the node N8.
1 is connected.

As described above, since the output circuit OP5 is composed of the pull-up PMOS transistor Q8, the circuit size of the output circuit OP5 can be reduced. Further, the output circuit OP5 has a P for pull-up.
Since it is composed of the MOS transistor Q8, when the logic signal DT is at the low level, the PMOS transistor Q8
However, the current is strongly drawn.

The semiconductor device IC17 has an internal circuit IC1.
2. Including the input circuit IP6. The input circuit IP6 is a PMO
It includes S transistors Q23 and Q24, NMOS transistors Q25 to Q27, and a load L14.

One end of the PMOS transistor Q23 is connected to the transmission line T1 via the node N51. PMOS
The other end of the transistor Q23 is connected to NM via the node N52.
It is connected to one end of the OS transistor Q25. NMOS
The ground potential is supplied to the other end of the transistor Q25.
The reference potential Vref is supplied to one end of the resistor R21.
The other end of the resistor R21 is connected to the gate of the PMOS transistor Q23 and one end of the PMOS transistor Q24 via the node N53. PMOS transistor Q2
The gate of 4 is connected to the node N52. The other end of the PMOS transistor Q24 is connected to the N node via the node N54.
Connected to the gates of MOS transistors Q25 and Q26, and one end of PMOS transistor Q26.
The ground potential is supplied to the other end of the NMOS transistor Q26. The power supply voltage VCC is supplied to one end of the load L14. The other end of the load L14 passes through the node N55 and N
One end of MOS transistor Q27 and internal circuit IC1
Connected with 2. The gate of NMOS transistor Q27 is connected to the gates of NMOS transistors Q25 and Q26. The ground potential is supplied to the other end of the NMOS transistor Q27.

With the above structure, internal circuit IP6 compares reference potential Vref with the potential of node N51, and the gate potential of PMOS transistor Q23 is controlled according to the result of the comparison. Therefore, when the pull-up current of the node N51 is large, the PMOS transistor Q2
The current drivability of No. 3 is increased and the potential of the node N52 is increased. As a result, the current drivability of the PMOS transistor Q24 is lowered and the potential of the node N54 is lowered. Therefore, the current flowing through the PMOS transistor Q23 and the NMOS transistor Q25 is reduced, and the rise in the potential of the node N51 is suppressed. As a result, the potential amplitude at the node N51 disappears, but the current amplitude exists.

On the contrary, when the pull-up current is small,
The current driving capability of the PMOS transistor Q23 is suppressed,
The potential of the node N51 drops. Therefore, the PMOS
The current driving capability of the transistor Q24 increases, and the node N5
The potential of 4 will rise. By the above operation, the potential of the node N54 causes the NMOS transistor Q27
The gate potential is controlled, and the current flows through the load L14, whereby the output potential appears at the node N55. Therefore, the voltage signal VO is output from the node N55 to the internal circuit IC12.
Output to

With the above operation, when the logic signal DT is at the low level, the PMOS transistor Q8 strongly draws the current, and the input circuit IP6 detects the high level data. Therefore, also in this embodiment, the voltage amplitude does not appear on the transmission line T1, and the signal is transmitted by the current change. As a result, even if the board wiring has a large capacity, the capacity is not charged or discharged, so that a signal can be transmitted at high speed with low power consumption.

[0107]

In the output circuit according to any one of claims 1 to 5, the first circuit according to the first and second complementary logic signals is provided.
Since the second complementary current signal can be output to the outside in the current mode, the signal can be transmitted at high speed with low power consumption.

In the input circuit according to any one of claims 6 to 10, the first and second complementary current signals transmitted in the current mode are converted into the first and second complementary current signals and internally output in the voltage mode. Therefore, it becomes possible to transmit signals at high speed with low power consumption.

In the input circuit according to any one of claims 11 to 15, the potential of the current signal transmitted in the current mode is compared with a predetermined reference potential, and the voltage signal is internally fed in the voltage mode in accordance with the comparison result. Since it can be output, a signal can be transmitted at high speed with low power consumption.

In the input / output interface system according to the sixteenth and seventeenth aspects, the first mode in the current mode is used.
Since the second complementary current signal can be transmitted from the output semiconductor device to the input semiconductor device, the signal can be transmitted at high speed with low power consumption.

In the input / output interface system according to the eighteenth aspect, since the current signal can be transmitted from the semiconductor device to the input semiconductor device in the current mode, the signal can be transmitted at high speed with low power consumption. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an input / output interface system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms of the input / output interface system shown in FIG.

FIG. 3 is a block diagram showing a configuration of an input / output interface system according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an input / output interface system according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an input / output interface system according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an input / output interface system according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an input / output interface system according to a sixth embodiment of the present invention.

8 is a diagram showing signal waveforms of the input / output interface system shown in FIG.

FIG. 9 is a block diagram showing the configuration of an input / output interface system according to a seventh embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of an input / output interface system according to an eighth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of an input / output interface system according to a ninth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of an input / output interface system using a conventional push-pull type output circuit.

FIG. 13 is a block diagram showing a configuration of an input / output interface system using a conventional open drain type output circuit.

FIG. 14 is a block diagram showing a configuration of a conventional TDL standard input / output interface system.

FIG. 15 is a block diagram showing a configuration of a conventional CTT standard input / output interface system.

[Explanation of symbols]

IC1 semiconductor device, IC11 semiconductor device, IS1
Internal circuit, OP1 output circuit, T1 transmission line, T2 transmission line, IS11 internal circuit, IP1 input circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H03K 19/0944 H03K 19/092 19/094 A

Claims (18)

[Claims] 1. An output circuit for transmitting complementary first and second complementary current signals to the outside in a current mode through a transmission line, the input circuit receiving complementary first and second complementary logic signals. And an output circuit for outputting the first and second complementary current signals to the outside in the current mode according to the potentials of the first and second complementary logic signals input to the input terminal. 2. The output circuit according to claim 1, further comprising resistance means connected to a terminal of the output means and receiving a predetermined terminal potential. 3. The resistance means includes first and second resistors for receiving the terminal potential at one end thereof, and the output means has a current source and a gate for receiving the first complementary logic signal, one end of which is A first NMOS transistor connected to the first resistor and the other end connected to the current source; and a gate receiving the second complementary logic signal, one end connected to the second resistor and the other end connected to the second resistor. The output circuit according to claim 2, further comprising a second NMOS transistor connected to the current source. 4. The output means includes a gate for receiving the first complementary logic signal, a first pull-down NMOS transistor for receiving a ground potential at one end, and a gate for receiving the second complementary logic signal, The output circuit according to claim 1, further comprising a second pull-down NMOS transistor receiving at one end the ground potential. 5. The output means has a gate that receives the first complementary logic signal, a first pull-up PMOS transistor that receives a power supply voltage at one end, and a gate that receives the second complementary logic signal. 2. The output circuit according to claim 1, further comprising a second pull-up PMOS transistor which receives the power supply voltage at one end thereof. 6. An input circuit for receiving complementary first and second complementary current signals transmitted from the outside in a current mode through a transmission line, the input circuit receiving the first and second complementary current signals. And converting a current change of the first and second complementary current signals input to the input terminal into a voltage change, the first and second
An input circuit including converting means for internally outputting first and second complementary voltage signals complementary to each other according to the current of the complementary current signal in a voltage mode. 7. The input circuit according to claim 6, wherein the conversion means includes a current conversion circuit that differentially converts the currents of the first and second complementary current signals and converts a current change into a voltage change. 8. The current-conveying circuit includes: a first load that receives the first complementary current signal at one end and a power supply voltage at the other end; and a first PMOS transistor having one end connected to one end of the first load. A second PMOS transistor having one end connected to the other end of the first PMOS transistor and having a gate for receiving the ground potential; one end connected to the other end of the second PMOS transistor for receiving the ground potential at the other end; A load, a third load receiving at one end the second complementary current signal and receiving the power supply voltage at the other end, one end connected to one end of the first load, and the other end of the first load
A third PMOS transistor having a gate connected to the gate of the PMOS transistor and receiving a potential at a connection point of the first and second PMOS transistors; one end connected to the other end of the third PMOS transistor and the gate of the first PMOS transistor; A fourth PMOS transistor having a gate for receiving the ground potential; and a fourth load having one end connected to the other end of the fourth PMOS transistor and receiving the ground potential at the other end, the second PMOS transistor and the second load The input circuit according to claim 7, wherein the first complementary voltage signal is output from a connection point between the second complementary voltage signal and the fourth PMOS transistor, and the second complementary voltage signal is output from a connection point between the fourth PMOS transistor and the fourth load. 9. The current-convey circuit includes: a first load that receives the first complementary current signal at one end and a ground potential at the other end; and a first NMOS transistor whose one end is connected to one end of the first load. A second NMOS transistor having one end connected to the other end of the first NMOS transistor and having a gate receiving a power supply voltage; one end connected to the other end of the second NMOS transistor and a second end receiving the power supply voltage A load, a third load receiving at one end the second complementary current signal and receiving the ground potential at the other end, one end connected to one end of the first load, and the other end of the first load
A third NMOS transistor having a gate connected to the gate of the NMOS transistor and receiving a potential at a connection point of the first and second NMOS transistors; one end connected to the other end of the third NMOS transistor and the gate of the first NMOS transistor; A fourth NMOS transistor having a gate for receiving the power supply voltage; and a fourth load having one end connected to the other end of the fourth NMOS transistor and receiving the power supply voltage at the other end, the second NMOS transistor and the second load 8. The input circuit according to claim 7, wherein the first complementary voltage signal is output from a connection point between the second complementary voltage signal and the fourth NMOS transistor, and the second complementary voltage signal is output from a connection point between the fourth NMOS transistor and the fourth load. 10. The input terminal includes a first input terminal for receiving the first complementary voltage signal and a second input terminal for receiving the second complementary voltage signal, wherein the input circuit has one end having the first A first terminating resistor connected to the input end and receiving a predetermined terminating potential at the other end, and a second terminating resistor having one end connected to the second input end and receiving the terminating potential at the other end. 6. The input circuit according to item 6. 11. An input circuit for receiving a current signal transmitted in a current mode from the outside via a transmission path, comprising: a comparing means for comparing a potential of the current signal with a predetermined reference potential; An input circuit including an output unit that internally outputs a voltage signal corresponding to a current of the current signal in a voltage mode according to a comparison result. 12. The comparison means includes a comparator that receives the current signal at a negative side input terminal and receives the reference voltage at a positive side input terminal, and the output means has a gate that receives an output signal of the comparator. And an NMOS transistor having one end receiving the current signal, and a load having one end connected to the other end of the NMOS transistor and receiving a power supply voltage at the other end, the voltage from a connection point of the NMOS transistor and the load. The input circuit according to claim 11, wherein a signal is output. 13. The comparison means includes a comparator that receives the current signal at a positive side input terminal and receives the reference potential at a negative side input terminal, and the output means has a gate that receives an output signal of the comparator. And receiving the current signal at one end and the power supply voltage at the other end
A second PMOS transistor having a PMOS transistor, a gate receiving the output signal of the comparator, receiving the power supply voltage at one end, a load having one end connected to the other end of the second PMOS transistor and receiving the ground potential at the other end 12. The input circuit according to claim 11, wherein the voltage signal is output from a connection point between the second PMOS transistor and the load. 14. The comparing means includes: a first NMOS transistor having one end for receiving the current signal; a first PMOS transistor having one end and a gate connected to the other end of the first NMOS transistor and the other end for receiving a power supply voltage; A second NM having the other end and the gate connected to the gate of the first NMOS transistor.
An OS transistor, one end of which is connected to the other end and the gate of the second NMOS transistor, the other end of which receives the power supply voltage, and the first P
A first PMOS transistor having a gate connected to a connection point between the first NMOS transistor and the first PMOS transistor and a gate of the MOS transistor; and the output means has a gate connected to the gate of the second PMOS transistor. And a third PMOS that receives the power supply voltage at one end
12. A transistor and a load including one end connected to the other end of the third PMOS transistor and receiving the ground potential at the other end, wherein the voltage signal is output from a connection point between the third PMOS transistor and the load. Input circuit described. 15. The comparing means comprises: a first PMOS transistor having one end for receiving the current signal; a first NMOS transistor having one end connected to the other end of the first PMOS transistor and receiving a ground potential at the other end; A resistor connected to the gate of the first PMOS transistor, the other end receiving the reference potential, one end connected to one end of the resistor and the gate of the first PMOS transistor, and a connection point between the first PMOS transistor and the first NMOS transistor A second PMOS transistor having a gate connected to, and one end connected to the other end of the second PMOS transistor, the other end receiving the ground potential, and the other end of the second PMOS transistor and the gate of the first NMOS transistor Second NMOS having a controlled gate And a third NMOS transistor having a gate connected to the gate of the second NMOS transistor, the other end having a third NMOS transistor receiving the ground potential, and one end connected to the other end of the third NMOS transistor, The input circuit according to claim 11, further comprising a load receiving a power supply voltage at the other end, wherein the voltage signal is output from a connection point between the third NMOS transistor and the load. 16. An input / output interface system for transmitting, in a current mode, first and second complementary current signals complementary to each other in a current mode from a semiconductor device for output to a semiconductor device for input through a transmission line, wherein the output The semiconductor device for input includes an output circuit for outputting the first and second complementary current signals to the transmission line in a power supply mode, and the semiconductor device for input includes the first and second input circuits input through the transmission line. An input circuit is provided which converts a current change of the complementary current signal into a voltage change and internally outputs in a voltage mode complementary first and second complementary voltage signals corresponding to the currents of the first and second complementary current signals. I / O interface system. 17. The input semiconductor device is connected to a first input terminal for receiving the first complementary voltage signal, a second input terminal for receiving the second complementary current signal, and the first input terminal, and the like. 17. The input / output interface system according to claim 16, further comprising a first terminating resistor having an end receiving a predetermined terminating potential, and a second terminating resistor connected to the second input end and having the other end receiving the terminating potential. 18. An input / output interface system for transmitting a current signal in a current mode from an output semiconductor device to an input semiconductor device via a transmission path, wherein the output semiconductor device comprises a MOS transistor, An output circuit that outputs a current signal to the transmission line in a current mode is included, the input semiconductor device converts a current change of the current signal input via the transmission line into a voltage change, and the complementary current signal An input / output interface system including an input circuit that internally outputs a voltage signal according to a current in a voltage mode.