JPH08161277A - Parallel computer system - Google Patents

Abstract

PURPOSE: To improve the network connecting plural processors and performing an inter-processor data transfer, in a parallel computer system. CONSTITUTION: Each of plural processors 201 and 202 is provided with transmission circuit and reception circuit. A service processor 101 outputs a transmission permission signal and a reception permission signal to the transmission circuit and the reception circuit, respectively, outputs the network validating signal corresponding to each network to the both of the circuits and enables the inter- processor data transfer by the both networks. When a fault occurs in one network, the network validating signal of a faulty network is turned off, the transmission and reception permission signals are turned on and the inter-processor data transfer by other network is enabled, after the transmission and permission signals are turned off, the data transmission and reception are suppressed and all the data on the network is destroyed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer system for transferring data between processors through a network connecting a plurality of processors, and particularly to a network for transferring data between processors in which a failure such as unavailability of operation occurs. The present invention relates to a parallel computer system capable of continuing a network function by a failure recovery process at the time of an emergency.

[0002]

2. Description of the Related Art In a conventional parallel computer system for transferring data between processors by a network connecting a plurality of processors, as a method for improving fault tolerance and reliability of a network for realizing a data transfer function between processors, There is a method of making a part of the network redundant, for example, an interface part between each processor and the network, and switching the working part to a spare part when the working part cannot continue operation. As another method, in a network that performs inter-processor data transfer, when operation cannot be continued partially, the part is logically separated and the remaining part is in charge of the inter-processor data transfer function. is there. As an example of the conventional technique for improving the fault tolerance and reliability of the network for performing data transfer between processors as described above, Yoshihiro Toma's "Fault Tolerant System Theory" (published by the Institute of Electronics, Information and Communication Engineers) The methods described on pages 267 to 270 can be mentioned.

[0003]

The first method described in the prior art is to make a part of a network for data transfer between processors redundant so that the current part cannot continue operation. With the method of switching to the spare part, it is possible to deal with failures and failures that occur in the redundant part, but it is impossible to deal with failures and failures in other parts that are not redundant, and the network fault tolerance The reliability range is also limited. Further, in the second method described in the prior art, in a network for performing inter-processor data transfer, a method of logically separating a part where operation cannot be continued and performing a inter-processor data transfer function in the remaining part Then, the inter-processor data transfer function realized by the network after the occurrence of the failure is deteriorated in performance as compared with that before the occurrence of the network failure. An object of the present invention is to provide a data transfer function between processors on a parallel computer system,
A failure recovery process when a failure occurs in the network that transfers data between processors, such as inability to continue operation, allows the network function to continue, thereby improving the fault tolerance of the network and the reliability of the system. Another object of the present invention is, in a parallel computer system in which a plurality of processors are connected to each other in a network to transfer data between processors, and when the inter-processor data transfer function of the network cannot be continued, a receiver processor is provided on the network. The purpose is to discard all the data that has not arrived yet and remove the remaining data on the network so that the inter-processor data transfer function of the network can be continued.

[0004]

In order to solve the above problems, the present invention provides a parallel computer system including a plurality of processors, a network for performing data transfer between processors, and a service processor, wherein the network is duplicated. Each of the processors includes a transmission circuit that selects a network to transmit data and a reception circuit that selects a network to receive data, and the service processor receives a transmission permission signal from the transmission circuit to the reception circuit. A permission signal is output to the transmission circuit and the reception circuit as a network validation signal corresponding to each network to enable data transfer between the processors by both networks, and when the fault occurrence notification signal is received from one network, the transmission permission is given. Turn off the signal and the reception enable signal to transmit data and Communication is suppressed and all data on the network is discarded, then the network enable signal corresponding to the one network is turned off, the transmission permission signal and the reception permission signal are turned on, and the interprocessor data by the other network is turned on. It is designed to allow transfers. Further, in a parallel computer system including a plurality of processors, a network for performing data transfer between processors, and a service processor, and the network is a parallel computer system including an active network and a backup network, each processor selects a network and transmits data. A service circuit and a receiving circuit for receiving data by selecting a network are provided, and the service processor transmits a transmission permission signal to the transmission circuit, a reception permission signal to the reception circuit, and supports the transmission circuit and the reception circuit for each network. Outputs the network enable signal of, and turns on the network enable signal for the active network when using the active network, and turns off the network enable signal for the spare network to enable data transfer between processors by the active network. , When receiving the fault occurrence notification signal from the current network, to suppress the transmission and reception of data by turning off the receive enable signal and the transmission permission signal,
After discarding all the data on the working network, the network enabling signal for the working network is turned off, and the transmission permission signal, the reception permission signal, and the network enabling signal for the protection network are turned on, and the protection network is turned on. It enables data transfer between processors.

[0005]

In the parallel computer system, when the network for data transfer between processors is duplicated and both networks are operating, if the inter-processor data transfer function of one network cannot continue,
Interprocessor data transfer function after stopping the operation of the transmission circuit and reception circuit for each processor's network and discarding the unreachable data on the network, such as packet data, at the data reception unit for each processor's network Operation is restarted on the other normal network. Also, in a parallel computer system, if a working network and a spare network for performing data transfer between processors are provided and the data transfer function between processors of the working network cannot be continued while operating the working network, each processor Operation of the inter-processor data transfer function after stopping the operation of the transmission circuit and the reception circuit for the network and discarding the data that has not arrived on the network, such as packet data, at the data reception unit for the network of each processor. Restart with the backup network. As a result, it becomes possible to continue the network function after removing the influence of the failure that has occurred in the network.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the parallel computer system according to the present invention will be described. FIG. 1 shows a parallel computer system according to the present invention, which shows a configuration of a parallel computer system in which a plurality of processors are connected and a network for performing data transfer between the processors is duplicated. In FIG. 1, 20
Reference numerals 1 and 202 denote two PUs (1) and PU (n) out of n processors that constitute a parallel computer system, and each include a CPU and a memory. 501,
Reference numeral 502 represents networks NW (1) and NW (2) that perform data transfer between processors. Each of the networks 501 and 502 includes a transfer data receiving destination changeover switch, a network failure detection circuit, and the like. 10
1 is a service processor SVP, which is a processor for starting up a parallel computer system, setting and managing configuration information, analyzing and recovering from failures, managing system operation status, and supporting maintenance. Prepare a stand. Reference numeral 71 is a processor control signal by the service processor, and 72 is also a network control signal by the service processor. Reference numerals 91, 92, 93 and 94 denote inter-processor data transfer signals, which are a part of the network configuration of the parallel computer system. , 202 are data transfer signals between the processors 201, ..., 202 and the network 501, and 92, 94 are data transfer signals between the processors 201, ..., 202 and the network 502. As shown in FIG. 1, the present invention adopts a system in which a network for realizing a data transfer function between processors is duplicated.

In FIG. 2, reference numerals 201 and 202 denote two PU (1) and PU (n) of n processors constituting a parallel computer system, respectively.
01 and a memory 302. 501 and 502 are network NWs that perform data transfer between processors
(1) and NW (2) are represented, and 501 and 502 are operated as the first network NW (1) and the second network NW (2), respectively. First network 50
The first and second networks 502 respectively include transfer data receiving destination changeover switches 603, 604, 605, 606 and network failure detection circuits 601 and 602. A service processor SVP 101 is a processor for starting the parallel computer system, setting and managing configuration information, analyzing and recovering from failures, managing system operation status, and supporting maintenance. Prepare a stand.

In each processor, the CPU 301 executes programs such as arithmetic processing, and the memory 302 is the CPU 30.
1 stores programs and data required for the operation of 1. Reference numerals 303 and 304 denote data buffers for transferring data between processors via a network.
Reference numeral 03 represents a transmission buffer, and 304 represents a reception buffer. Reference numerals 305, 401, 403, and 404 constitute a transmission circuit that selects a network and transmits data.
06, 402, 405, and 406 constitute a receiving circuit that selects a network and receives data. 305, 30
6 determines whether to use the first network 501 or the second network 502 when transferring data between each processor and the first network 501 and the second network 502, and executes data transmission / reception to / from the network. Is an arbitration circuit for data transmission / reception. An arbitration circuit 305 for data transmission uses which of the first network 501 and the second network 502 to transmit the packet data when each processor transmits the packet data to the first network 501 or the second network 502. It is a circuit that determines whether or not and executes packet data transmission to the network. For example, if both networks are normal, this decision is made to select both networks alternately. Further, 306 is an arbitration circuit for data reception, and when the packet data transferred from the first network 501 or the second network 502 is received by each processor, the packet data received from the first network 501 or the second network 502 is It is a circuit for processing in the receiving processor without conflict. When reception from both networks overlaps, for example, both networks are alternately selected, packet data of one network is sent to the gate 402, and packet data of the other network is buffered in the data reception arbitration circuit 306. It is temporarily stored in. This packet data transmission / reception arbitration circuit 30
The first network activation signal 701 and the second network activation signal 702 from the service processor 101 are also input to 5, 306.
The availability of each of 1 and 502 is constantly monitored, and the result is used as a reference for arbitration work at the time of transmitting and receiving packet data.

In the inter-processor data transfer via both the first network 501 and the second network 502 which are operated when the system is started up, the packet data transmitted from the transmission buffer 303 on the processor is attached to it. Corresponding to the destination processor number, transfer data destination changeover switches 603, 6 in the first network 501 or the second network
It is transferred to the destination processor via 04, 605, and 606. When each packet data passes through the transfer data receiving destination changeover switches 603, 604, 605, 606, the switch is switched according to the receiving destination processor number attached to each packet data, and the packet data is sent to the receiving destination processor. To transfer.

Next, the operation of the parallel computer system according to this embodiment will be described. When the system is operating, system operation is managed by the service processor 101, and mutual data transfer between the n processors 201, ..., 202 is enabled by the service processor 101. The first network 5
01 and the second network 502. From the service processor 101, a transmission permission signal 703 for permitting transmission of packet data, a reception permission signal 704 for permitting reception of packet data, a first network validation signal 701, and a second network validation signal 7
02 is output, and each output has a logical value of 1 in the valid state. The packet data output from the data buffer 303 is logically ANDed with the transmission permission signal 703 by the AND circuit 303, and the data transmission arbitration circuit 305.
Output 804, and the data transmission arbitration circuit 305 arbitrates which network to transmit to, and outputs the data transmission signal 805 or 806. Data transmission to the first network is performed by the first network enable signal 701 from the service processor 101 and each processor 2
.., 202 are ANDed with the data transmission signal 805 by the AND circuit 403, and data transmission to the second network is performed by the second network activation signal 702 from the service processor 101 and each processor 201. , 202 by AND with the data transmission signal 806 by the AND circuit 404. When the system is started up, the service processor 101 recognizes that both networks of the duplicated networks 501 and 502 are valid, and the first network validation signal 701 and the second network validation that are distributed to the respective processors 201, ..., 202. This is dealt with by setting the signal 702 to a logical value of 1, and the logical product of this signal and the data transmission signals 805 and 806 in each of the processors 201, ...
Data transmission to the first network 501 and the second network 502 is realized by the D circuits 403 and 404.

Similarly, AND circuits 405 and 406 take the logical product of the first network enabling signal 701 and the second network enabling signal 702 and the data reception signals 903 and 904 to the processors 201 ,. , And the resulting data received signals 808 and 80
Arbitration is performed by the data reception arbitration circuit 306 so that the content of 9 does not cause a conflict, whereby data reception from the first network 501 and the second network 502 to each processor is realized. In addition, the network 501,
When receiving packet data from 502, the packet data arriving from the first network 501 and the second network 502 is the first network enable signal 701 and the second network enable signal 7 from the service processor 101.
Depending on the logical value of 02, the AND circuits 405 and 406 select passage or non-passage to the destination processor side, and as a result, the data reception arbitration circuit 306 having both signals of the data reception signals 808 and 809 as input signals. As a result, the contention of packet data arriving from both networks is avoided, and the first network 501 and the second network 50 are
2 receives packet data. The data reception signal output from the data reception arbitration circuit 306 is logically ANDed with the reception permission signal 704 by the AND circuit 402 and becomes an output 803 to the data buffer 304.

Here, when the data transfer between the processors of one of the networks cannot be continued during the operation of the system, the occurrence of a failure on the network is detected by an internal failure detection circuit (601 for the first network, and for the second network). 602), and notifies the service processor 101 of the fault occurrence of the abnormal network in the first network fault occurrence notification signal 705 or the second network fault occurrence notification signal 706, which normally has a logical value of 0. By setting the signal to the logical value 1, the failure occurrence in the network is notified. Service processor 1
01 receives the notification that a failure has occurred in one of the first network 501 and the second network 502 used in parallel, and each processor 20
The transmission permission signal 703, which normally has a logical value of 1, is switched to a logical value of 0 for 1, ...
03 and the value of the data transmission signal 802 are ANDed by the AND circuit 401 on each processor,
Transmission of new packet data from 1, ..., 202 to the network is suppressed.

After that, the service processor 101 discards all the packet data that has not yet arrived at the destination processor on the network at the time of occurrence of a failure. Therefore, the reception enable signal 704 normally having the logical value 1 is logically output. Switch to the value 0 and set it to each processor 201, ..., 20
By ANDing with the data reception signal 807 by the AND circuit 402 in 2, all the packet data left unarriving at the destination processor in the network at the time of the occurrence of the failure in each processor 201 ,. Discard all when receiving. Furthermore, after a certain period of time, which is set to be sufficient for all the packet data left unarriving on the network at the time of failure to arrive at the data receiving unit of the destination processor and to be discarded, the service processor Reference numeral 101 indicates that the abnormal network is invalidated, that is, the first network validation signal 701 or the second network validation signal 702 is set to a logical value of 0, and the interprocessor data transfer function is operated only on the other normal network. It is stored in the internal configuration information storage unit. After that, the service processor 101 sets the transmission permission signal 703 and the reception permission signal 70, which have been set to the logical value 0 in order to suppress the data transfer between the processors on the network.
4 is switched to the logical value 1 to enable packet data transmission / reception to the other normal network in which the network enable signal has the logical value 1 and continue the inter-processor data transfer function after the above network failure recovery processing. .

It should be noted that networks for data transfer between processors 501, 502 from the respective processors 201, ..., 202.
When transmitting the packet data to the upper side, the transmission source processor determines that the packet data transmission is completed upon receipt of the packet data reception completion notification from the reception destination processor. Therefore, even if the packet data is discarded and lost due to the network failure and the failure recovery process accompanying the network failure before it reaches the destination processor after transmitting the packet data from the transmission source processor to the networks 501 and 502, The transmission source processor recognizes that the reception completion notification from the reception destination processor has not arrived, determines that the packet data transmission has not been completed, and tries to retransmit the packet data. According to this mechanism, by continuing the operation of the inter-processor data transfer function on the other normal network, it is interrupted because the inter-processor data transfer function of one of the redundant networks cannot continue. It is possible to restart the packet data transfer function and the inter-processor packet data transmission / reception function that have been used.

In the above-mentioned embodiment, the example in which the network is duplicated by the first network and the second network has been described. However, either one of the first network and the second network is used as an active and the other is used as a spare. May be. In this case, the service processor 10
1 is one of the normal first network and the second network, for example, the first network is in use, the second network is in standby, the first network enable signal 701 is a logical value 1, and the second network The enable signal 702 is set to a logical value 0. In this state, data transfer between processors is performed as in the above embodiment. When an abnormality occurs in the first network, the transmission of each of the processors 201, ..., 202 is suppressed and the reception of each of the processors 201 ,. All of the packet data that has not yet arrived at the destination processor is discarded when each processor 201, ..., 202 receives it.
Furthermore, after a certain period of time, which is set to be sufficient for all the packet data left unarriving on the network at the time of failure to arrive at the data receiving unit of the destination processor and to be discarded, the service processor 101 invalidates the abnormal network, that is, sets the first network validating signal 701 of the first network in use to a logical value of 0. Then, the second network activation signal 702 of the spare second network is set to the logical value 1. Then, the suppression of transmission and the suppression of reception of each processor 201, ..., 202 are released. Thereby, thereafter, the data transfer between the processors is normally executed by the backup second network.

[0016]

As described above, according to the present invention,
It is possible to improve the operation rate of a parallel computer that connects multiple processors via a network and transfers data between the processors, and after eliminating the effect of a failure in one of the redundant networks, By restarting the operation of the transfer function in the other normal network, it becomes possible to continue the network function after the failure recovery processing. Also, if a failure occurs in one of the duplicated networks, the transmission / reception of new data between the processors in each processor is interrupted at that point, and the failure or failure in one network occurs on the network. In this way, it becomes possible to discard all the data that has not yet arrived at the receiving processor and to continue the system operation after the failure recovery process after the failure recovery process. In addition, when the network is used as a working or protection network, after removing the effect of a failure in the working network, the operation of the inter-processor data transfer function is restarted in the protection network so that the network function after the failure recovery process can be performed. It is possible to continue. Further, when a failure occurs in the working network, transmission / reception of new data between the processors in the network at each processor is interrupted at that time, and when a failure occurs in the working network and a failure occurs in the working network, the receiver processor that has not yet arrived at the destination network has not arrived. It is possible to discard all the remaining data and then continue the system operation by the backup network after the failure recovery processing and the failure recovery processing.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a configuration of a parallel computer system according to an embodiment.

FIG. 2 is a diagram showing details of the configuration of a parallel computer system according to the embodiment.

[Explanation of symbols]

71 processor control signal 72 network monitoring signal 91, 92, 93, 94 inter-processor data transfer signal 101 service processor (SVP) 201 processor (PU (1)) 202 processor (PU (n)) 301 CPU 302 memory 303 for data transmission Buffer 304 Data reception buffer 305 Data transmission arbitration circuit 306 Data reception arbitration circuit 401, 402, 40, 404, 405, 406 AN
D circuit 501 First network for data transfer between processors (NW (1)) 502 Second network for data transfer between processors (NW (2)) 601 and 602 Failure detection circuit 701 First network enable signal 702 Second network enable Signal 703 transmission permission signal 704 reception permission signal 705 first network failure occurrence notification signal 706 second network failure occurrence notification signal 801 data transmission / reception signal 802, 804, 805, 806, 901, 902, 9
05,906 Inter-processor data transmission signal 803,807,808,809,903,904,9
07,908 Inter-processor data reception signal

Claims (2)

[Claims] 1. A parallel computer system comprising a plurality of processors, a network for performing data transfer between the processors, and a service processor, wherein the network is duplicated, wherein each processor selects a network and transmits data. And a reception circuit for selecting a network to receive data, wherein the service processor transmits a transmission permission signal to the transmission circuit, a reception permission signal to the reception circuit, and a network corresponding to each network for the transmission circuit and the reception circuit. Outputs an enable signal to enable data transfer between processors on both networks, and when receiving a fault notification signal from one network, turns off the transmission permission signal and reception permission signal to suppress data transmission and reception. And discard all data on the network After, parallel computer system in which the transmission permission signal and to turn on the receive enable signal, characterized in that to enable inter-processor data transfer by the other network as well as to the one of the network-enabled network enable signal off. 2. A parallel computer system comprising a plurality of processors, a network for performing data transfer between processors, and a service processor, wherein the network comprises a working network and a spare network, wherein each processor selects a network to perform data transfer. Is provided with a receiving circuit that receives data by selecting a transmitting circuit and a network, and the service processor transmits a transmitting permission signal to the transmitting circuit, a receiving permission signal to the receiving circuit, and the transmitting circuit and the receiving circuit. Outputs a network enable signal for each network, turns on the network enable signal for the active network when using the active network, and turns off the network enable signal for the spare network to transfer data between processors via the active network When the fault occurrence notification signal is received from the working network, the transmission permission signal and the reception permission signal are turned off to inhibit the transmission and reception of data, and all the data on the working network are discarded before the working A network enabling signal for a network is turned off, and a transmission enabling signal, a reception enabling signal, and a network enabling signal for the spare network are turned on to enable data transfer between processors by the spare network. Parallel computer system.