JPH08153830A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH08153830A JPH08153830A JP29522994A JP29522994A JPH08153830A JP H08153830 A JPH08153830 A JP H08153830A JP 29522994 A JP29522994 A JP 29522994A JP 29522994 A JP29522994 A JP 29522994A JP H08153830 A JPH08153830 A JP H08153830A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- substrate
- wiring board
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置およびその
製造方法に係り、特に片面樹脂封止型パッケージ構造を
有する半導体装置およびチップ封止用樹脂層の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a single-sided resin-sealed package structure and a method for forming a resin layer for chip sealing.
【０００２】[0002]
【従来の技術】例えば集積回路カード、ゲーム用マスク
ＲＯＭカード、小型携帯電話器などに使用される半導体
装置は、パッケージの小型化・薄型化に対する要求が特
に強い。このような要求に応じるべく、ベア状態の半導
体チップ（ベア・チップ）の実装技術が発展しており、
チップ・オン・ボード（ＣＯＢ）実装、フリップチップ
実装などが知られている。2. Description of the Related Art For semiconductor devices used in, for example, integrated circuit cards, mask ROM cards for games, small mobile phones, etc., there is a strong demand for miniaturization and thinning of packages. In order to meet such demands, mounting technology of bare semiconductor chips (bare chips) has been developed,
Chip-on-board (COB) mounting, flip-chip mounting, etc. are known.
【０００３】上記フリップチップ実装は、ベア・チップ
の素子形成面の金属バンプ電極を配線基板上の一主面に
形成されている電極パッドに押し付けて接続（フリップ
チップボンディング）するものである。これは、ワイヤ
ーボンディングを必要とするＣＯＢ実装よりも実装密度
が優れているが、基板の熱膨脹などに起因する応力が基
板・チップの接続部に加わって接続の信頼性を損なうと
いう問題がある。In the flip chip mounting, the metal bump electrodes on the element forming surface of the bare chip are pressed against the electrode pads formed on one main surface of the wiring board to connect (flip chip bonding). This has a higher mounting density than the COB mounting which requires wire bonding, but has a problem that stress due to thermal expansion of the substrate is applied to the connecting portion between the substrate and the chip to impair the reliability of the connection.
【０００４】上記フリップチップ実装の改良例として、
ベア・チップと基板との間に樹脂を介在させて基板・チ
ップ相互を機械的に固定した片面樹脂封止型パッケージ
構造が例えば特公平２−７１８０号などにより知られて
いる。As an improved example of the flip chip mounting,
A single-sided resin-sealed package structure in which a resin is interposed between a bare chip and a substrate to mechanically fix the substrate and the chip together is known, for example, from Japanese Patent Publication No. 2-7180.
【０００５】さらに、上記片面樹脂封止型パッケージ構
造の改良例およびその製造方法として、本願出願人の出
願に係る特願平６−３２２９６号、特願平６−５０７５
７号、特願平６−６０４９３号などにより種々の提案が
なされている。Further, as an improved example of the single-sided resin-encapsulated package structure and a manufacturing method thereof, Japanese Patent Application Nos. Hei 6-32296 and Hei 6-5075, filed by the applicant of the present application, are disclosed.
Various proposals have been made in Japanese Patent No. 7 and Japanese Patent Application No. 6-60493.
【０００６】図４は、上記提案に係る特願平６−５０７
５７号に開示されている片面樹脂封止型パッケージ構造
の一例を示している。このパッケージ構造は、一主面に
被接続部（例えば接続パッド１ｂ）を含む配線１ａを有
する配線基板１と、上記基板の一主面にフェースダウン
型に実装された半導体チップ２と、上記チップと配線基
板との間に充填された樹脂層５と、前記基板の他の主面
側に導出・露出され、前記チップに電気的に接続された
外部接続用端子４とを具備する。なお、図４中、２ａは
バンプ電極、３はスルーホール配線である。FIG. 4 shows a Japanese Patent Application No. 6-507 (Japanese Patent Application No. 6-507) relating to the above proposal.
57 shows an example of a single-sided resin-sealed package structure disclosed in No. 57. This package structure has a wiring board 1 having a wiring 1a including a connected portion (for example, a connection pad 1b) on one main surface, a semiconductor chip 2 mounted face down on the one main surface of the board, and the chip described above. And a wiring layer, and a resin layer 5 filled between the wiring board and the wiring board, and an external connection terminal 4 which is led out and exposed on the other main surface side of the board and electrically connected to the chip. In FIG. 4, 2a is a bump electrode and 3 is a through hole wiring.
【０００７】図５は、前記提案に係る特願平６−６０４
９３号に開示されている片面樹脂封止型パッケージ構造
の一例を示している。このパッケージ構造は、図４のパ
ッケージ構造の改良例であり、前記基板１の一主面に対
してほぼ同一平面（平面性が±１０μｍ程度）を成すよ
うに前記配線１ａを埋め込み形成している。なお、図５
において、図４中と同一部分には同一符号を付してい
る。FIG. 5 shows a Japanese Patent Application No. 6-604 relating to the above proposal.
An example of a single-sided resin-sealed package structure disclosed in No. 93 is shown. This package structure is an improved example of the package structure shown in FIG. 4, and the wiring 1a is formed by embedding so as to form substantially the same plane (planarity is about ± 10 μm) with respect to one main surface of the substrate 1. . Note that FIG.
4, the same parts as those in FIG. 4 are denoted by the same reference numerals.
【０００８】このパッケージ構造によれば、チップ・基
板間に対して毛細管現象を利用して樹脂を流し込む際、
チップ・基板間の平坦性がよく、樹脂が容易に流れ込む
ので、ボイドのない緻密な樹脂層を形成でき、チップ・
基板間固定の信頼性を高めることができる。According to this package structure, when the resin is poured between the chip and the substrate by utilizing the capillary phenomenon,
The flatness between the chip and substrate is good, and the resin easily flows in, so a dense resin layer without voids can be formed.
The reliability of fixation between substrates can be improved.
【０００９】ところで、図４、図５中の樹脂層５の形成
に際しては、図６に示すように、樹脂供給装置（ディス
ペンサ）のノズル（ニードル）７１から樹脂５ａを基板
１上の一辺部に供給し、いわゆる毛細管現象を利用して
チップ・基板間に樹脂を流し込んで充填した後に硬化さ
せる。なお、チップ２の露出している上面は、緻密、堅
牢な素材（例えばシリコン）からなり、樹脂封止を行わ
なくても信頼性上の問題は少ない。By the way, when forming the resin layer 5 in FIGS. 4 and 5, as shown in FIG. 6, the resin 5a is applied to one side of the substrate 1 from the nozzle (needle) 71 of the resin supply device (dispenser). The resin is supplied and the resin is poured between the chip and the substrate by utilizing the so-called capillary phenomenon to fill the resin and then cured. The exposed upper surface of the chip 2 is made of a dense and robust material (for example, silicon), and there is little problem in reliability without resin sealing.
【００１０】また、上記したような提案に係るパッケー
ジ構造を有する半導体装置は、樹脂封止後に温度ストレ
スおよび／または電界ストレスを印加するためのバーン
インテストを実施し得るので、樹脂封止を行わないフリ
ップチップ実装よりも優れている。In the semiconductor device having the package structure according to the above proposal, since the burn-in test for applying the temperature stress and / or the electric field stress can be performed after the resin sealing, the resin sealing is not performed. Better than flip chip mounting.
【００１１】ところで、前記したような樹脂充填方法で
は、図６に示すように、基板上の樹脂供給側とは反対側
の一辺部にはみ出した樹脂（その表面形状をフィレット
と称する。）のはみ出し量（約０．２５ｍｍ）Ｓ１より
も、基板上の樹脂供給側の一辺部における樹脂のはみ出
し量Ｓ２の方がはるかに大きい。因みに、樹脂供給側の
一辺部におけるはみ出し量は、チップ・基板間の容積を
基準にして樹脂供給量が２倍の場合に最大０．８３ｍ
ｍ、３倍の場合に最大１．１５ｍｍ、４倍の場合に最大
２．１２ｍｍであった。By the way, in the resin filling method as described above, as shown in FIG. 6, the resin (the surface shape thereof is referred to as a fillet) protruding from one side of the substrate opposite to the resin supply side is protruded. The resin protrusion amount S2 at one side of the substrate on the resin supply side is much larger than the amount (about 0.25 mm) S1. By the way, the protrusion amount on one side of the resin supply side is 0.83m at maximum when the resin supply amount is twice as large as the volume between the chip and the substrate.
m was 3.15 times, the maximum was 1.15 mm, and 4 times was the maximum 2.12 mm.
【００１２】また、樹脂供給側とは反対側の一辺部にお
いては、樹脂のはみ出し量Ｓ１は樹脂の物性でほぼ決ま
るが、樹脂供給側の一辺部においては、チップに触れな
いようにニードル７１を接近させて樹脂を供給するの
で、樹脂のはみ出し量Ｓ２はニードルのサイズ（現在使
用している標準型のものは外径０．８２ｍｍ、１．２５
ｍｍなど）より大きくなる。On the side opposite to the resin supply side, the resin protrusion amount S1 is substantially determined by the physical properties of the resin, but on the side of the resin supply side, the needle 71 is placed so as not to touch the tip. Since the resin is supplied in close proximity, the amount of resin squeeze out S2 is the size of the needle (the standard type currently used is 0.82 mm in outer diameter, 1.25 mm
mm).
【００１３】また、前記したような樹脂充填方法では、
チップ外縁・基板外縁間の距離（樹脂の供給スペース）
Ｓ３を小さくしようとする場合、ニードル７１の外径に
より制約され、ニードルの外径小さくしようとすると、
樹脂の目詰りなどが生じ、樹脂を基板上のチップ側方部
に正常に供給することが困難になる。Further, in the resin filling method as described above,
Distance between chip outer edge and substrate outer edge (resin supply space)
When trying to reduce S3, it is restricted by the outer diameter of the needle 71, and when trying to reduce the outer diameter of the needle,
The resin is clogged, and it becomes difficult to normally supply the resin to the side portion of the chip on the substrate.
【００１４】また、前記したような樹脂充填方法は、チ
ップ側面の上縁部まで完全にフィレットを形成させるよ
うに封止させてはいない。仮に、基板上の樹脂供給側の
一辺部ではチップ側面の上縁部まで完全にフィレットを
形成できたとしても、基板上の樹脂供給側とは反対側の
一辺部ではチップ側面の上縁部まで完全にフィレットを
形成させるように封止することが困難である。In the resin filling method as described above, the fillet is not completely sealed up to the upper edge of the side surface of the chip. Even if the fillet could be completely formed up to the upper edge of the chip side on one side of the resin supply side on the substrate, the fillet could be formed up to the upper edge of the chip side on one side opposite to the resin supply side on the substrate. It is difficult to seal to form a complete fillet.
【００１５】上記したような構造の半導体装置は、外部
からの衝撃などによりベア・チップが破損するおそれが
強く、パッケージの外観不良を引き起こし易い。特に、
ベア・チップの基板材料として通常用いられるシリコン
は、脆性を有するので、小さな衝撃荷重でも破損し易
い。In the semiconductor device having the above-mentioned structure, the bare chip is highly likely to be damaged by an external impact or the like, and the appearance of the package is likely to be defective. In particular,
Silicon, which is usually used as a substrate material for bare chips, has brittleness and is easily damaged by a small impact load.
【００１６】また、上記したような樹脂によりベア・チ
ップ側面の上縁部まで完全には封止されていない半導体
装置は、外部の環境の影響を受け易く、信頼性の点で必
ずしも十分ではない。A semiconductor device in which the upper edge portion of the side surface of the bare chip is not completely sealed with the resin as described above is easily affected by the external environment and is not always sufficient in terms of reliability. .
【００１７】そこで、樹脂をチップと基板との間に隙間
なく充填し、かつ、チップの各外周側面を樹脂でほぼ均
等に覆うようにするために、ニードル７１から１回で吐
き出す樹脂量を増やすと、ニードル７１から吐き出した
樹脂がチップ上面に乗り上げたり基板端面から垂れ下が
ったりしてパッケージの仕上がり寸法のばらつきや外観
上の不具合が生じるおそれがある。Therefore, the amount of resin discharged from the needle 71 at one time is increased in order to fill the resin between the chip and the substrate without leaving a gap and to cover the outer peripheral side surfaces of the chip almost uniformly with the resin. As a result, the resin discharged from the needle 71 may run onto the upper surface of the chip or hang down from the end surface of the substrate, causing variations in the finished dimensions of the package and defects in appearance.
【００１８】一方、上記したような片面樹脂封止型パッ
ケージ構造の一層の小型化が要求され、チップとチップ
サイズに近い基板とをフリップチップボンディングした
後の状態で基板の各辺部においてチップ外縁・基板外縁
間の距離Ｓ３を例えば１ｍｍ以下にすることが要求され
てきている。On the other hand, further miniaturization of the single-sided resin-sealed package structure as described above is required, and after the chip and the substrate close to the chip size are flip-chip bonded, the chip outer edge is formed on each side of the substrate. -It has been required to set the distance S3 between the outer edges of the substrate to, for example, 1 mm or less.
【００１９】しかし、チップ外縁・基板外縁間の距離が
微小になると、樹脂の供給スペースが狭くなるので、前
記したようにチップの各外周側面を樹脂でほぼ均等に覆
うように樹脂の供給量を増やすために、ニードル７１か
ら１回で吐き出す樹脂量を増やすと、やはり、前記した
ようにニードル７１から吐き出した樹脂がチップ上面に
乗り上げたり基板端面から垂れ下がったりしてパッケー
ジの仕上がり寸法のばらつきや外観上の不具合が生じる
おそれがある。However, if the distance between the outer edge of the chip and the outer edge of the substrate becomes small, the space for supplying the resin becomes narrower. Therefore, as described above, the amount of the resin supplied is such that the outer peripheral side surfaces of the chip are almost evenly covered with the resin. When the amount of resin discharged from the needle 71 at one time is increased in order to increase the amount, the resin discharged from the needle 71 still rides on the upper surface of the chip or hangs down from the end face of the substrate as described above. The above problem may occur.
【００２０】換言すれば、従来の樹脂充填方法では、充
填しようとする樹脂量を調整して１回の樹脂供給でチッ
プ・基板間での毛細管現象を利用して樹脂を流し込むこ
とによりチップ側面部に理想の形状のフィレットを形成
させることが非常に困難であった。In other words, in the conventional resin filling method, the amount of resin to be filled is adjusted, and the resin is poured into the side surface of the chip by utilizing the capillary phenomenon between the chip and the substrate in a single resin supply. It was very difficult to form a fillet with an ideal shape.
【００２１】[0021]
【発明が解決しようとする課題】上記したように従来の
片面樹脂封止型パッケージ構造を有する半導体装置は、
樹脂によりベア・チップ側面の上縁部まで完全には封止
しないので、得られた半導体装置が外部の環境の影響を
受け易く、信頼性の点で必ずしも十分ではないという問
題があった。As described above, the semiconductor device having the conventional single-sided resin-sealed package structure is
Since the resin is not completely sealed up to the upper edge portion of the side surface of the bare chip, there is a problem that the obtained semiconductor device is easily affected by the external environment and is not always sufficient in terms of reliability.
【００２２】また、従来の片面樹脂封止型パッケージ構
造の樹脂封止方法は、樹脂をベア・チップと基板との間
に隙間なく充填し、かつ、ベア・チップの外周側面を樹
脂で覆うために、ニードルから１回で吐き出す樹脂量を
増やすと、フィレットの裾部分が広がって樹脂が基板端
面から垂れ下がったり、ニードルから吐き出した樹脂が
チップ上面に乗り上げたりしてパッケージの仕上がり寸
法のばらつきや外観上の不具合が生じるという問題があ
った。Further, in the conventional resin encapsulation method of the single-sided resin encapsulation type package structure, the resin is filled without any gap between the bare chip and the substrate, and the outer peripheral side surface of the bare chip is covered with the resin. In addition, when the amount of resin discharged from the needle at one time is increased, the skirt of the fillet spreads and the resin hangs down from the end surface of the substrate, or the resin discharged from the needle runs onto the top surface of the chip, resulting in variations in package finish size and appearance. There was a problem that the above trouble occurred.
【００２３】本発明は上記の問題点を解決すべくなされ
たもので、ベア・チップが外部の環境や衝撃などの影響
を受け難く、信頼性の高い半導体装置を提供することを
目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable semiconductor device in which the bare chip is not easily affected by the external environment or shock.
【００２４】また、本発明は、片面樹脂封止型パッケー
ジ構造を有する半導体装置を製造する際、チップ外縁・
基板外縁間の距離が微小の場合でも、ニードルから１回
で吐き出す樹脂量を増やさずに、チップと配線基板とを
固定すると共にチップの外周側面上縁部から配線基板上
面の外周縁部までを完全に覆う樹脂層を形成でき、信頼
性が高く一層の小型化を図り得る半導体装置の製造方法
を提供することを目的とする。Further, according to the present invention, when manufacturing a semiconductor device having a single-sided resin-sealed package structure, the chip outer edge /
Even if the distance between the outer edges of the substrate is small, the chip and the wiring board are fixed and the area from the upper edge of the outer peripheral side surface of the chip to the outer edge of the upper surface of the wiring board is increased without increasing the amount of resin discharged from the needle at one time. An object of the present invention is to provide a method of manufacturing a semiconductor device, which can form a resin layer that completely covers the semiconductor device, has high reliability, and can be further miniaturized.
【００２５】[0025]
【課題を解決するための手段】本発明の半導体装置は、
一主面に被接続部を含む配線を有する配線基板と、上記
配線基板の一主面にフェースダウン型に実装された半導
体チップと、上記半導体チップと配線基板との間に充填
されると共に上記半導体チップの外周側面上縁部から前
記配線基板上面の外周縁部までを覆い、上記半導体チッ
プの各外周側面部にほぼ均等なフィレットを有するよう
に形成された樹脂層と、前記配線基板の他の主面側に導
出・露出され、前記半導体チップに電気的に接続された
外部接続用端子とを具備することを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A wiring board having a wiring including a connected portion on one main surface, a semiconductor chip mounted face down on the one main surface of the wiring board, and filled between the semiconductor chip and the wiring board and A resin layer that covers from the upper edge of the outer peripheral side surface of the semiconductor chip to the outer peripheral edge of the upper surface of the wiring board, and has a substantially uniform fillet on each outer peripheral side surface of the semiconductor chip; An external connection terminal that is led out / exposed on the main surface side of and is electrically connected to the semiconductor chip.
【００２６】また、本発明の半導体装置の製造方法は、
一主面に被接続部を含む配線を有し、他主面に外部接続
用端子を導出・露出させた配線基板の被接続部とこれに
対応する半導体チップの電極端子部の位置が対向するよ
うに半導体チップを配置する工程と、上記配線基板の被
接続部とこれに対応する半導体チップの電極端子部を固
定接続する工程と、この後、上記半導体チップと配線基
板とを固定すると共に上記半導体チップを封止するため
の樹脂層を形成する工程と、上記充填した封止用樹脂を
硬化させる工程とを具備し、前記チップ封止用の樹脂層
を形成する際、前記配線基板上の前記チップ・基板間の
開口部に第１の樹脂を供給し、チップ・基板間における
第１の樹脂樹脂の毛細管現象を利用して上記チップ・基
板間に第１の樹脂を充填する第１の樹脂供給工程と、上
記工程により充填した第１の樹脂を硬化させた後あるい
は硬化させる前に上記第１の樹脂上で前記半導体チップ
の外周側面部から前記配線基板上面の外周縁部にかけて
第２の樹脂を供給する第２の樹脂供給工程と、上記工程
により供給した第２の樹脂を単独であるいは前記第１の
樹脂と共に硬化させる樹脂硬化工程とを具備することを
特徴とする。The method of manufacturing a semiconductor device according to the present invention is
The wiring board including the connected portion is provided on one main surface, and the connected portion of the wiring board on which the external connection terminals are led out / exposed on the other main surface and the corresponding electrode terminal portion of the semiconductor chip face each other. As such, the step of arranging the semiconductor chip, the step of fixedly connecting the connected portion of the wiring board and the electrode terminal portion of the semiconductor chip corresponding thereto, and thereafter fixing the semiconductor chip and the wiring board together with the above A step of forming a resin layer for encapsulating a semiconductor chip; and a step of curing the filled encapsulating resin, and when forming the resin layer for encapsulating the chip, on the wiring board The first resin is supplied to the opening between the chip and the substrate, and the first resin is filled between the chip and the substrate by utilizing the capillary phenomenon of the resin between the chip and the substrate. Resin supply process and filling by the above process A second resin that supplies the second resin after curing the first resin or before curing the first resin from the outer peripheral side surface portion of the semiconductor chip to the outer peripheral edge portion of the wiring board upper surface. It is characterized by comprising a supply step and a resin curing step of curing the second resin supplied in the above step alone or together with the first resin.
【００２７】[0027]
【作用】本発明の半導体装置は、片面樹脂封止型パッケ
ージ構造を有する半導体装置において、半導体チップと
配線基板とを固定するための樹脂層は、半導体チップと
配線基板との間に充填されると共に半導体チップの外周
側面上縁部から配線基板上面の外周縁部までを覆い、上
記半導体チップの各外周側面部にほぼ均等なフィレット
を有するように形成されている。The semiconductor device of the present invention is a semiconductor device having a single-sided resin-sealed package structure, and a resin layer for fixing the semiconductor chip and the wiring board is filled between the semiconductor chip and the wiring board. At the same time, the semiconductor chip is formed so as to cover from the outer peripheral side upper edge portion to the outer peripheral edge portion of the wiring board upper surface, and to have substantially uniform fillets on the outer peripheral side surface portions of the semiconductor chip.
【００２８】従って、チップと基板とが機械的に強固に
固定されており、熱などによる内部応力の他に機械的応
力などからも保護されるので、ベア・チップが外部の環
境や衝撃などの影響を受け難くなり、半導体装置の信頼
性が向上する。Therefore, since the chip and the substrate are mechanically firmly fixed and protected from internal stress such as heat as well as mechanical stress, the bare chip is protected from external environment and impact. It is less likely to be affected and the reliability of the semiconductor device is improved.
【００２９】また、本発明の半導体装置の製造方法は、
片面樹脂封止型パッケージ構造を有する半導体装置の製
造に際して封止用樹脂を充填する際、配線基板上の前記
チップ・基板間の開口部に第１の樹脂を供給し、チップ
・基板間における第１の樹脂樹脂の毛細管現象を利用し
て上記チップ・基板間に第１の樹脂を充填し、上記第１
の樹脂を硬化させた後あるいは硬化させる前に、さら
に、上記第１の樹脂上で前記半導体チップの外周側面部
から配線基板上面の外周縁部にかけて第２の樹脂を供給
した後、上記第２の樹脂を単独であるいは前記第１の樹
脂と共に硬化させる。The method of manufacturing a semiconductor device according to the present invention is
When filling the encapsulating resin in the production of a semiconductor device having a single-sided resin-encapsulated package structure, the first resin is supplied to the opening between the chips and the substrate on the wiring substrate, and the first resin between the chips and the substrate is provided. First resin is filled with the first resin between the chip and the substrate by utilizing the capillary phenomenon of the resin.
After or before curing the resin, the second resin is further supplied on the first resin from the outer peripheral side surface portion of the semiconductor chip to the outer peripheral edge portion of the wiring board upper surface. The resin is cured alone or together with the first resin.
【００３０】これにより、チップ・基板間に樹脂を充填
すると共に、チップの外周側面上縁部から基板上面の外
周縁部までを覆い、チップの各外周側面部にほぼ均等な
理想の形状のフィレットを有する樹脂層を形成すること
が可能になる。As a result, the resin is filled between the chip and the substrate, and the fillet having an ideal shape is formed so as to cover from the upper edge portion of the outer peripheral side surface of the chip to the outer peripheral edge portion of the upper surface of the substrate, and to equip each outer peripheral side surface portion of the chip. It is possible to form a resin layer having
【００３１】この際、樹脂供給工程を２回に分けている
ので、ニードルから１回で吐き出す樹脂量を増やす必要
がなくなり、チップ外縁・基板外縁間の距離が微小の場
合でも、従来と同様のディスペンサと使用樹脂の性質に
見合った口径を有するニードルを使用でき、ニードルか
ら吐き出した樹脂がチップ上面に乗り上げたり基板端面
から垂れ下がったりしてパッケージの仕上がり寸法のば
らつきや外観上の不具合が生じるおそれがなくなる。従
って、半導体装置の一層の小型化を図り、製造上の歩留
り、信頼性を向上させ、コストダウンを図ることが可能
になる。At this time, since the resin supply process is divided into two, it is not necessary to increase the amount of resin discharged from the needle once, and even when the distance between the chip outer edge and the substrate outer edge is small, the same as in the conventional case. It is possible to use a dispenser and a needle with a diameter that matches the properties of the resin used, and the resin discharged from the needle may run onto the top surface of the chip or hang down from the board end surface, causing variations in the finished dimensions of the package and appearance defects. Disappear. Therefore, it is possible to further reduce the size of the semiconductor device, improve the manufacturing yield and reliability, and reduce the cost.
【００３２】[0032]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図１（ａ）乃至（ｃ）は、本発明の一実施
例に係る片面樹脂封止型パッケージ構造を有する半導体
装置の製造工程、特に樹脂封止工程の一例を概略的に示
している。Embodiments of the present invention will be described below in detail with reference to the drawings. 1A to 1C schematically show an example of a manufacturing process of a semiconductor device having a single-sided resin-sealed package structure, particularly a resin-sealed process, according to an embodiment of the present invention.
【００３３】図２（ａ）乃至（ｃ）は、図１（ａ）乃至
（ｃ）の工程に対応する樹脂の封止状態を示しており、
図２（ｃ）は、完成後の半導体装置の上面を示してい
る。図３は、完成後の半導体装置の断面構造を示してい
る。FIGS. 2A to 2C show a resin sealing state corresponding to the steps of FIGS. 1A to 1C.
FIG. 2C shows the top surface of the completed semiconductor device. FIG. 3 shows a sectional structure of the completed semiconductor device.
【００３４】この半導体装置は、一主面に被接続部１ｂ
を含む配線１ａを有する配線基板１と、上記基板の一主
面にフェースダウン型に実装された半導体チップ２と、
上記チップと基板との間に充填されると共にチップの外
周側面上縁部から基板上面の外周縁部までを覆った状態
のフィレットをチップの各外周側面部にほぼ均等に有す
る樹脂層５と、前記基板の他の主面側に導出・露出さ
れ、前記チップに電気的に接続された外部接続用端子４
とを具備する。This semiconductor device has a connection portion 1b on one main surface.
A wiring substrate 1 having a wiring 1a including a semiconductor chip 2 mounted face down on one main surface of the substrate,
A resin layer 5 which is filled between the chip and the substrate, and which has fillets in a state of covering from the upper edge portion of the outer peripheral side surface of the chip to the outer peripheral edge portion of the upper surface of the substrate substantially evenly on each outer peripheral side surface portion of the chip; External connection terminal 4 which is led out / exposed to the other main surface side of the substrate and electrically connected to the chip.
And
【００３５】次に、図１および図２を参照しながら、配
線基板１と半導体チップ２とをボンディングするまでの
工程の一例を簡単に説明する。上記チップ２として、素
子形成面の外部接続用パッド部上に導電性物質、例えば
金属からなるバンプ電極（例えば直径１００μｍ、高さ
３０μｍ）２ａが形成されているものを用意する。上記
バンプ電極２ａは、例えば電気メッキ法により形成され
た金バンプあるいはボールボンディング法により形成さ
れた金のボールバンプである。Next, an example of steps for bonding the wiring board 1 and the semiconductor chip 2 will be briefly described with reference to FIGS. 1 and 2. As the chip 2, a chip having a bump electrode (for example, a diameter of 100 μm and a height of 30 μm) 2a made of a conductive substance, such as a metal, is prepared on the pad for external connection on the element formation surface. The bump electrodes 2a are, for example, gold bumps formed by electroplating or gold ball bumps formed by ball bonding.
【００３６】前記配線基板１として、一主面に被接続部
１ｂを含む配線１ａを有し、上記被接続部１ｂからスル
ーホール配線３を介して他の主面側に導出・露出され、
格子状に配列された平面型の外部接続用端子４を具備す
るものを用意する。The wiring board 1 has a wiring 1a including a connected portion 1b on one main surface, and is led out and exposed from the connected portion 1b to the other main surface side through the through-hole wiring 3.
The thing provided with the planar type external connection terminal 4 arranged in the shape of a lattice is prepared.
【００３７】本例では、上記基板１は、配線１ａおよび
外部接続用端子４が絶縁基材面から少し（例えば３５μ
ｍ程度）突出している。なお、前記基板１の一主面に被
接続部１ｂを形成する際には、一主面に配線１ａを有す
る基板１を例えば真空吸着機構付きのスクリーン印刷機
のステージ上に固定し、基板上１でチップの金属バンプ
電極２ａに対応する部分に平面型の接続パッド（例えば
直径１５０μｍ、高さ８０μｍ）１ｂを形成する。この
際、チップのバンプ電極２ａに対応する開口（例えば１
５０μｍ×１５０μｍ）を有するメタルマスクを用いて
基板の配線形成面上に導電性ペースト、例えば銀ペース
ト（銀の粒径１μｍ、粘度１００ｐｓ）をスクリーン印
刷して前記接続パッド１ｂを形成する。In this example, in the substrate 1, the wiring 1a and the external connection terminals 4 are slightly (for example, 35 μm) from the surface of the insulating base material.
about m) protruding. When forming the connected portion 1b on the one main surface of the substrate 1, the substrate 1 having the wiring 1a on the one main surface is fixed on a stage of a screen printing machine with a vacuum suction mechanism, for example. In step 1, a flat type connection pad (for example, a diameter of 150 μm and a height of 80 μm) 1b is formed on a portion of the chip corresponding to the metal bump electrode 2a. At this time, openings (for example, 1
The connection pad 1b is formed by screen-printing a conductive paste, for example, a silver paste (silver grain size 1 μm, viscosity 100 ps) on the wiring formation surface of the substrate using a metal mask having a size of 50 μm × 150 μm.
【００３８】次に、チップ２を真空吸着し得る機構を有
するボンディング装置を用いて基板１上にチップ２をフ
ェースダウン型に実装するためにフリップチップボンデ
ィングを行う。この場合、上記基板の接続パッド１ｂに
対してチップの対応するバンプ電極２ａが対向するよう
に配置し、ボンディングヘッドを押し下げることにより
接続パッドにバンプ電極の少なくとも先端部を埋め込む
ように圧入して両者を固定させ、この状態で前記接続パ
ッド１ｂ用の銀ペーストを熱硬化させることにより両者
を接合する。Next, flip chip bonding is performed to mount the chip 2 face down on the substrate 1 using a bonding apparatus having a mechanism capable of vacuum chucking the chip 2. In this case, the bump electrodes 2a corresponding to the chip are arranged so as to face the connection pads 1b on the substrate, and the bonding head is pressed down to press-fit the connection pads so that at least the tip portions of the bump electrodes are embedded. Are fixed, and in this state, the silver paste for the connection pad 1b is thermally cured to bond them.
【００３９】次に、上記したように基板上にチップがフ
リップチップボンディングされた状態において樹脂層５
を形成する。この樹脂層５は、チップと基板との間（本
例では３０〜４０μｍ）に充填された部分と、チップの
外周側面上縁部から基板上面の外周縁部までを覆い、チ
ップの各外周側面部にほぼ均等なフィレットを有する部
分とを有する。Next, in the state where the chip is flip-chip bonded on the substrate as described above, the resin layer 5 is formed.
To form. The resin layer 5 covers the portion filled between the chip and the substrate (30 to 40 μm in this example), the outer peripheral side upper edge of the chip to the outer peripheral edge of the substrate upper surface, and each outer peripheral side surface of the chip. And a portion having a substantially uniform fillet.
【００４０】ところで、基板１のサイズが、例えば縦横
とも１５ｍｍ、厚さ０．２ｍｍであり、チップ２のサイ
ズは、例えば縦横とも１３ｍｍ、厚さ０．２５ｍｍであ
るとすると、基板１の各辺部においてチップ外縁・基板
外縁間の距離Ｓ３が極めて小さく（１ｍｍ以下）、基板
１の一辺部の端部上に樹脂を供給する際に、樹脂の供給
スペースが狭いので、樹脂がチップ上面に乗り上げたり
基板端面から垂れ下がることがないように工夫する必要
がある。If the size of the substrate 1 is, for example, 15 mm in length and width and 0.2 mm in thickness, and the size of the chip 2 is, for example, 13 mm in length and width and 0.25 mm in thickness, each side of the substrate 1 is assumed. The distance S3 between the outer edge of the chip and the outer edge of the substrate is extremely small (1 mm or less), and when the resin is supplied onto the end of one side of the substrate 1, the resin supply space is narrow, so the resin runs on the top surface of the chip. It is necessary to devise it so that it does not hang down from the substrate end face.
【００４１】そこで、本実施例においては、前記樹脂層
５を形成する際に、図１および図２に示すように、樹脂
供給工程を２回に分けている。即ち、基板上のチップ・
基板間の開口部に第１の樹脂５ａを供給し、チップ・基
板間における樹脂の毛細管現象を利用してチップ・基板
間に第１の樹脂５ａを充填する第１の樹脂供給工程と、
上記工程により充填した第１の樹脂５ａを例えば熱によ
り硬化させた後に第１の樹脂５ａ上でチップの外周側面
部から基板上面の外周縁部にかけて第２の樹脂５ｂを供
給する第２の樹脂供給工程とを具備し、上記工程により
供給した第２の樹脂５ｂを例えば熱により硬化させるよ
うにしている。Therefore, in this embodiment, when the resin layer 5 is formed, the resin supply step is divided into two steps as shown in FIGS. That is, the chip on the substrate
A first resin supplying step of supplying the first resin 5a to the opening between the substrates and filling the first resin 5a between the chip and the substrate by utilizing the capillary action of the resin between the chip and the substrate;
A second resin that supplies the second resin 5b from the outer peripheral side surface portion of the chip to the outer peripheral edge portion of the chip on the first resin 5a after the first resin 5a filled in the above step is cured by, for example, heat. The second resin 5b supplied in the above step is cured by, for example, heat.
【００４２】なお、本実施例の各工程は、既存の半導体
装置用の自動組立装置および新規に制作される専用装置
を用いて自動的に実施される。前記樹脂供給工程におい
ては、樹脂が適度の流動性などを呈する条件に設定し、
あるいは、液状の樹脂を使用する。Each step of this embodiment is automatically carried out by using an existing automatic assembly apparatus for semiconductor devices and a newly produced special apparatus. In the resin supply step, the resin is set to a condition that exhibits appropriate fluidity,
Alternatively, a liquid resin is used.
【００４３】そして、第１の樹脂供給工程においては、
チップをボンディングした状態の基板をワーク上に載置
し、従来と同様のディスペンサあるいは他の方法を用い
て、基板の一辺部の端部上に例えば一文字状に第１の樹
脂５ａをほぼ一定量だけ供給する。この場合、第１の樹
脂５ａがチップ・基板間の開口部に付着するように供給
することが望ましい。これにより、樹脂５ａの毛細管現
象が始まり、チップ・基板間における樹脂の毛細管現象
を利用してチップ・基板間にほぼ均等に樹脂５ａを流し
込んで充填させることが可能になる。この際、上記毛細
管現象を促進するために、樹脂充填部に例えば６０℃程
度の温度を加えるようにすれば、樹脂の粘度が低下し、
樹脂の流し込み速度が向上する。Then, in the first resin supplying step,
A substrate with chips bonded is placed on a work, and the same amount of the first resin 5a is formed in a letter on the end of one side of the substrate by using a dispenser or another method similar to the conventional one. Supply only. In this case, it is desirable that the first resin 5a be supplied so as to adhere to the opening between the chip and the substrate. As a result, the capillarity phenomenon of the resin 5a starts, and the resin capillarity phenomenon between the chip and the substrate can be utilized to allow the resin 5a to be poured and evenly filled between the chip and the substrate. At this time, in order to promote the above-mentioned capillary phenomenon, if a temperature of about 60 ° C. is applied to the resin-filled portion, the viscosity of the resin decreases,
The resin pouring speed is improved.
【００４４】これに対して、第２の樹脂供給工程におい
ては、従来と同様のディスペンサあるいは他の方法を用
いて、前記ワーク上の基板の各辺部における第１の樹脂
上でチップの外周側面部から基板上面の外周縁部にかけ
て第２の樹脂を供給する。この場合、ワークを回転させ
たり樹脂供給用の例えばニードル１０を移動させたりし
てニードルと基板の各辺部とを順次対向させて第２の樹
脂を上記各辺部に順次供給し、あるいは、方形リング状
の開口部を有するニードルを使用し、上記開口部を基板
の各辺部に対向させて第２の樹脂を同時に供給する。On the other hand, in the second resin supplying step, the same peripheral surface of the chip is formed on the first resin on each side of the substrate on the workpiece by using the same dispenser or another method as in the conventional case. Portion to the outer peripheral edge portion of the upper surface of the substrate. In this case, the work is rotated or, for example, the needle 10 for supplying resin is moved to sequentially face the needle and each side of the substrate to sequentially supply the second resin to each side, or A needle having a square ring-shaped opening is used, and the second resin is simultaneously supplied with the opening facing each side of the substrate.
【００４５】なお、第１の樹脂５ａとしては、樹脂層５
として形成された状態でチップ・基板の材質の違い（ヤ
ング率、熱膨脹率など）から生じる内部応力によりチッ
プ・基板相互の接続部が劣化することを緩和する性質を
持ち、かつ、チップ・基板間への充填時にチップ・基板
間へ入り込める径（例えば２５μｍ以下）のフィラーを
含むものを選択することが望ましい。The resin layer 5 is used as the first resin 5a.
In the state of being formed as a chip, it has the property of alleviating the deterioration of the connection part between the chip and the substrate due to the internal stress caused by the difference in the material of the chip and the substrate (Young's modulus, coefficient of thermal expansion, etc.). It is desirable to select a material containing a filler having a diameter (for example, 25 μm or less) that can enter the space between the chip and the substrate during filling.
【００４６】また、第２の樹脂５ｂとしては、光の透過
を防ぐ例えば黒色樹脂や機械的衝撃を吸収する性質を有
するものを選択することが望ましい。即ち、上記実施例
の方法においては、封止用樹脂を充填する際、配線基板
上の前記チップ・基板間の開口部に第１の樹脂を供給
し、チップ・基板間における第１の樹脂樹脂の毛細管現
象を利用して上記チップ・基板間に第１の樹脂を充填
し、上記第１の樹脂を硬化させた後、さらに、上記第１
の樹脂上で前記半導体チップの外周側面部から配線基板
上面の外周縁部にかけて第２の樹脂を供給した後、上記
第２の樹脂を硬化させることにより、片面樹脂封止型パ
ッケージ構造を有する半導体装置を完成させる。Further, as the second resin 5b, it is desirable to select, for example, a black resin which prevents transmission of light or a resin which has a property of absorbing mechanical shock. That is, in the method of the above-described embodiment, when the sealing resin is filled, the first resin is supplied to the opening between the chip and the substrate on the wiring board, and the first resin resin between the chip and the substrate is supplied. After the first resin is filled between the chip and the substrate by utilizing the capillary phenomenon of (1) and the first resin is cured, the first resin is further
After the second resin is supplied on the resin from the outer peripheral side surface of the semiconductor chip to the outer peripheral edge of the upper surface of the wiring board, the second resin is cured to form a semiconductor having a single-sided resin-sealed package structure. Complete the device.
【００４７】これにより、チップ・基板間に樹脂を充填
すると共に、チップの外周側面上縁部から基板上面の外
周縁部までを覆った状態のフィレットを、チップの各外
周側面部にほぼ均等な理想の形状を有するように形成す
ることが可能になる。As a result, the fillet is filled between the chip and the substrate, and the fillet covering from the upper edge of the outer peripheral side surface of the chip to the outer peripheral edge of the upper surface of the substrate is evenly distributed over each outer peripheral side surface of the chip. It can be formed to have an ideal shape.
【００４８】この際、樹脂供給工程を２回に分けている
ので、ニードルから１回で吐き出す樹脂量を増やす必要
がなくなり、チップ外縁・基板外縁間の距離Ｓ３が微小
の場合でも、従来と同様のディスペンサと使用樹脂の性
質に見合った口径を有するニードルを使用でき、ニード
ルから吐き出した樹脂がチップ上面に乗り上げたり基板
端面から垂れ下がったりしてパッケージの仕上がり寸法
のばらつきや外観上の不具合が生じるおそれがなくな
る。従って、半導体装置の一層の小型化を図り、製造上
の歩留り、信頼性を向上させ、コストダウンを図ること
が可能になる。At this time, since the resin supply step is divided into two, it is not necessary to increase the amount of resin discharged from the needle once, and even when the distance S3 between the chip outer edge and the substrate outer edge is small, the same as in the conventional case. It is possible to use a dispenser and a needle that has a diameter that matches the properties of the resin used, and the resin discharged from the needle may run onto the top surface of the chip or hang down from the edge of the board, causing variations in the finished dimensions of the package and appearance defects. Disappears. Therefore, it is possible to further reduce the size of the semiconductor device, improve the manufacturing yield and reliability, and reduce the cost.
【００４９】また、上記したように形成された片面樹脂
封止型パッケージ構造を有する半導体装置は、チップと
基板とを固定するための樹脂層が、チップ・基板間に充
填されると共にチップの外周側面上縁部から基板上面の
外周縁部までを覆い、チップの各外周側面部にほぼ均等
なフィレットを有するように形成されている。Further, in the semiconductor device having the single-sided resin-sealed package structure formed as described above, the resin layer for fixing the chip and the substrate is filled between the chip and the substrate and the outer periphery of the chip is formed. The chip is formed so as to cover from the upper edge portion of the side surface to the outer peripheral edge portion of the upper surface of the substrate and to have substantially uniform fillets on each outer peripheral side surface portion of the chip.
【００５０】従って、チップと基板とが機械的に強固に
固定されており、熱などによる内部応力の他に機械的応
力などからも保護されるので、ベア・チップが外部の環
境や衝撃などの影響を受け難くなり、半導体装置の信頼
性が向上する。Therefore, the chip and the substrate are mechanically firmly fixed to each other and protected from mechanical stress as well as internal stress due to heat, so that the bare chip is protected from external environment and impact. It is less likely to be affected and the reliability of the semiconductor device is improved.
【００５１】なお、第１の樹脂および第２の樹脂とし
て、各工程の目的に応じてそれぞれ適切な性質を有する
ものを使用すればよく、異なる性質の樹脂あるいは同じ
性質の樹脂を使用してもよく、それぞれの硬化は順次あ
るいは同時に行うようにしてもよい。As the first resin and the second resin, those having appropriate properties depending on the purpose of each step may be used, and resins having different properties or resins having the same properties may be used. Of course, each curing may be performed sequentially or simultaneously.
【００５２】即ち、第１の樹脂および第２の樹脂として
同じ樹脂を使用した場合には、前記第１の樹脂供給工程
の後、引き続き（第１の樹脂を硬化させる前に）第２の
樹脂供給工程を行った後に第２の樹脂を前記第１の樹脂
と共に硬化させるようにしてもよい。That is, when the same resin is used as the first resin and the second resin, the second resin is continuously (before curing the first resin) after the first resin supplying step. The second resin may be cured together with the first resin after the supply step is performed.
【００５３】また、第１の樹脂および第２の樹脂として
異なる樹脂あるいは同じ樹脂を使用した場合に、第１の
樹脂供給工程後に第１の樹脂を少し硬化させた状態（仮
キュア状態）で第２の樹脂供給工程を行った後に第２の
樹脂を前記第１の樹脂と共に硬化させるようにしてもよ
い。When different resins or the same resin are used as the first resin and the second resin, the first resin is slightly cured after the first resin supplying step (temporary cure state). The second resin may be cured together with the first resin after performing the second resin supply step.
【００５４】また、上記実施例では、第１の樹脂を供給
する際、基板の一辺部上にのみ供給したが、基板の直交
する二辺部上にそれぞれ供給するようにしてもよく、さ
らには、基板の四辺部上にそれぞれ供給するようにして
もよい。In the above embodiment, when the first resin is supplied, it is supplied only on one side of the substrate. However, it may be supplied on two sides of the substrate orthogonal to each other. , May be supplied to the four sides of the substrate, respectively.
【００５５】また、前記チップ・基板間に充填させた樹
脂を硬化させる際、チップ・基板に荷重を加えてチップ
のバンプ電極と基板の接続パッドとの位置ずれを防ぎな
がら樹脂を硬化させることが望ましい。When the resin filled between the chip and the substrate is cured, the resin may be cured while applying a load to the chip and the substrate to prevent the bump electrodes of the chip from being displaced from the connection pads of the substrate. desirable.
【００５６】また、基板として、その一主面上の外周縁
端部にベタ型配線パターンを形成したものを用意すれ
ば、前記フリップチップボンディングを行う際に、前記
ベタ型配線パターンによる補強的な作用により、配線基
板の割れや反りなどの発生が抑制され、完成品の歩留り
が良くなり、完成品をメモリカードなどに組み込んだ場
合に耐ノイズ性も良好になる。また、前記バンプ電極
を、チップ側ではなく基板側に形成してもよい。If a solid wiring pattern is formed on the outer peripheral edge of one main surface of the substrate, it is possible to reinforce the solid wiring pattern when performing the flip chip bonding. By the action, the generation of cracks or warpage of the wiring board is suppressed, the yield of the finished product is improved, and the noise resistance is also improved when the finished product is incorporated into a memory card or the like. Further, the bump electrodes may be formed on the substrate side instead of the chip side.
【００５７】なお、基板およびチップは、外形が正方形
のものに限らず、長方形のものを用いてもよい。また、
基板は、アルミナ系、窒化アルミ系のものに限らず、樹
脂系のもの（ＢＴレジン基板など）を用いてもよい。ま
た、基板は、図４に示したように、配線および外部接続
用端子が基板から突出する状態で形成されているものに
限らず、図５に示したように、配線および外部接続用端
子が基板に対してほぼ同一平面を成すように埋め込まれ
ているもの（例えばアルミナ系の絶縁基材に対してグリ
ーンシート法により形成されたものとか、樹脂系の絶縁
基材に対してプリプレグ法により形成されたもの）を用
いてもよい。また、基板は、ブラインドビアホールを介
して上下面が電気的に接続されているものや多層構造の
ものを用いてもよい。The substrate and the chips are not limited to having a square outer shape, but may have a rectangular outer shape. Also,
The substrate is not limited to an alumina-based or aluminum nitride-based substrate, and a resin-based substrate (BT resin substrate or the like) may be used. Further, the substrate is not limited to one in which the wiring and the external connection terminal are formed so as to project from the substrate as shown in FIG. 4, and the wiring and the external connection terminal are not provided as shown in FIG. Those embedded so as to form substantially the same plane with the substrate (for example, those formed by a green sheet method on an alumina-based insulating base material, or formed by a prepreg method on a resin-based insulating base material) Those that have been used) may be used. Further, the substrate may have a structure in which the upper and lower surfaces are electrically connected via a blind via hole or a multilayer structure.
【００５８】また、チップを基板上にフリップチップボ
ンディングする際、前記実施例のように接続パッドにバ
ンプ電極の少なくとも先端部を埋め込むように圧入する
方法に限らず、前記特願平６−５０７５７号に詳細に記
載されているように、例えば金の接続パッドと金のバン
プ電極との間で固相拡散を起こさせて接合させるように
してもよい。Further, when the chip is flip-chip bonded onto the substrate, the method is not limited to the method of press-fitting so that at least the tip of the bump electrode is embedded in the connection pad as in the above-mentioned embodiment, but the above-mentioned Japanese Patent Application No. 6-50757. As described in detail in Section 1), for example, solid phase diffusion may occur between the gold connection pad and the gold bump electrode so as to be joined.
【００５９】[0059]
【発明の効果】上述したように本発明の半導体装置によ
れば、樹脂によりベア・チップ側面の上縁部まで完全に
は封止され、ベア・チップが外部の環境や衝撃などの影
響を受け難く、信頼性の高い片面樹脂封止型パッケージ
構造を実現することができる。また、本発明の半導体装
置の製造方法によれば、片面樹脂封止型パッケージ構造
を有する半導体装置を製造する際に、チップ外縁・基板
外縁間の距離が微小の場合でも、ニードルから１回で吐
き出す樹脂量を増やさずに、チップと配線基板とを固定
すると共にチップの外周側面上縁部から配線基板上面の
外周縁部までを覆う樹脂層を形成でき、信頼性が高く一
層の小型化を図る半導体装置を実現することができる。As described above, according to the semiconductor device of the present invention, the resin is completely sealed up to the upper edge of the side surface of the bare chip, and the bare chip is not affected by the external environment or impact. It is possible to realize a difficult and highly reliable single-sided resin-sealed package structure. Further, according to the method of manufacturing a semiconductor device of the present invention, when a semiconductor device having a single-sided resin-sealed package structure is manufactured, even if the distance between the chip outer edge and the substrate outer edge is small, it is possible to use only once from the needle. It is possible to fix the chip and the wiring board without increasing the amount of resin discharged and to form a resin layer that covers from the upper edge of the outer peripheral side surface of the chip to the outer peripheral edge of the upper surface of the wiring board, resulting in high reliability and further miniaturization. It is possible to realize the intended semiconductor device.
【図１】本発明の半導体装置の製造方法の一実施例に係
る樹脂封止工程の一例を概略的に示す図。FIG. 1 is a diagram schematically showing an example of a resin sealing step according to an embodiment of a method for manufacturing a semiconductor device of the present invention.
【図２】図１の工程に対応する樹脂の封止状態を示す上
面図。FIG. 2 is a top view showing a sealed state of resin corresponding to the process of FIG.
【図３】図１の工程により形成された半導体装置の一例
を示す断面図。3 is a cross-sectional view showing an example of a semiconductor device formed by the process of FIG.
【図４】先願に係る片面樹脂封止型パッケージ構造の一
例を示す断面図。FIG. 4 is a sectional view showing an example of a single-sided resin-sealed package structure according to the prior application.
【図５】他の先願に係る片面樹脂封止型パッケージ構造
の一例を示す断面図。FIG. 5 is a sectional view showing an example of a single-sided resin-sealed package structure according to another prior application.
【図６】図４および図５中の樹脂層の形成工程を示す
図。FIG. 6 is a diagram showing a step of forming a resin layer in FIGS. 4 and 5;
１…配線基板、１ａ…配線、１ｂ…被接続部（接続パッ
ド）、２…半導体チップ、２ａ…バンプ電極、３…スル
ーホール配線、４…外部接続用端子、５…樹脂層、５ａ
…第１の樹脂、５ｂ…第２の樹脂、Ｓ３…チップ外縁・
基板外縁間の距離。DESCRIPTION OF SYMBOLS 1 ... Wiring board, 1a ... Wiring, 1b ... Connected part (connection pad), 2 ... Semiconductor chip, 2a ... Bump electrode, 3 ... Through hole wiring, 4 ... External connection terminal, 5 ... Resin layer, 5a
... first resin, 5b ... second resin, S3 ... chip outer edge
The distance between the outer edges of the board.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/12 23/29 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 23/12 23/29 23/31
Claims (6)
線基板と、上記配線基板の一主面にフェースダウン型に
実装された半導体チップと、上記半導体チップと配線基
板との間に充填されると共に上記半導体チップの外周側
面上縁部から前記配線基板上面の外周縁部までを覆い、
上記半導体チップの各外周側面部にほぼ均等なフィレッ
トを有するように形成された樹脂層と、前記配線基板の
他の主面側に導出・露出され、前記半導体チップに電気
的に接続された外部接続用端子とを具備することを特徴
とする半導体装置。1. A wiring board having a wiring including a connected portion on one main surface, a semiconductor chip mounted face down on the one main surface of the wiring board, and between the semiconductor chip and the wiring board. While being filled, covers from the outer peripheral side upper edge of the semiconductor chip to the outer peripheral edge of the wiring board upper surface,
A resin layer formed so as to have a substantially uniform fillet on each outer peripheral side surface of the semiconductor chip, and an external portion that is led out / exposed to the other main surface side of the wiring board and electrically connected to the semiconductor chip. A semiconductor device comprising a connecting terminal.
主面に外部接続用端子を導出・露出させた配線基板の被
接続部とこれに対応する半導体チップの電極端子部の位
置が対向するように半導体チップを配置する工程と、上
記配線基板の被接続部とこれに対応する半導体チップの
電極端子部を固定接続する工程と、この後、上記半導体
チップと配線基板とを固定すると共に上記半導体チップ
を封止するための樹脂層を形成する工程と、上記充填し
た封止用樹脂を硬化させる工程とを具備し、前記チップ
封止用の樹脂層を形成する際、前記配線基板上の前記チ
ップ・基板間の開口部に第１の樹脂を供給し、チップ・
基板間における第１の樹脂の毛細管現象を利用して上記
チップ・基板間に第１の樹脂を充填する第１の樹脂供給
工程と、上記工程により充填した第１の樹脂を硬化させ
た後あるいは硬化させる前に上記第１の樹脂上で前記半
導体チップの外周側面部から前記配線基板上面の外周縁
部にかけて第２の樹脂を供給する第２の樹脂供給工程
と、上記工程により供給した第２の樹脂を単独であるい
は前記第１の樹脂と共に硬化させる樹脂硬化工程とを具
備することを特徴とする半導体装置の製造方法。2. A connected portion of a wiring board having wirings including a connected portion on one main surface and external connection terminals led out and exposed on the other main surface, and an electrode terminal portion of a semiconductor chip corresponding to the connected portion. The step of arranging the semiconductor chip so that the positions of the semiconductor chips face each other, the step of fixedly connecting the connected part of the wiring board and the electrode terminal part of the semiconductor chip corresponding thereto, and then the semiconductor chip and the wiring board A step of forming a resin layer for sealing the semiconductor chip together with fixing, and a step of curing the filled sealing resin, when forming the chip sealing resin layer, The first resin is supplied to the opening between the chip and the substrate on the wiring board,
After the first resin supplying step of filling the first resin between the chips and the substrate by utilizing the capillary phenomenon of the first resin between the substrates and after curing the first resin filled by the above step, or A second resin supply step of supplying a second resin on the first resin from the outer peripheral side surface portion of the semiconductor chip to the outer peripheral edge portion of the upper surface of the wiring board before curing, and a second resin supply step performed by the above step. And a resin hardening step of hardening the resin alone or together with the first resin.
おいて、前記第１の樹脂および第２の樹脂として異なる
性質を有するものを使用し、それぞれを順次に硬化させ
ることを特徴とする半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 2, wherein the first resin and the second resin having different properties are used, and the first resin and the second resin are sequentially cured. Manufacturing method.
おいて、前記第１の樹脂および第２の樹脂として同じ性
質を有するものを使用し、それぞれを同時に硬化させる
ことを特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 2, wherein the first resin and the second resin having the same properties are used and they are simultaneously cured. Production method.
半導体装置の製造方法において、前記第２の樹脂供給工
程は、樹脂供給装置を回転させ、あるいは前記配線基板
を移動させることにより、上記樹脂供給装置と上記配線
基板の各辺部とを順次対向させて前記第２の樹脂を上記
配線基板の各辺部に順次供給することを特徴とする半導
体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 2, wherein in the second resin supplying step, the resin supplying device is rotated or the wiring board is moved. A method of manufacturing a semiconductor device, wherein the resin supply device and the side portions of the wiring board are sequentially opposed to each other, and the second resin is sequentially supplied to the side portions of the wiring board.
半導体装置の製造方法において、前記第２の樹脂供給工
程は、リング状の開口部を有する樹脂供給装置を使用
し、上記樹脂供給装置の開口部を上記配線基板の各辺部
に対向させて前記第２の樹脂を同時に供給することを特
徴とする半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 2, wherein the second resin supplying step uses a resin supplying device having a ring-shaped opening, A method of manufacturing a semiconductor device, characterized in that an opening of a supply device is opposed to each side of the wiring board and the second resin is supplied at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29522994A JPH08153830A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29522994A JPH08153830A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08153830A true JPH08153830A (en) | 1996-06-11 |
Family
ID=17817888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29522994A Pending JPH08153830A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08153830A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056104A (en) * | 1996-06-24 | 1998-02-24 | Internatl Business Mach Corp <Ibm> | Semiconductor device package and method for assembling the same |
| JPH11251343A (en) * | 1998-02-27 | 1999-09-17 | Nec Corp | Resin sealing structure for device and sealing method |
| JP2000164610A (en) * | 1998-11-30 | 2000-06-16 | Ngk Spark Plug Co Ltd | Semiconductor device and its manufacture |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| JP2002538625A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Process for underfilling a controlled collapse chip connection (C4) integrated circuit package having an underfill material partially heated to a gel state |
| JP2002538624A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Process line for underfilling controlled collapse chip connection (C4) integrated circuit packages |
| DE102004009056A1 (en) * | 2004-02-23 | 2005-09-22 | Infineon Technologies Ag | Semiconductor device with a rewiring substrate and method of making the same |
| JP2006128488A (en) * | 2004-10-29 | 2006-05-18 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| JP2008103450A (en) * | 2006-10-18 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Method for manufacturing module |
| JP2008177617A (en) * | 2008-04-09 | 2008-07-31 | Sharp Corp | Semiconductor device and manufacturing method therefor |
| JP2009049115A (en) * | 2007-08-17 | 2009-03-05 | Seiko Epson Corp | Semiconductor device, and manufacturing method thereof |
| JP2010003879A (en) * | 2008-06-20 | 2010-01-07 | Fujitsu Ltd | Semiconductor device and its method of manufacturing |
| US7768136B2 (en) | 2005-02-02 | 2010-08-03 | Sharp Kabushiki Kaisha | Sealed-by-resin type semiconductor device |
| JP2012244034A (en) * | 2011-05-23 | 2012-12-10 | Panasonic Corp | Mounting structure of semiconductor package component and manufacturing method thereof |
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-
1994
- 1994-11-29 JP JP29522994A patent/JPH08153830A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056104A (en) * | 1996-06-24 | 1998-02-24 | Internatl Business Mach Corp <Ibm> | Semiconductor device package and method for assembling the same |
| JPH11251343A (en) * | 1998-02-27 | 1999-09-17 | Nec Corp | Resin sealing structure for device and sealing method |
| JP2000164610A (en) * | 1998-11-30 | 2000-06-16 | Ngk Spark Plug Co Ltd | Semiconductor device and its manufacture |
| JP2002538624A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Process line for underfilling controlled collapse chip connection (C4) integrated circuit packages |
| US6238948B1 (en) | 1999-03-03 | 2001-05-29 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material |
| JP2002538625A (en) * | 1999-03-03 | 2002-11-12 | インテル・コーポレーション | Process for underfilling a controlled collapse chip connection (C4) integrated circuit package having an underfill material partially heated to a gel state |
| JP2002540593A (en) * | 1999-03-03 | 2002-11-26 | インテル・コーポレーション | Controlled Collapsed Chip Connection (C4) Integrated Circuit Package with Filler Encapsulating Underfill Material |
| US6528345B1 (en) | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| DE102004009056B4 (en) * | 2004-02-23 | 2010-04-22 | Infineon Technologies Ag | A method of manufacturing a semiconductor module from a plurality of stackable semiconductor devices having a redistribution substrate |
| DE102004009056A1 (en) * | 2004-02-23 | 2005-09-22 | Infineon Technologies Ag | Semiconductor device with a rewiring substrate and method of making the same |
| US8624372B2 (en) | 2004-02-23 | 2014-01-07 | Infineon Technologies Ag | Semiconductor component comprising an interposer substrate |
| JP2006128488A (en) * | 2004-10-29 | 2006-05-18 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| JP4737370B2 (en) * | 2004-10-29 | 2011-07-27 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US7768136B2 (en) | 2005-02-02 | 2010-08-03 | Sharp Kabushiki Kaisha | Sealed-by-resin type semiconductor device |
| JP4752717B2 (en) * | 2006-10-18 | 2011-08-17 | パナソニック株式会社 | Module manufacturing method |
| JP2008103450A (en) * | 2006-10-18 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Method for manufacturing module |
| JP2009049115A (en) * | 2007-08-17 | 2009-03-05 | Seiko Epson Corp | Semiconductor device, and manufacturing method thereof |
| JP2008177617A (en) * | 2008-04-09 | 2008-07-31 | Sharp Corp | Semiconductor device and manufacturing method therefor |
| JP2010003879A (en) * | 2008-06-20 | 2010-01-07 | Fujitsu Ltd | Semiconductor device and its method of manufacturing |
| JP2012244034A (en) * | 2011-05-23 | 2012-12-10 | Panasonic Corp | Mounting structure of semiconductor package component and manufacturing method thereof |
| JP2018195673A (en) * | 2017-05-16 | 2018-12-06 | 富士通株式会社 | Bump and forming method thereof, and substrate |
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