JPH08153707A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- JPH08153707A JPH08153707A JP6294396A JP29439694A JPH08153707A JP H08153707 A JPH08153707 A JP H08153707A JP 6294396 A JP6294396 A JP 6294396A JP 29439694 A JP29439694 A JP 29439694A JP H08153707 A JPH08153707 A JP H08153707A
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- gas
- film
- electrode
- semiconductor device
- manufacturing
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- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に微細加工後の貴金属の表面処理に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a surface treatment of a noble metal after fine processing.
【0002】[0002]
【従来の技術】近年、ルチル構造を有す代表的な導電性
酸化物(RuO2 ,IrO2 ,OsO2 ,RhO2 )や
白金をキャパシタ電極材料として応用したマイクロエレ
クトロニクスデバイス(例えば、ダイナミックランダム
アクセスメモリ(DRAM)やエフラム(FRAM))
の研究開発が著しい進展を見せている。このマイクロデ
バイスの製造には、前記導電性酸化物及び白金の成膜技
術、微細加工技術などプロセス技術の開発が不可欠であ
る。 2. Description of the Related Art In recent years, typical conductive oxides having a rutile structure (RuO 2 , IrO 2 , OsO 2 , RhO 2 ) and platinum are used as capacitor electrode materials for microelectronic devices (for example, dynamic random access). Memory (DRAM) and Efram (FRAM))
R & D is making significant progress. In order to manufacture this microdevice, development of process technology such as film forming technology and fine processing technology of the conductive oxide and platinum is indispensable.
【0003】前記導電性酸化物のうち、RuO2 をドラ
イエッチングする技術を本発明者はすでに提案してい
る。図5を用いて、この技術を説明する。シリコン基板
1上にシリコン酸化膜2を成膜する。次に、前記シリコ
ン酸化膜2上にスパッタリング法により窒化チタン膜3
を成膜する。さらに酸素ガスを用いた反応性スパッタリ
ッグ法を用いて、前記窒化チタン膜3上にRuO2 膜4
を成膜する。次に、エッチングマスクとなるシリコン酸
化膜5を成膜し、前記シリコン酸化膜5上に感光性レジ
ストを塗布及び現像することで微細レジストパターン6
が得られる(図5(a)参照)。The present inventor has already proposed a technique of dry etching RuO 2 among the conductive oxides. This technique will be described with reference to FIG. A silicon oxide film 2 is formed on a silicon substrate 1. Next, a titanium nitride film 3 is formed on the silicon oxide film 2 by a sputtering method.
To form a film. Further, a RuO 2 film 4 is formed on the titanium nitride film 3 by using a reactive sputter rig method using oxygen gas.
To form a film. Next, a silicon oxide film 5 serving as an etching mask is formed, and a fine resist pattern 6 is formed by applying and developing a photosensitive resist on the silicon oxide film 5.
Is obtained (see FIG. 5 (a)).
【0004】まず、ECR(Electron Cyc
lotron Resonance)プラズマドライエ
ッチング装置を用いて、シリコン酸化膜5をドライエッ
チングする。用いたエッチングガスはCHF3 である
(図5(b))。そして、前記エッチングされたシリコ
ン酸化膜5をエッチングマスクに用いて、RuO2 膜4
を酸素と塩素の混合ガス(塩素の混合比率は最大で75
%まで有効)で前記ドライエッチング装置を用いエッチ
ングする(図5(c)参照)。引き続き、不必要になっ
たシリコン酸化膜5をCHF3 ガスを用いてエッチバッ
クにより除去する(図5(d)参照)。最後に、エッチ
ングされたRuO2 膜4をエッチングマスクに用いて、
窒化チタン膜3を塩素ガスでエッチングすることで微細
パターン7が形成される(図5(e)参照)。First, ECR (Electron Cyc)
The silicon oxide film 5 is dry-etched using a plasma dry etching apparatus. The etching gas used is CHF 3 (FIG. 5B). Then, using the etched silicon oxide film 5 as an etching mask, the RuO 2 film 4 is formed.
Is a mixed gas of oxygen and chlorine (the maximum mixing ratio of chlorine is 75
% Effective) and etching is performed using the dry etching apparatus (see FIG. 5C). Subsequently, the unnecessary silicon oxide film 5 is removed by etchback using CHF 3 gas (see FIG. 5D). Finally, using the etched RuO 2 film 4 as an etching mask,
The fine pattern 7 is formed by etching the titanium nitride film 3 with chlorine gas (see FIG. 5E).
【0005】上記技術では、シリコン酸化膜5のエッチ
バック工程以降で、微細パターン7の表面はプラズマに
曝されることになる。その結果、前記微細パターン7の
表面はエッチングガス中の元素(炭素、ハロゲン元素
等)で汚染される。In the above technique, the surface of the fine pattern 7 is exposed to plasma after the step of etching back the silicon oxide film 5. As a result, the surface of the fine pattern 7 is contaminated with elements (carbon, halogen elements, etc.) in the etching gas.
【0006】図6は微細パターン7形成後の表面状態
を、マイクローオージェ分析器で観察した結果を示した
ものである。表面には、塩素、フッ素、炭素によって汚
染されていることがわかる。この汚染された状態で電子
デバイスを形成すれば、そのデバイスの電気特性及びそ
の長期信頼性は著しく劣化する可能性が高い。FIG. 6 shows the result of observing the surface condition after the formation of the fine pattern 7 with a micro-Auger analyzer. It can be seen that the surface is contaminated with chlorine, fluorine and carbon. If an electronic device is formed in this contaminated state, the electrical characteristics of the device and its long-term reliability are likely to be significantly deteriorated.
【0007】すなわち、電子デバイスの電気特性及びそ
の長期信頼性を得るには、微細パターン7表面はドライ
エッチングによる微細加工後も電極材料成膜時と同等も
しくはそれに極めて近い状態になっている必要がある。That is, in order to obtain the electrical characteristics of the electronic device and its long-term reliability, the surface of the fine pattern 7 must be in a state equal to or extremely close to that at the time of forming the electrode material even after fine processing by dry etching. is there.
【0008】[0008]
【発明が解決しようとする課題】従来の半導体装置の製
造方法では、ドライエッチングにより白金や導電性酸化
物の微細パターンを形成する過程で、電極材料表面に炭
素及びハロゲン元素等による汚染が生じる。この汚染は
電子デバイスの電気特性及びその長期信頼性に著しく悪
影響を与える。In the conventional method of manufacturing a semiconductor device, the surface of the electrode material is contaminated by carbon and halogen elements in the process of forming a fine pattern of platinum or a conductive oxide by dry etching. This contamination seriously affects the electrical properties of electronic devices and their long-term reliability.
【0009】本発明は、この汚染を除去し且つ電極表面
状態を電極材料成膜時と同等、もしくはそれに極めて近
付けることを特徴とする表面処理方法を含んだ半導体装
置の製造方法を提供することにある。The present invention provides a method for manufacturing a semiconductor device including a surface treatment method which removes this contamination and brings the surface condition of the electrode to be equal to or extremely close to that at the time of forming the electrode material. is there.
【0010】[0010]
【課題を解決するための手段】前記目的を達成するた
め、本発明は、白金や導電性酸化物を含む半導体装置の
製造方法において、特に炭素又はハロゲン元素を含むガ
スを用いてドライエッチングによる微細パターン形成
後、ドライエッチングで生じた電極表面の汚染を除去す
るため、引き続き酸素ガス、オゾンガス、水蒸気ガス、
窒素酸化物ガスのうち少なくとも一種類以上のガスを選
択し、プラズマにより前記材料の表面を処理する工程を
含むことを特徴とする。In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device containing platinum or a conductive oxide, and in particular, fine etching by dry etching using a gas containing carbon or a halogen element. After the pattern formation, in order to remove the contamination of the electrode surface caused by dry etching, oxygen gas, ozone gas, steam gas,
It is characterized by including a step of treating at least one kind of gas among nitrogen oxide gas and treating the surface of the material with plasma.
【0011】[0011]
【作用】本発明の原理について説明する。ドライエッチ
ングによる電極の微細加工時点で、電極表面には汚染層
が形成される。この汚染層は、主に、ドライエッチング
に用いたハロゲンガスやフロロカーボンガスを構成する
元素から成る。この汚染層に対して、プラズマ放電によ
り生成された活性化状態の酸素原子及び分子は、汚染層
と化学反応する。予想される化学反応式は、以下の通り
である。The principle of the present invention will be described. At the time of fine processing of the electrode by dry etching, a contamination layer is formed on the surface of the electrode. This contaminated layer is mainly composed of elements that constitute the halogen gas and fluorocarbon gas used for dry etching. Activated oxygen atoms and molecules generated by the plasma discharge chemically react with the contaminated layer. The expected chemical reaction formula is as follows.
【0012】O+C→CO (1) O+F→OF (2) O+X→OF (3) (3)式に於いて、Xはフッ素以外のハロゲン元素を表
す。上式より、フロロカーボンは活性酸素原子と反応し
て、一酸化炭素やフッ化酸素となり除去される。また、
他のハロゲン元素は飽和蒸気圧の高い酸化ハロゲン化物
となって、容易に除去することができる。O + C → CO (1) O + F → OF (2) O + X → OF (3) In the formula (3), X represents a halogen element other than fluorine. According to the above formula, the fluorocarbon reacts with the active oxygen atom to become carbon monoxide or oxygen fluoride and is removed. Also,
Other halogen elements become oxidized halides having a high saturated vapor pressure and can be easily removed.
【0013】[0013]
【実施例】以下、本発明の実施例につき説明する。図1
は本発明の一実施例を示す工程断面図である。EXAMPLES Examples of the present invention will be described below. FIG.
FIG. 3 is a process sectional view showing an embodiment of the present invention.
【0014】シリコン基板11を熱酸化してシリコン酸
化膜12を400nmの膜厚に成膜する。次に、前記シ
リコン酸化膜12上にDCマグネトロンスパッタリング
法によりTiN膜13を50nmの膜厚に成膜する。さ
らに酸素ガスを用いた反応性のDCマグネトロンスパッ
タリング法を用いて、前記TiN膜13上にRuO2膜
14を500nmの膜厚に成膜する。次に、エッチング
マスクとなる有機シリカから成るSOG(Spin o
n Glass)膜15を塗布し320nmの膜厚に成
膜し、前記SOG膜15上に感光性レジストを塗布及び
光リソグラフィー装置で感光及び現像することで微細レ
ジストパターン16を得る(図1(a)参照)。The silicon substrate 11 is thermally oxidized to form a silicon oxide film 12 having a film thickness of 400 nm. Next, a TiN film 13 having a film thickness of 50 nm is formed on the silicon oxide film 12 by a DC magnetron sputtering method. Further, a RuO 2 film 14 having a film thickness of 500 nm is formed on the TiN film 13 by using a reactive DC magnetron sputtering method using oxygen gas. Next, SOG (Spin o
(n glass) film 15 is applied to form a film having a thickness of 320 nm, and a fine resist pattern 16 is obtained by applying a photosensitive resist on the SOG film 15 and exposing and developing it with an optical lithography apparatus (see FIG. )reference).
【0015】次に、SOG膜15をECRプラズマドラ
イエッチング装置でドライエッチングする。用いたドラ
イエッチング条件は、エッチングガスCHF3 を20s
ccmの流量に設定し、圧力を10mTorrに保っ
た。プラズマ生成のため2.45GHzのマイクロ波電
力を760Wを印加し、さらに被エッチング基板に対す
るプラズマ中のインオン運動エネルギーを所望の値に制
御するため、被エッチング基板を支える下部電極に2M
Hzの高周波電力を15W印加した。エッチング時間は
66秒とした(図1(b)参照)。引き続き、前記エッ
チングされたSOG膜15をエッチングマスクに用い
て、RuO2 膜14を酸素と塩素の混合ガスでエッチン
グする。その際のエッチング条件は、ガス層流量200
sccm、塩素混合率10%,圧力15mTorr,マ
イクロ波220W,高周波150W,エッチング時間2
08秒である(図1(c)参照)。RuO2 膜14のエ
ッチング終了後、不必要になったSOG膜15をCHF
3 ガスを用いてエッチバック法により除去する。エッチ
バック条件は前記のSOG膜エッチング条件と同等とし
た(図1(d)参照)。その後、微細パターンに形成さ
れたRuO2 膜14をエッチングマスクに用いて、Ti
N膜13を塩素ガスでエッチングする。エッチング条件
は、塩素ガス流量100sccm,圧力15mTor
r,マイクロ波電極220W,高周波電力50Wとし
た。その結果、図1(e)に示すような異方性の微細パ
ターンが得られると同時に、微細パターン表面は塩素、
フッ素及び炭素を含む汚染層17で覆われた。Next, the SOG film 15 is dry-etched by an ECR plasma dry etching apparatus. The dry etching conditions used were etching gas CHF 3 for 20 s.
The flow rate was set to ccm and the pressure was kept at 10 mTorr. Microwave power of 2.45 GHz is applied at 760 W for plasma generation, and in order to control the in-on kinetic energy in the plasma with respect to the substrate to be etched to a desired value, 2 M is applied to the lower electrode supporting the substrate to be etched.
15 W of high frequency power of Hz was applied. The etching time was 66 seconds (see FIG. 1 (b)). Subsequently, the RuO 2 film 14 is etched with a mixed gas of oxygen and chlorine using the etched SOG film 15 as an etching mask. At that time, the etching condition is a gas layer flow rate of 200.
sccm, chlorine mixing rate 10%, pressure 15 mTorr, microwave 220 W, high frequency 150 W, etching time 2
It is 08 seconds (see FIG. 1 (c)). After etching the RuO 2 film 14, the unnecessary SOG film 15 is removed by CHF.
It is removed by an etch-back method using 3 gases. The etch back conditions were the same as the SOG film etching conditions described above (see FIG. 1D). Then, using the RuO 2 film 14 formed in the fine pattern as an etching mask, Ti
The N film 13 is etched with chlorine gas. Etching conditions are: chlorine gas flow rate 100 sccm, pressure 15 mTorr
r, the microwave electrode 220W, and the high frequency power 50W. As a result, an anisotropic fine pattern as shown in FIG. 1 (e) is obtained, and at the same time, the fine pattern surface has chlorine,
It was covered with a contamination layer 17 containing fluorine and carbon.
【0016】次に、前記汚染層17の除去を行うことを
目的として、すでに微細パターンが形成されている基板
を前記ECRエッチング装置から表面処理装置へ大気に
曝すことなしに搬送した。前記表面処理装置は数Tor
rから数十Torrの圧力下で酸素ガスを導入し、2.
45GHzのマイクロ波を用いたマイクロ波放電を利用
することで酸素プラズマを生成することができる。そし
てプラズマ生成領域と基板との間に金属グリッドを設
け、金属グリッドを電気的に接地することにより、荷電
粒子の基板への流入を防ぎ活性化された酸素原子及び分
子のみが表面処理に寄与できるような構造となってい
る。このようなプラズマは一般にダウンストリームプラ
ズマと称される。表面処理条件は酸素ガス流量を400
sccm、圧力を3Torr、マイクロ波を660W、
基板加熱温度を150℃、表面処理時間を180秒とし
た。かくして、汚染層が取り除かれたパターンが得られ
る(図1(f))。Next, for the purpose of removing the contaminated layer 17, the substrate on which the fine pattern was already formed was transferred from the ECR etching apparatus to the surface processing apparatus without being exposed to the atmosphere. The surface treatment device is several Tor
1. Introduce oxygen gas under a pressure of several tens to several Torr, and 2.
Oxygen plasma can be generated by utilizing microwave discharge using a microwave of 45 GHz. Further, by providing a metal grid between the plasma generation region and the substrate and electrically grounding the metal grid, it is possible to prevent charged particles from flowing into the substrate and only activated oxygen atoms and molecules can contribute to the surface treatment. It has a structure like this. Such plasma is generally called a downstream plasma. The surface treatment conditions are oxygen gas flow rate of 400
sccm, pressure 3 Torr, microwave 660W,
The substrate heating temperature was 150 ° C. and the surface treatment time was 180 seconds. Thus, a pattern with the contaminated layer removed is obtained (FIG. 1 (f)).
【0017】図2は、前記表面処理を施した後の微細パ
ターンの表面をマイクロオージェ分析器を用いて観察し
た結果を示したものである。汚染層は完全に除去され、
表面状態はRuO2 膜の成膜時に近い状態、すなわちR
uとOの組成比がほぼ1対2になっている。FIG. 2 shows the result of observing the surface of the fine pattern after the surface treatment using a micro Auger analyzer. The contaminated layer is completely removed,
The surface condition is close to that at the time of forming the RuO 2 film, that is, R
The composition ratio of u and O is approximately 1: 2.
【0018】なお、蒸気の実施例では表面処理装置とし
てダウンストリームプラズマを用いた例を延べたが、本
発明は、表面処理装置として容量結合型のプラズマ装
置、誘電結合型のプラズマ装置、ECRプラズマ装置、
ヘリコン波プラズマ装置などを用いても有効である。ま
た、酸素ガスの代わりにオゾンガス、水蒸気、窒素酸化
物ガス等を用いても有効である。さらに、被エッチング
材料としてRuO2 の例を延べたが、本発明は、被エッ
チング材料としてルテニウム、イリジウム及びその酸化
物、オスミウム及びその酸化物、ロジウム及びその酸化
物、そして白金をアロゲン元素を含むガスを用いたプラ
ズマでドライエッチングした後の表面処理に対しても有
効である。すなわち、蒸気各実施例の構成は端に例示で
あり、本発明の半導体装置の製造方法は、蒸気実施例の
構成から様々の修正及び変更を加えた半導体装置の製造
方法を含む。In the steam embodiment, the example in which the downstream plasma is used as the surface treatment apparatus has been extended, but the present invention is not limited to the capacitive coupling type plasma apparatus, the inductive coupling type plasma apparatus, and the ECR plasma as the surface treatment apparatus. apparatus,
It is also effective to use a helicon wave plasma device or the like. Also, it is effective to use ozone gas, water vapor, nitrogen oxide gas, or the like instead of oxygen gas. Further, although the example of RuO 2 as the material to be etched has been extended, the present invention includes ruthenium, iridium and its oxide, osmium and its oxide, rhodium and its oxide, and platinum as the material to be etched, and an allogen element. It is also effective for surface treatment after dry etching with plasma using gas. That is, the configuration of each steam embodiment is merely an example, and the semiconductor device manufacturing method of the present invention includes a semiconductor device manufacturing method in which various modifications and changes are made to the configuration of the steam embodiment.
【0019】図3は本発明の方法により得られた薄膜キ
ャパシタを示す。101は抵抗率が0.01Ωcmのn
型シリコン基板、102は層間絶縁膜のシリコン酸化膜
(500nm)、103は導電体層としてのリンをドー
ピンクしたポリシリコン、104はバリアメタルとして
のRuO2 (500nm)/TiN(50nm)、10
5は誘電体膜としてのSrTiO3 (100nm)、1
06は導電体としてのAl(1μm)/TiN(50n
m)である。シリコン基板101を熱酸化してシリコン
酸化膜102を形成し、所望の位置にコンタクトを開口
し、CVD法によりポリシリコン104を1μm成膜し
てリンを拡散し、塩素ガスを用いたプラズマによるエッ
チバックを行ってコンタクトを埋め込んだ。FIG. 3 shows a thin film capacitor obtained by the method of the present invention. 101 is n having a resistivity of 0.01 Ωcm
Type silicon substrate, 102 is a silicon oxide film (500 nm) of an interlayer insulating film, 103 is polysilicon doped with phosphorus as a conductor layer, 104 is RuO 2 (500 nm) / TiN (50 nm) as a barrier metal, 10
5 is SrTiO 3 (100 nm) as a dielectric film, 1
06 is Al (1 μm) / TiN (50 n as a conductor)
m). The silicon substrate 101 is thermally oxidized to form a silicon oxide film 102, a contact is opened at a desired position, polysilicon 104 is formed to a thickness of 1 μm by a CVD method, phosphorus is diffused, and etching is performed by plasma using chlorine gas. I went back and buried the contact.
【0020】しかる後に、バリアメタルとしてRuO2
/TiN105をDCマグネトロンスパッタ法により成
膜し、図1の実施例に延べた塩素と酸素の混合ガスプラ
ズマにより所望の大きさに加工し、その後酸素プラズマ
による表面処理を行った。つづいてCVD法により基板
温度450℃でSrTiO3 105を100nm成膜
し、続いてDCマグネトロンスパッタ法によりAl/T
iN106を成膜しCL2 ガスプラズマを用いて所望の
大きさに加工した。After that, RuO 2 was used as a barrier metal.
/ TiN105 was formed into a film by the DC magnetron sputtering method, processed into a desired size by the mixed gas plasma of chlorine and oxygen expanded in the example of FIG. 1, and then surface-treated with oxygen plasma. Subsequently, SrTiO 3 105 having a film thickness of 100 nm is formed at a substrate temperature of 450 ° C. by a CVD method, and then Al / T is formed by a DC magnetron sputtering method.
A film of iN106 was formed and processed into a desired size using CL 2 gas plasma.
【0021】図4は本発明の表面処理を行ったキャパシ
タと従来の何も処理を行なわないキャパシタの電流−電
圧特性を比較した図である。従来のキャパシタは低電界
においてリーク電流値が大きかった。これは塩素、フッ
素及び炭素などの汚染層が原因と考えられる。FIG. 4 is a diagram comparing the current-voltage characteristics of the surface-treated capacitor of the present invention and the conventional capacitor not subjected to any treatment. The conventional capacitor has a large leak current value in a low electric field. This is considered to be caused by a contaminated layer such as chlorine, fluorine and carbon.
【0022】一方、本発明の薄膜キャパシタはリーク電
流特性も小さく、長期信頼性も従来のキャパシタよりも
優れていることがわかった。On the other hand, it has been found that the thin film capacitor of the present invention has a small leakage current characteristic and is superior in long-term reliability to the conventional capacitor.
【0023】なお、上記の実施例では高誘電率膜として
SrTiO3 の例を延べたが、本発明は、高誘電率膜と
して化学式がABO3 で表され、それぞれAとしてB
a,Sr,Pb,La,Li,Kのうち少なくとも1種
以上、BとしてZr,Ti,Ta,Nb,Mg,Mn,
Fe,Zn,Wのうち少なくとも1種以上からなるも
の、例えば、(Ba,Sr)TiO3 ,PbTiO3 ,
Pb(Zr,Ti)O3 ,(Pb,La)(Zr,T
i)O3 ,Pb(Mg,Nb)O3 ,Pb(Mg,W)
O3 ,Pb(Zn,Nb)O3 ,LiTaO3 ,LiN
bO3 ,KTaO3 ,KHbO3 など、あるいはそれ以
外の化学式の、Ta2 O5 ,Bi4 Ti3 O12,BaM
gF4 などを用いても有効である。また、バリアメタル
としてRuO2/TiNの例を延べたが、本発明はTi
Nの変わりにTiやTa,TaN,ZrNなどのバリア
層あるいはそれらの積層構造を用いても有効である。ま
た、本発明はRuO2 の代わりにルテニウム、イリジウ
ム及びその酸化物、オスミウム及びその酸化物、ロジウ
ム及びその酸化物、そして白金を用いた構造においても
有効である。さらに上記の実施例では表面処理装置とし
てダウンストリームプラズマを用いた例を延べたが、本
発明は、表面処理装置として容量結合型のプラズマ装
置、誘導結合型のプラズマ装置、ECRプラズマ装置、
ヘリコン波プラズマ装置などを用いても有効である。加
えて、酸素ガスの代わりにオゾンガス、水蒸気、窒素酸
化物ガス等を用いても有効である。すなわち、上記各実
施例の構成は単に例示であり、本発明の半導体装置の製
造方法は、上記実施例の構成から様々の修正及び変更を
加えた半導体装置の製造方法を含む。In the above embodiment, SrTiO3 is used as the high dielectric constant film. In the present invention, the chemical formula of the high dielectric constant film is represented by ABO 3 , and A is B
at least one of a, Sr, Pb, La, Li and K, and B as Zr, Ti, Ta, Nb, Mg, Mn,
Fe, Zn, those comprising at least one or more of W, for example, (Ba, Sr) TiO3, PbTiO 3,
Pb (Zr, Ti) O 3 , (Pb, La) (Zr, T
i) O 3 , Pb (Mg, Nb) O 3 , Pb (Mg, W)
O 3 , Pb (Zn, Nb) O 3 , LiTaO 3 , LiN
bO 3 , KTaO 3 , KHbO 3, etc., or other chemical formulas such as Ta 2 O 5 , Bi 4 Ti 3 O 12 , BaM
It is also effective to use gF 4 or the like. The example of RuO2 / TiN as the barrier metal has been extended.
It is also effective to use a barrier layer such as Ti, Ta, TaN, ZrN or a laminated structure thereof instead of N. The present invention is also effective in a structure using ruthenium, iridium and its oxide, osmium and its oxide, rhodium and its oxide, and platinum instead of RuO 2 . Furthermore, in the above-mentioned embodiment, the example in which the downstream plasma is used as the surface treatment apparatus has been extended. However, the present invention provides a capacitively coupled plasma apparatus, an inductively coupled plasma apparatus, an ECR plasma apparatus as the surface treatment apparatus,
It is also effective to use a helicon wave plasma device or the like. In addition, it is effective to use ozone gas, water vapor, nitrogen oxide gas or the like instead of oxygen gas. That is, the configurations of the above-described embodiments are merely examples, and the semiconductor device manufacturing method of the present invention includes a semiconductor device manufacturing method in which various modifications and changes are added to the configurations of the above-described embodiments.
【0024】[0024]
【発明の効果】以上説明したように、本発明を用いれ
ば、ドライエッチングによる白金や導電性酸化物の微細
パターン形成過程で生じる、電極材料表面の炭素及びハ
ロゲン元素等による汚染に対し、この汚染を除去し電極
表面状態を電極材料成膜時の状態に近付け、且つ電子デ
バイスの電気特性及びその長期信頼性を損なうことのな
い、半導体装置の製造方法を提供することができる。As described above, according to the present invention, the contamination of carbon and halogen elements on the surface of the electrode material caused by the fine pattern formation of platinum or the conductive oxide by dry etching is contaminated with this contamination. It is possible to provide a method for manufacturing a semiconductor device in which the electrode surface state is made closer to the state at the time of film formation of the electrode material, and the electrical characteristics of the electronic device and its long-term reliability are not impaired.
【図1】本発明の一実施例を示す工程断面図。FIG. 1 is a process sectional view showing an embodiment of the present invention.
【図2】図1の方法によって得られたパターンのマイク
ロオージェ分析器で得られた電極材料表面の組成図。FIG. 2 is a composition diagram of an electrode material surface obtained by a micro-Auger analyzer having a pattern obtained by the method of FIG.
【図3】図1の方法を用いて形成した薄膜キャパシタの
断面図。3 is a cross-sectional view of a thin film capacitor formed using the method of FIG.
【図4】図3のキャパシタと従来のキャパシタの電圧−
電流特性図。4 is a voltage of the capacitor of FIG. 3 and a conventional capacitor-
Current characteristic diagram.
【図5】従来例の工程断面図。FIG. 5 is a process sectional view of a conventional example.
【図6】図5のパターンのマイクロオージェ分析器で得
られた組成図。6 is a composition diagram obtained by the micro-Auger analyzer having the pattern of FIG.
1,11,101 シリコン基板 2,5,12,102 シリコン酸化膜 3,13 TiN膜 4,14 RuO2 膜 15 SOG膜 6,16 微細レジストパターン 7 微細パターン 17 汚染層 103 リンをドーピングしたポリシリコン 104 バリアメタルRuO2 /TiN 105 SrTiO3 膜 106 Al/TiON膜1, 11, 101 Silicon substrate 2, 5, 12, 102 Silicon oxide film 3,13 TiN film 4,14 RuO 2 film 15 SOG film 6,16 Fine resist pattern 7 Fine pattern 17 Contaminated layer 103 Phosphorus-doped polysilicon 104 Barrier metal RuO 2 / TiN 105 SrTiO 3 film 106 Al / TiON film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/10 451 27/108 21/8242 H01L 27/04 C 7735−4M 27/10 651 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H01L 27/10 451 27/108 21/8242 H01L 27/04 C 7735-4M 27/10 651
Claims (8)
少なくとも一種類以上を含む電極を選択的にドライエッ
チングする工程と、引き続き酸素ガス、オゾンガス、水
蒸気ガス、窒素化物ガスのうち少なくとも一種類以上の
ガスを用いて、前記電極の表面を処理する工程とを含む
ことを特徴とする半導体装置の製造方法。1. A step of selectively dry etching an electrode containing at least one or more of ruthenium and ruthenium oxide, followed by at least one or more gas of oxygen gas, ozone gas, water vapor gas and nitride gas. And a step of treating the surface of the electrode.
ち、少なくとも一種類以上を含む電極を選択的にドライ
エッチングする工程と、引き続き酸素ガス、オゾンガ
ス、水蒸気ガス、窒素酸化物ガスのうち少なくとも一種
類以上のガスを用いて、該電極の表面を処理する工程と
を含むことを特徴とする半導体装置の製造方法。2. A step of selectively dry etching an electrode containing at least one or more of iridium and iridium oxide, followed by at least one or more of oxygen gas, ozone gas, water vapor gas, and nitrogen oxide gas. A step of treating the surface of the electrode with a gas, the method for manufacturing a semiconductor device.
ち、少なくとも一種類以上を含む電極を選択的にドライ
エッチングにする工程と、引き続き酸素ガス、オゾンガ
ス、水蒸気ガス、窒素酸化物ガスのうち少なくとも一種
類以上のガスを用いて、該電極の表面を処理する工程と
を含むことを特徴とする半導体装置の製造方法。3. A step of selectively dry-etching an electrode containing at least one or more of osmium and osmium oxide, followed by at least one or more of oxygen gas, ozone gas, water vapor gas, and nitrogen oxide gas. And a step of treating the surface of the electrode with the gas described above.
なくとも一種類以上を含む電極を選択的にドラインエッ
チングする工程と、引き続き酸素ガス、オゾンガス、水
蒸気ガス、窒素酸化物ガスのうち少なくとも一種類以上
のガスを用いて、該電極の表面を処理する工程とを含む
ことを特徴とする半導体装置の製造方法。4. A step of selectively dry etching an electrode containing at least one or more of rhodium and rhodium oxide, followed by at least one or more of oxygen gas, ozone gas, water vapor gas and nitrogen oxide gas. A step of treating the surface of the electrode with a gas, the method for manufacturing a semiconductor device.
ングする工程と、引き続き酸素ガス、オゾンガス、水蒸
気ガス、窒素酸化物ガスのうち少なくとも一種類以上の
ガスを用いて、該電極の表面を処理する工程とを含むこ
とを特徴とする半導体装置の製造方法。5. A step of selectively dry etching an electrode containing platinum, followed by treating the surface of the electrode with at least one gas selected from oxygen gas, ozone gas, water vapor gas and nitrogen oxide gas. A method of manufacturing a semiconductor device, comprising:
面処理方法にプラズマを用いてことを特徴とする半導体
装置の製造方法。6. A method of manufacturing a semiconductor device, wherein plasma is used in the surface treatment method according to claim 1, 2, 3, 4 or 5.
含まないガスを用い残った電極の表面を処理することを
特徴とする半導体装置の製造方法。7. A method of manufacturing a semiconductor device, which comprises treating the surface of the remaining electrode with a gas containing neither carbon nor halogen element.
する半導体装置の製造方法に置いて、前記キャパシタ素
子の下部電極上に該高誘電率膜を形成する直前に、少な
くとも1回以上、前記下部電極の表面を酸素原子を含
み、かつ炭素及びハロゲン元素を含まないガスを用いた
プラズマにさらし、それに引き続いて前記高誘電率膜を
成長することを特徴とする半導体装置の製造方法。8. A method of manufacturing a semiconductor device having a capacitor element using a high dielectric constant film, wherein at least once or more immediately before forming the high dielectric constant film on the lower electrode of the capacitor element. A method for manufacturing a semiconductor device, comprising exposing the surface of a lower electrode to plasma using a gas containing oxygen atoms and not containing carbon and halogen elements, and subsequently growing the high dielectric constant film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP6294396A JPH08153707A (en) | 1994-11-29 | 1994-11-29 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6294396A JPH08153707A (en) | 1994-11-29 | 1994-11-29 | Manufacturing method for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08153707A true JPH08153707A (en) | 1996-06-11 |
Family
ID=17807199
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6294396A Pending JPH08153707A (en) | 1994-11-29 | 1994-11-29 | Manufacturing method for semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JPH08153707A (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0823726A1 (en) * | 1996-08-05 | 1998-02-11 | Siemens Aktiengesellschaft | Process for plasma enhanced anisotropic etching of metals, metal oxides and their mixtures |
FR2755297A1 (en) * | 1996-10-28 | 1998-04-30 | Samsung Electronics Co Ltd | METHOD FOR FORMING A MULTILAYER WIRING IN A SEMICONDUCTOR COMPONENT |
JPH10189885A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Ferroelectric memory element and its manufacture |
JPH11163271A (en) * | 1997-11-28 | 1999-06-18 | Rohm Co Ltd | Manufacture of capacitor |
JPH11224936A (en) * | 1997-11-05 | 1999-08-17 | Internatl Business Mach Corp <Ibm> | Manufacture method for noble metal oxide and structure formed from the noble metal oxide |
US6046490A (en) * | 1998-08-10 | 2000-04-04 | Matsushita Electronics Corporation | Semiconductor device having a capacitor dielectric element and wiring layers |
KR20000028631A (en) * | 1998-10-05 | 2000-05-25 | 가나이 쓰도무 | Semiconductor integrated circuit device and fabrication thereof |
US6100100A (en) * | 1996-06-18 | 2000-08-08 | Matsushita Electronics Corporation | Method for manufacturing capacitor element |
US6232131B1 (en) | 1998-06-24 | 2001-05-15 | Matsushita Electronics Corporation | Method for manufacturing semiconductor device with ferroelectric capacitors including multiple annealing steps |
US6326218B1 (en) | 1998-12-11 | 2001-12-04 | Hitachi, Ltd. | Semiconductor integrated circuit and its manufacturing method |
JP2001339053A (en) * | 2000-05-29 | 2001-12-07 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
US6607988B2 (en) * | 1999-12-28 | 2003-08-19 | Hitachi, Ltd. | Manufacturing method of semiconductor integrated circuit device |
US6790786B2 (en) * | 2002-03-05 | 2004-09-14 | Micron Technology, Inc. | Etching processes for integrated circuit manufacturing including methods of forming capacitors |
JP2011134966A (en) * | 2009-12-25 | 2011-07-07 | Fujitsu Semiconductor Ltd | Method of manufacturing semiconductor device |
JP2019054238A (en) * | 2017-09-12 | 2019-04-04 | パナソニックIpマネジメント株式会社 | Capacitance element, image sensor, and manufacturing method of capacitance element |
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JPH06151383A (en) * | 1992-11-12 | 1994-05-31 | Mitsubishi Electric Corp | Method of etching high-permittivity multicomponent oxide film and refractory metal film, manufacture of thin-film capacitor, and plasma apparatus for film formation |
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JPH0274006A (en) * | 1988-09-09 | 1990-03-14 | Matsushita Electric Ind Co Ltd | Etching method for ruthenium oxide thin film |
JPH06151383A (en) * | 1992-11-12 | 1994-05-31 | Mitsubishi Electric Corp | Method of etching high-permittivity multicomponent oxide film and refractory metal film, manufacture of thin-film capacitor, and plasma apparatus for film formation |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100100A (en) * | 1996-06-18 | 2000-08-08 | Matsushita Electronics Corporation | Method for manufacturing capacitor element |
EP0823726A1 (en) * | 1996-08-05 | 1998-02-11 | Siemens Aktiengesellschaft | Process for plasma enhanced anisotropic etching of metals, metal oxides and their mixtures |
US6043165A (en) * | 1996-10-28 | 2000-03-28 | Samsung Electronics Co., Ltd. | Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent |
FR2755297A1 (en) * | 1996-10-28 | 1998-04-30 | Samsung Electronics Co Ltd | METHOD FOR FORMING A MULTILAYER WIRING IN A SEMICONDUCTOR COMPONENT |
JPH10189885A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Ferroelectric memory element and its manufacture |
JPH11224936A (en) * | 1997-11-05 | 1999-08-17 | Internatl Business Mach Corp <Ibm> | Manufacture method for noble metal oxide and structure formed from the noble metal oxide |
JPH11163271A (en) * | 1997-11-28 | 1999-06-18 | Rohm Co Ltd | Manufacture of capacitor |
US6232131B1 (en) | 1998-06-24 | 2001-05-15 | Matsushita Electronics Corporation | Method for manufacturing semiconductor device with ferroelectric capacitors including multiple annealing steps |
US6046490A (en) * | 1998-08-10 | 2000-04-04 | Matsushita Electronics Corporation | Semiconductor device having a capacitor dielectric element and wiring layers |
US6432835B1 (en) | 1998-10-05 | 2002-08-13 | Hitachi, Ltd. | Process for fabricating an integrated circuit device having a capacitor with an electrode formed at a high aspect ratio |
KR20000028631A (en) * | 1998-10-05 | 2000-05-25 | 가나이 쓰도무 | Semiconductor integrated circuit device and fabrication thereof |
US6326218B1 (en) | 1998-12-11 | 2001-12-04 | Hitachi, Ltd. | Semiconductor integrated circuit and its manufacturing method |
US6451665B1 (en) | 1998-12-11 | 2002-09-17 | Hitachi, Ltd. | Method of manufacturing a semiconductor integrated circuit |
US6607988B2 (en) * | 1999-12-28 | 2003-08-19 | Hitachi, Ltd. | Manufacturing method of semiconductor integrated circuit device |
JP2001339053A (en) * | 2000-05-29 | 2001-12-07 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
US6790786B2 (en) * | 2002-03-05 | 2004-09-14 | Micron Technology, Inc. | Etching processes for integrated circuit manufacturing including methods of forming capacitors |
JP2011134966A (en) * | 2009-12-25 | 2011-07-07 | Fujitsu Semiconductor Ltd | Method of manufacturing semiconductor device |
JP2019054238A (en) * | 2017-09-12 | 2019-04-04 | パナソニックIpマネジメント株式会社 | Capacitance element, image sensor, and manufacturing method of capacitance element |
WO2020235596A1 (en) * | 2019-05-22 | 2020-11-26 | 東京エレクトロン株式会社 | Film formation method, film formation apparatus, and method for cleaning treatment vessel |
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