JPH08152596A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE: To guarantee the life and display quality of a liquid crystal panel without wasting a current by supplying an optimum current from a bias voltage generating circuit according to the load of the connected liquid crystal panel. CONSTITUTION: This circuit is provided with 1st and 2nd bias voltage generating circuits which are different in current supply quantity and display data and select data, are inputted as serial data to a shift register 21, whose contents are latched by a latch circuit 22, thereby selecting one of the two bias voltage generating circuits according to the latched select data. At this time, the 1st bias voltage generating circuit 34 which is large in current supply quantity when the load of the liquid crystal panel is large or the 2nd bias voltage generating circuit 36 which is small in current supply quantity is selected when the load is small,.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit having a bias voltage supply circuit for driving liquid crystal.

[0002]

2. Description of the Related Art Generally, a liquid crystal drive circuit having a built-in bias voltage generation circuit is constructed by a circuit as shown in FIG. 2, and this figure shows a case of a 1/3 duty / 1/3 bias system. ing. In FIG. 2, 1 is a clock input terminal for inputting a clock signal CL sent from a system controller such as a microcomputer (not shown), 2 is a data input terminal for inputting display data DI sent as serial data from the system controller, 3 is a Display data input to the data input terminal 2 is transferred to the clock input terminal 1
A shift register which takes in based on the clock signal CL inputted to the circuit 4, a latch circuit which latches the contents of the shift register 3 by a latch pulse L from the latch signal generation circuit 5, and a segment driver output waveform control circuit 7 and a segment driver output A segment driver which is composed of a waveform generation circuit 8 and supplies an output waveform from the output terminals 9a, 9b, ...
Reference numeral 10 includes a common driver output waveform control circuit 11 and a common driver output waveform generation circuit 12, and an output terminal 13
It is a common driver that supplies an output waveform from a, 13b, 13c to the common of the liquid crystal panel. Further, 15 is composed of a resistance division circuit composed of three resistors having the same resistance value R1, and is composed of three levels of bias voltages V1 (= VDD),
2, V3 and the ground voltage VSS are bias voltage generation circuits for supplying the segment driver 6 and the common driver 10.

Therefore, when display data and a clock signal are sent from the system controller, the display data is fetched in the shift register 3 in synchronism with the clock, and the latch pulse L causes the display data to be latched when the fetching is completed. Latched in circuit 4. The latched display data is applied to the segment driver output waveform control circuit 7 of the segment driver 6 by 3 bits. Here, four segment drivers corresponding to the display data are synchronized with the timing signal generated from the timing generation circuit 14. An output waveform control signal is generated.

The lines 151, 152, 153, 154 for supplying the bias voltages V1, V2, V3 and the ground voltage VSS of the bias voltage generating circuit 15 are connected to the segment output terminals 9a, 9a, via the four transmission gates 8, respectively. 9b, ..., 9n, the four segment driver output waveform control signals from each segment driver output waveform control circuit 7 are used to control the opening and closing of the four transmission gates 8 to output the segment driver output waveforms. Is formed. Then, the segment driver output waveforms are output terminals 9a, 9b, ...
It is output from n and applied to the liquid crystal panel.

On the other hand, in the common driver 10, each common driver output waveform control circuit 11 generates four common driver output waveform control signals in synchronization with the timing signal generated from the timing generation circuit 14. Bias voltages V1 and V of the bias voltage generation circuit 15
Lines 15 for supplying V2, V3 and ground voltage VSS respectively
1, 152, 153, and 154 are segment drivers 6
In the same manner as in the above case, each of the common output terminals 13a, 13b, 13 is connected via the four transmission gates 12.
The common driver output waveform control circuit 11 controls the opening and closing of the four transmission gates 12 by the four common driver output waveform control signals from each common driver output waveform control circuit 11 to form a common driver output waveform. This common driver output waveform is output to the output terminal 13a,
The signals are output from 13b and 13c and applied to the liquid crystal panel.

With the above operation, three common driver output waveforms COM1 and CO as shown in FIGS.
M2 and COM3 and the segment driver output waveform Sn are formed. As the segment driver output waveform, only the waveform corresponding to the common driver output waveform COM1 is shown. By the way, the segment output terminals 9a,
9b, ..., 9n and common output terminals 13a, 13
When the load of the liquid crystal panel connected to b and 13c is large, the amount of current supplied from these output terminals to the liquid crystal panel increases. In such a case, if the resistance value R1 of the bias generation circuit 15 is large, the common and segment output waveforms are distorted, leading to early deterioration of the liquid crystal panel and deterioration of display quality.

Therefore, conventionally, the resistance value R1 of the bias generation circuit 15 is set small so that the life and the display quality can be guaranteed for all the liquid crystal panels having a small load to a large load. Also, IC
In order to suppress the current consumption of the resistor, as shown in FIG. 3, in the built-in bias voltage generating circuit 16, the resistance value R2 of the resistance dividing circuit is set to be large, and the resistance value of the resistance value R3 is small outside the IC. An external bias voltage generating circuit 17 composed of a dividing circuit can be connected in parallel with the bias voltage generating circuit 16, and in the case of a liquid crystal panel having a large load, the external bias voltage generating circuit 17 is used. There were things.

[0008]

In the circuit shown in FIG.
Since the resistance value R1 of the bias voltage generation circuit 15 is set to be small, the current consumption is large, and therefore, when driving a liquid crystal panel with a small load, there is a problem of wasting current. . In addition, the circuit of FIG. 3 requires an external resistor depending on the liquid crystal panel used, which causes an increase in external components and also causes an external resistor even when the IC stops operating. Since this consumes a current, it is not suitable for lowering the current.

[0009]

SUMMARY OF THE INVENTION The present invention provides a timing generation circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and the timing signal. A common driver that forms a common driver output waveform, a plurality of bias voltage generation circuits that supply a bias voltage for driving the liquid crystal to the segment driver and the common driver, and each supply a different amount of current, and select data. According to the present invention, the above problem is solved by configuring a liquid crystal drive circuit including a selection circuit that selects any one of the plurality of bias voltage generation circuits.

Further, the present invention is characterized by further comprising a shift register for inputting the display data and the selection data, and a latch circuit for latching the contents of the shift register. Furthermore, in the present invention, the display data is input as serial data, and the selection data is data input as a series of serial data together with the display data.

[0011]

In the present invention, only by inputting selection data, a bias voltage generating circuit with a small current supply amount is used for a liquid crystal panel with a small load, and a bias voltage generating circuit with a small current supply amount is used for a liquid crystal panel with a large load. A large bias voltage generation circuit can be used. Further, since the selection data is the display data and a series of serial data, the data input terminal can also be used as the display data, and the circuit configuration such as the shift register and the latch circuit can be handled by only increasing the number of bits.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which all illustrated components are built in an LSI. Further, the same components as those of the conventional example shown in FIGS. Here, the system controller (not shown) sends 1-bit selection data SD as a series of serial data immediately after the display data DI. Therefore, the shift register 21 and the latch circuit 22 are the same as those of the conventional shift register. 3 and latch circuit 4
The number of bits is increased by one bit. Then, in the latch circuit 22, the latch 23 at the final bit position is a latch for selected data.

As for the bias voltage generating circuit, the resistance value R4 of the resistance dividing circuit is set to a small value to increase the current supply amount, and the first bias voltage generating circuit 34 and the resistance value R5 of the resistance dividing circuit are set. Is set to a large value to reduce the current supply amount, and a second bias voltage generating circuit 36 is provided. In each of the bias voltage generating circuits 34 and 36, the first transmission gates 35a and 37a are connected between the power supply potential VDD and the first resistor.
The second transmission gates 35b and 37b are provided between the first voltage dividing point A and the output line 152, and the third transmission gates 35c and 37c are provided between the second voltage dividing point B and the output line 153. Each is inserted. Output line 1
51 and 154 are directly connected to the power supply potentials VDD and VSS of the bias voltage generating circuit 34, respectively.

The output of the latch 23 is input as a control signal to each of the transmission gates 35a, 35b and 35c of the first bias voltage generating circuit 34, and the second gate
Each transmission gate of the bias voltage generation circuit 36
The inverted output of the latch 23 is input as a control signal to the gates 37a, 37b, and 37c. Next, the operation of this embodiment will be described in detail.

Serial data consisting of display data and selection data is input to the data terminal 2 and the clock signal CL
Is input to the clock terminal 1, the shift register 21
The display data and the selection data are fetched in synchronism with the clock. After the fetching, when the latch signal L is applied, the display data and the selection data of the shift register 21 are latched by the latch circuit 22. Specifically, the selection data is latched by the latch 23 in the latch circuit 22.

Now, when the selection data SD is "1", the inverted selection data "0" is input to the second bias voltage generating circuit 36, so that the transmission gate 37
b and 37c are turned off, the bias voltage is not supplied to the output lines 152 and 153, and the transmission gate 37a is turned off, so that no current is generated in the resistance division circuit which constitutes this bias voltage generation circuit. Consumption of will not occur.

On the other hand, in the bias voltage generating circuit 34, all the transmission gates 35a, 35b, 35c are turned on, so that the bias voltages V2, V3 are supplied from the bias voltage generating circuit 34 to the output lines 152, 153, and the outputs are outputted. Lines 151 and 154 have power supply voltages VDD and VSS
Is supplied. In the bias voltage generation circuit 34, since the resistance value R4 is small, a large amount of current is supplied to the segment and common drivers 6 and 10. Therefore, when connecting a liquid crystal panel with a large load, the output waveform is changed. Optimal drive can be performed without distorting. The operations of forming the segment and common output waveforms in the segment and common drivers 6 and 10 are as described in the conventional example.

When the selection data SD is "0",
Since all the three transmission gates 35a, 35b, 35c of the bias voltage generating circuit 34 are turned off, the bias voltage is not supplied from here and the current consumption does not occur. However, the bias voltage generation circuit 36
Then, three transmission gates 37a, 37
Since all of b and 37c are turned on, output lines 152 and 1
Bias voltages V2 and V3 are supplied to 53. In the bias voltage generation circuit 36, since the resistance value R5 is large, only a small amount of current is supplied to the segment and common drivers 6 and 10. Therefore, when connecting a liquid crystal panel with a small load, it is useless. Optimal driving can be performed without consuming a large amount of current.

As described above, the bias voltage generating circuit of the current supply amount can be selected according to the load of the connected liquid crystal panel by the selection data. Next, a second embodiment will be described with reference to FIG. Here, the selection data SD is composed of 2 bits SD1 and SD2.
When both 1 and SD2 are "1", the two bias voltage generating circuits 34 and 36 are selected together, and SD1 and SD2
When "1" is "1,0", only the bias voltage generating circuit 34 is selected, and when SD1 and SD2 are "0,1", only the bias voltage generating circuit 36 is selected.

That is, when the load of the liquid crystal panel to be connected is large, the two bias voltage generating circuits 34 and 36 are connected in parallel between the power supply voltages, so that the resistance value becomes smaller and a larger current is supplied to the liquid crystal. The panel can be supplied. When the load of the liquid crystal panel to be connected is medium, the bias voltage generating circuit 34 can supply an appropriate current, and when the load of the liquid crystal panel to be connected is small, the bias voltage generating circuit 36 consumes unnecessary current. Optimal driving can be performed without

The embodiment described above is an example in which two bias voltage generating circuits are provided, but the number may be increased if necessary, and the number of bits of selected data may be increased accordingly. . Furthermore, the driving method is 1/3
It is naturally applicable not only to the duty / 1/3 bias method but also to other methods.

[0022]

According to the present invention, an optimum amount of current can be supplied from the bias voltage generation circuit according to the load of the liquid crystal panel to be connected, and therefore, no wasted current is consumed.
It is possible to guarantee the life and display quality of the liquid crystal panel. Further, by making the selection data the display data and a series of serial data, it is possible to suppress the increase in the number of terminals and obtain the above-mentioned effect by only a slight circuit change.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a block diagram showing the configuration of another conventional example.

FIG. 4 is a waveform diagram showing common and segment driver output waveforms.

FIG. 5 is a block diagram showing a main part of another embodiment of the present invention.

[Explanation of symbols]

 1 clock input terminal 2 data input terminal 3,21 shift register 4,22 latch circuit 6 segment driver 7 segment driver output waveform control circuit 8 segment driver output waveform generation circuit 9a, 9b, ..., 9n segment output terminal 10 common driver 11 common driver output waveform control circuit 12 common driver output waveform generation circuit 13a, 13b, 13c common output terminal 14 timing generation circuit 15, 16, 17, 34, 36 bias voltage generation circuit 35a, 35b, 35c transmission gate 37a, 37b, 37c transmission gate

Claims (4)

[Claims] 1. A timing generation circuit that generates a timing signal for display control, a segment driver that forms a segment driver output waveform based on display data and the timing signal, and a common driver output waveform that forms in accordance with the timing signal. Common driver, a plurality of bias voltage generating circuits for supplying a bias voltage for driving the liquid crystal to the segment driver and the common driver, and different current supply amounts, and a plurality of bias voltage generating circuits according to selected data. A liquid crystal drive circuit comprising: a selection circuit for selecting one of the circuits. 2. A timing generation circuit that generates a timing signal for display control, a segment driver that forms a segment driver output waveform based on display data and the timing signal, and a common driver output waveform that forms in accordance with the timing signal. Common driver, a plurality of bias voltage generating circuits for supplying a bias voltage for driving the liquid crystal to the segment driver and the common driver, and different current supply amounts, and a plurality of bias voltage generating circuits according to selected data. A liquid crystal drive circuit comprising a selection circuit for selecting one or a plurality of circuits. 3. The liquid crystal drive circuit according to claim 1 or 2,
A liquid crystal drive circuit further comprising a shift register for inputting the display data and the selection data, and a latch circuit for latching the contents of the shift register. 4. The liquid crystal drive circuit according to claim 3, wherein the display data is input as serial data, and the selection data is data input as a series of serial data together with the display data.