JPH08152459A - Semiconductor device and its test method - Google Patents

Abstract

PURPOSE: To obtain a test method in which increase of external terminals for test and in the test time is prevented by a method wherein a circuit means checks whether data inside a memory has been stored erroneously or not. CONSTITUTION: A test control circuit 3 on an IC substrate 31 outputs a control signal to a ROM 2 exclusively used for a test, a serial-parallel conversion circuit 5, a selector 6 and a semiconductor device body 1 on the basis of test data, a control signal and a clock signal which are input from terminals 8, 9. By an address signal from the circuit 3, the ROM 2 outputs stored test data for the body 1 to the selector 6, and it outputs the test data and redundant data for its inspection to an inspection circuit 4. The circuit 5 converts a serial signal for the test data from the circuit 3 into a parallel signal, and the selector 6 selects the test data of either the ROM 2 or the circuit 5 so as to be output to the body 1. At this time, the circuit 4 selects the existence of a fault in the test data by utilizing the redundant data which has been input, and it outputs a result to an external terminal 11. Thereby, it is possible to prevent an increase in an external terminal for a test and in the test time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of testing the same, and more particularly to a semiconductor device having test data stored in a ROM and a method of testing the same.

[0002]

2. Description of the Related Art In order to test whether a semiconductor device having various functions such as a memory and a digital logic circuit integrated on a single semiconductor substrate has a desired function, this semiconductor device is used. There is a method of connecting a tester, inputting predetermined data, comparing the output data with expected value data facilitated in the tester, and determining that they are non-defective if they match.

In addition to this method, test data, test control functions, expected value data, etc. are built in the same semiconductor substrate, and a test is performed by this, and it is not necessary to prepare an external tester. There is a method of conducting a test by significantly reducing the function of.

Japanese Patent Laid-Open No. 58-35545, which is equipped with a circuit of a semiconductor device having test data built in a read-only memory (ROM), which is constructed according to the latter test method.
Referring to FIG. 4 showing the publication, the semiconductor integrated circuit board 30 includes a semiconductor device main body 41 which receives a signal pattern from the outside at an input terminal 47, executes a predetermined signal processing, and outputs the result to an output terminal 53. , A first memory 4 in which a test pattern for the semiconductor device main body 41 is stored in advance.
2 and the device body 41 corresponding to the above test pattern
Second memory 57 in which the output pattern of
And when testing the device body 41, the first memory 4
2 compares the test pattern stored in No. 2 to the device body 41 with the response pattern of the device body 41 to which the test pattern is given and the output pattern stored in the second memory 57. And a comparison circuit 52 for

Here, the first and second memories 42 and 57
Is an address counter 5 which operates by receiving a clock signal.
The data in the memory is read out by the address control by 8. The read test pattern is input to the main body 41 via the multiplexer (MPX) 56. The output pattern read from the second memory 57 is supplied to the comparison circuit 52 and flip-flop (F
F) is compared with the response pattern of the body 41 provided via 55. In this configuration, the clock signal is supplied from the terminal 49, the control signal is supplied from the terminal 48, and the test control circuit 43 supplies a predetermined control signal to each unit. For this reason, it suffices to prepare a signal to be applied to the input terminals 48 and 49 in the tester, and the function in the tester is simplified.

[0006]

However, such a semiconductor device structure is intended to find a defect in the semiconductor device body 41 itself, but the reliability of the determination is poor. This is the first and second memories 4 for testing.
This is because the reliability of the stored data in 2, 57 is about the same as that of the main body 1. For example, the first memory 4
If the data in 2 is defective, the output data of the main body 41 does not match the data in the second memory 57 and is judged as a defective product, but in this case, the semiconductor device main body 41 has no defect. In some cases, it should be judged as a good product. Further, even when the second memory 57 has a defect, a portion which should be determined to be a good product is determined to be a defective product.

Therefore, the reliability of the judgment is extremely poor, and the side of the test, that is, the first and second memories 4 is tested.
The lack of means for finding 2,57 stored data defects is particularly problematic and impractical.

In view of the above problems, the present invention has the following problems. (1) The reliability of the test circuit formed on the same substrate should be considerably higher than the reliability of the main body. (2) Minimize the increase of external terminals (pins) dedicated to the test and improve the compatibility with the terminals of the tester. (3) The circuit configuration should be such that at least double tests can be performed by using different test circuits.
(4) The judgment signal should be an extremely simple output signal. (5) To prevent a meaningless decrease in the manufacturing yield of semiconductor devices. (6) Even if it is found that the test circuit is defective, the semiconductor device body can be tested. (7) Try to shorten the test time. (8) To provide a highly reliable semiconductor device body. (9) When connecting to a tester,
Make sure that the semiconductor device has the role of testing in a good balance so that a complicated interface is not required. (10) If it is desired to change the test items after the semiconductor device is manufactured, it should be configured so that it can be input from the outside immediately.

[0009]

The first structure of the present invention is as follows.
A semiconductor device main body to be tested, a memory storing test data to be supplied to the main body, and a test control circuit for controlling the test data to be read and input to the main body are provided on a semiconductor integrated circuit substrate. In the semiconductor device, circuit means for inspecting whether or not the test data is erroneously stored in the memory is formed on the substrate, and a test data signal from the outside is serially connected in parallel. The circuit means for converting is formed on the substrate.

A second structure of the present invention is, on a semiconductor integrated circuit substrate, a semiconductor device main body to be tested, a memory for storing test data to be supplied to the main body and expected value data obtained from the main body, A semiconductor device including a test control circuit for controlling to read test data and inputting it to the main body, and a matching circuit for collating expected value data obtained from the main body with expected value data stored in the memory. In the above, the circuit means for inspecting the test data in the memory and the expected value data is formed on the substrate, and the circuit means for converting an external test data signal from serial to parallel is provided. It is characterized in that it is formed on a substrate.

Further, in the semiconductor device testing method of the first or second structure of the present invention, erroneous storage of data for inspecting the semiconductor device body is found in the memory built in the semiconductor integrated circuit board. In this case, a part of the test data signal input from the outside is converted from serial to parallel and input to the main body.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing a block diagram of a first embodiment of the present invention, a semiconductor device of this embodiment includes a logic circuit for performing arithmetic processing, a temporary storage memory, a ROM, etc. The semiconductor device main body 1 configured to have the above function, the test-dedicated ROM 2 in which test data necessary for testing the main body 1 is stored, and whether or not the stored data in the ROM 2 is defective is inspected. Inspection circuit 4,
One of the serial-parallel conversion circuit 5 for converting serial test data input from one of the plurality of input terminals 8 into parallel data, and the output of the conversion circuit 5 and the storage data of the test-dedicated ROM 2 Selector 6 for selecting and outputting to main body 1, test control circuit 3 for outputting control signals necessary for performing a series of tests to selector 6, serial-parallel conversion circuit 5, test-only ROM 2, main body 1, etc. Are provided on the semiconductor substrate 31.

Here, the semiconductor device body 1 to be tested
Although it is preferable that all the circuits which operate in the normal mode are included, the circuits in (1) may be limited to the circuits which need to be particularly intensively tested. The input terminal 7 is, for example, 12
When bit data is input, it has 12 lines, and the output terminal 10 also has 12 lines. The control signal generating circuit for functioning the main body 1 is not shown in the normal mode operation, and the test control circuit 3 is used in the test mode operation. The test control circuit 3 is connected to a terminal 9 to which a clock signal is input and a plurality of terminals 8 to which a control signal or test data is input. Whether to input the control signal or the test data is determined by the combination of the input signals of the plurality of terminals 8. When the test data is input, this is output to the serial-parallel conversion circuit 5. When the test data is input from the input terminal 7 during the test (in the second test mode described later), the test data is also input from the input terminal 8 in order to secure the data necessary for the test more quickly. It is input as a serial signal, converted in parallel, and input to the main body 1 via the selector 6. In the normal mode, the test circuit described above is not necessary, so the main unit 1
An interface is prepared to cut the input-output relationship so as not to hinder the operation, but it is not shown. On the contrary, when the test mode is set, the control signal from the test control circuit 3 and the test data from the selector 6 are selected so as to be applied to the main body 1.

Referring now to FIG. 3 showing an example of the inspection circuit 4, this inspection circuit includes, for example, 8-bit data 20.
And 1 parity bit 23 for test ROM
A 9-bit register 24 input from 2 and an exclusive OR of 8 inputs in total (Exclusive O
R) It has a gate 21 and only one output terminal 22.
For example, when the sum of the logical 1s of the 8-bit data 20 is an even number, the parity bit 23 is set to the logical 1 and
When the sum of the logical 1s of the 8-bit data 20 is odd,
The parity bit 23 is set to logic 0 and stored in the test ROM 2 in advance. Therefore, the ROM 2 is stored such that the sum of logic 1 is always an odd number if normal. A logic 1 level is output to the output terminal 22 of the gate of the 2-input EX / OR 21 if normal,
If there is a mistaken storage of 1 bit or the like in the 8-bit data, a logic 0 level is output to the output terminal 22, and this signal can be immediately discriminated by monitoring the output terminal 11. A series of 8
Since the bit data is continuously input to the inspection circuit 4 and the determination result is output, the tester that inspects the output terminal 11 stores a series of determination results and compares them with the address data, so that they are erroneously stored. The memory cell in question can be specified, but if even one bit is erroneously stored, there is no need to specify it if the test ROM 2 is determined to be defective.

As the inspection circuit 4, a circuit as shown in FIG. 3 may be used. In addition to this, a defect is determined by counting logic 1 in 8 bits to determine whether it is an odd number or an even number. May be.

The test-dedicated ROM 2 is the semiconductor device body 1
Test data used for the test and redundant data for the test circuit 4 to check the test data for errors are written, and the test signal is sent to the selector 6 by the address signal supplied from the test control circuit 3. Data and redundant data for inspecting an error in the test data are input to the inspection circuit 4. The test control circuit 3 uses the control signal input from the external terminal 8 and the clock signal input from the external terminal 9 for the test-dedicated ROM 2
Address signal, serial signal of serial-parallel conversion circuit 5, control signal of selector 6, and operation mode of semiconductor device body 1. The inspection circuit 4 uses the redundant data written in the test-dedicated ROM 2 to make the test-dedicated ROM 2
It is inspected whether or not there is an error in the test data written in, and the inspection result is output to the external terminal 11. The serial-parallel conversion circuit 5 converts the serial signal input from the test control circuit 3 into a parallel signal and inputs the parallel signal to the selector 6.
The selector 6 switches between the test data from the test-dedicated ROM 2 and the test data from the serial-parallel conversion circuit 5 in response to a control signal from the test control circuit 3, and inputs the test data to the semiconductor device body 1.

The operation of the semiconductor device body 1 in the test mode is performed by operating the external terminals 8 and 9 to operate the test control circuit 3 and setting the control signal of the semiconductor device body 1 to the test mode. The semiconductor device body 1 is set to the test mode, signal processing is performed by the test data from the selector 6, and the result is output to the external terminal 10.

In the normal test mode, the selector 6 is set by the test control circuit 3 so as to input the test data from the test-dedicated ROM 2 to the semiconductor device body 1.

As a method of testing the semiconductor device of this embodiment,
A first test mode and a second test mode are prepared. First, the first test mode will be described.
The test control circuit 3 sets the address signal of the test-dedicated ROM 2 by the clock signal input from the external terminal 9, inputs the test data to the semiconductor device body 1, and outputs the signal according to the test data written in the test-dedicated ROM 2. Processing is performed and the result is output to the external terminal 10. At this time, the test of the semiconductor device body 1 is determined by whether or not the signal output from the external terminal 10 matches the expected value of the signal processing by the test data provided from the test-dedicated ROM 2. An external terminal 1 for outputting the inspection result of the inspection circuit 4 together with the gap external terminal 10
1 is also monitored to determine whether the test data written in the test ROM 2 has an error. The test control circuit 3 updates the address signal of the test-dedicated ROM 2 by the clock signal input from the external terminal 9 and supplies the test data to the semiconductor device body 1 to sequentially test the semiconductor device body 1.

If no error is found in the test data written in the test-dedicated ROM 2 according to the inspection result of the inspection circuit 4 output to the external terminal 11, the data after the processing of the main body 1 obtained from the output terminal 10 is processed. If the data and the expected value data prepared in the tester are collated and both data match, the semiconductor device 31 is determined as a non-defective product and is a shipping target, but both data do not match. If so, the semiconductor device body 1 is regarded as a defective circuit, and the semiconductor device 31 is discarded. This completes the test in the first test mode.

Next, when a defect is found in the test-dedicated ROM 2, the following test is performed in the second test mode. If an error is found in the test data written in the test-dedicated ROM 2 by the inspection result of the inspection circuit 4 output to the external terminal 11, the test result of that item is invalidated, and the plurality of external terminals 8 are inspected. The test control circuit 3 is set to the second test mode by a specific logic combination. In this case, the selector 6 is set so that the output of the serial-parallel conversion circuit 5 is input to the semiconductor device body 1, and the second test mode in which the test data is input from the outside of the semiconductor device is set. Next, normal test data is transferred from the external terminal 8 through the test control circuit 3 to the serial-parallel conversion circuit 5 as a serial signal and input to the semiconductor device body 1 to perform a test with normal test data. If the data obtained from the output terminal 10 matches the expected value data in the tester, the main body 1 is regarded as a good product,
This semiconductor device is determined to be non-defective. If they do not match, it is determined as a defective product.

In the second test mode, the data required for the test is also input from the input terminal 7 and the terminal 8
The test time is reduced because serial data from is added to this.

Since the inspection circuit 4 is provided, the ROM dedicated to the test is used.
The reliability of the data in 2 is improved, and the reliability of the test in the first test mode performed thereby is improved.

In addition, since the serial-parallel conversion circuit 5 can be used so that the test can be performed in the second test mode when the rescue is not performed in the first test mode, the main body 1 is mistakenly used.
The risk of determining the defect is extremely small, and the manufacturing yield is not reduced.

Further, since the lacking data is input as a serial signal and then converted into a parallel signal, the number of terminals in this portion is only one.

Since the test control function and the test exclusive data storage function are shared by the semiconductor device side, the matching with the tester is good and a complicated interface is not required.

Since a semiconductor device which is determined to be non-defective in the first test mode can be further tested in the second test mode, an extremely reliable semiconductor device main body can be supplied in this case.

Further, since test data can be given from outside the semiconductor device, there is an advantage that test items can be added after the semiconductor device is manufactured.

Referring to FIG. 2 showing a block diagram of the second embodiment of the present invention, the semiconductor integrated circuit substrate 3 of this embodiment is shown.
2 is provided with the coincidence circuit 12 and the ROM 2 dedicated to the test
Since the second embodiment is common to the first embodiment except that expected value data is also stored in the first embodiment, description of common configurations and effects will be omitted.

The inspection circuit 4 inspects not only the test data in the test-dedicated ROM 2 but also expected value data.

The matching circuit 12 compares the expected value data in the test-dedicated ROM 2 with the data output from the main body 1, and outputs a logic 1 or 0 to the output terminal 10 if they match. The coincidence circuit 2 takes, for example, the complement of one data and adds it to the other data,
This is achieved by a circuit in which the added value does not match other than logic 0.

According to this embodiment, it is not necessary to prepare expected value data on the tester side, and it is not necessary to prepare a circuit for inspecting match / mismatch on the tester side, so that the matching property with the tester is better. Becomes

As a means for inspecting the test data written in the test-dedicated ROM 2, there are various means such as a checksum in addition to the parity check shown in FIG.

The arrows in FIGS. 1 and 2 indicate the data flow by a thick line and the control signal flow by a thin line.

[0035]

As described above, according to the present invention, the inspection circuit for inspecting the data of the test-dedicated ROM, the serial-parallel conversion circuit for converting the serial signal supplied from the test control circuit into the parallel signal, etc. are built-in. As a result, it is possible to prevent an increase in external terminals and an increase in test time, and in the case where there is a defect in the test-dedicated ROM built in the semiconductor device, the semiconductor device is provided with test data from outside the semiconductor device. It is possible to obtain an effect such that the main body is tested, and it is possible to prevent the yield of the semiconductor device from being lowered due to the defect of the test-dedicated ROM.

[0036]

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram of an inspection circuit used in FIG. 1 or FIG.

FIG. 4 is a block diagram of a conventional semiconductor device.

[Explanation of symbols]

1,41 Semiconductor device main body 2 Test-only ROM 3,43 Test control circuit 4 Inspection circuit 5 Serial-parallel conversion circuit 6 Selector 7, 8, 9, 10, 11, 11, 13, 22, 47, 48, 4
9, 53, 50 Terminals 12 Matching circuit 20 8-bit data 21 2-input EX / OR gate 23 Parity bit 24 Registers 30, 31, 32 Semiconductor integrated circuit board 42, 57 Memory 52 Comparison circuit 55 Flip-flop 56 Multiplexer (MPX) 58 Address counter

Claims (6)

[Claims] 1. A semiconductor device main body to be tested, a memory storing test data to be given to the main body, and a test control for controlling the test data to be read and input to the main body on a semiconductor integrated circuit substrate. In a semiconductor device including a circuit, circuit means for inspecting whether or not the test data is erroneously stored in the memory is formed on the substrate. 2. The semiconductor device according to claim 1, wherein circuit means for converting an external test data signal from serial to parallel is formed on the substrate. 3. The semiconductor device according to claim 1, wherein redundant data for inspecting the data stored therein is written in the memory. 4. A semiconductor device main body to be tested, a memory storing test data to be given to the main body and expected value data obtained from the main body, and the main body by reading the test data on a semiconductor integrated circuit substrate. In a semiconductor device comprising a test control circuit for controlling to input to the device, and a matching circuit for collating expected value data obtained from the main body with expected value data stored in the memory,
A semiconductor device, wherein circuit means for inspecting test data and expected value data in the memory is formed on the substrate. 5. The semiconductor device according to claim 4, wherein circuit means for converting an external test data signal from serial to parallel is formed on the substrate. 6. When a mistaken storage of data for inspecting the semiconductor device body is found in the memory built in the semiconductor integrated circuit board, a part of a test data signal input from the outside is detected. The serial-to-parallel conversion is performed and input to the main body.
A method for testing a semiconductor device as described above.