JPH08147184A - Emulator - Google Patents

Abstract

PURPOSE: To provide the emulator with which memory access is enabled in the real operation of a user program even with an evaluation chip corresponding to a high-speed microcomputer by providing a parallel access function corresponding to the high-speed control of a memory. CONSTITUTION: This emulator is composed of the evaluation chip equipped with a /PREQ signal 8 and a /PACK signal 9 as signals for synchronization at the time of parallel access and a parallel access control part 18, to which a host CPU can perform access, or the like and this parallel access control part 18 is provided with a parallel access operation control part 23 for performing the synchronization with the evaluation chip corresponding to the /PREQ signal 8 and /PACK signal 9 based on the information transferred from a system bus interface 19 and for performing control to report the timing of parallel access start to the memory and an emulation memory interface control part 20 by making a /START signal 22 active.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator for supporting the development of microcomputer-applied equipment and software, and more particularly to a microcomputer built-in memory mounted in the emulator and an emulation memory acting on behalf of a user memory mounted in the emulator. That can be accessed from other than the microcomputer evaluation chip that substitutes the functions of the microcomputer of the specified user system (hereinafter referred to as parallel access function)
The present invention relates to a technique effective when applied to an emulator having.

[0002]

2. Description of the Related Art For example, in an emulator for supporting development of microcomputer-applied equipment and software, the parallel access function refers to data stored in an emulation memory or the like during execution of a user program without interrupting the user program. , A function used when changing. Generally, the emulator can display and change the contents of the memory while the user program is running.

Here, the outline of the parallel access function will be described with reference to the functional block diagram shown in FIG.

That is, in the parallel access function, during execution of the user program by the evaluation chip,
The parallel control block can respond to an access request to the emulation memory from another CPU or the like without stopping the access cycle to the emulation memory of the evaluation chip.

Further, in a typical 2-state access cycle between the evaluation chip and the emulation memory, as shown in FIG. 5, most conventional evaluation chips have a system clock of 2 clocks and complete one bus cycle. .

Therefore, as shown in the parallel access cycle of FIG. 6, another C is inserted in the bus cycle of the evaluation chip.
The parallel access function is realized by dividing the bus that transfers data between the PU and the emulation memory.

[0007]

By the way, in the parallel access system as described above, the access speed of the memory and the high speed control of the data bus buffer, which can be accessed twice within the bus cycle of the evaluation chip, are required. , The parallel access function based on this bus division is no longer compatible.

In other words, the operating clock of the evaluation chip has become faster year by year, and the number of evaluation chips operating with a bus cycle of one clock has increased. I can no longer follow.

Therefore, in the current parallel access method, the user program is temporarily stopped to access the memory, and there is a problem that the memory cannot be accessed in the actual operation of the user program.

Therefore, an object of the present invention is to realize a parallel access function corresponding to an access speed by high-speed control of a memory, and to perform a memory access in an actual operation of a user program even in an evaluation chip corresponding to a high-speed microcomputer. It is to provide an emulator that can do.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the emulator of the present invention substitutes the function of a microcomputer equipped with an evaluation chip in which there is an empty cycle without external access depending on the flow of program instructions, and enables debugging of a microcomputer application system. In particular, for parallel access control, the evaluation chip is provided with an input signal and an output signal, and the address and data bus signals possessed by the evaluation chip are in a high impedance state during the empty cycle period during which this input signal occurs during the active period. At the same time, the parallel access operation control means for activating the output signal is provided.

Further, without providing an input signal to the evaluation chip, the evaluation chip always puts the address and data bus signals in the evaluation chip into the high impedance state during the empty cycle period, and at the same time, activates the output signal. It is a thing.

Further, in response to an access request from a memory other than the evaluation chip to the microcomputer built-in memory mounted on the emulator and the user side system memory, the address and data bus signals are in a high impedance state. The access destination address, data, and control signal are output during the empty cycle period.

[0016]

According to the emulator described above, as the parallel access function, the evaluation chip is provided with the input signal and the output signal, and further the parallel access operation control means is provided. On the other hand, the input signal is activated for the evaluation chip.

Furthermore, the evaluation chip puts the address and data bus signals into a high impedance state when the input signal is in an empty cycle during the active period, and at the same time, activates the output signal.

Then, after confirming that the output signal is in the active state, the emulator outputs the access destination address to the address bus, and if the access request data from other than the evaluation chip is a read request, fetches the data and writes it. If requested, the data is output to the data bus.

As a result, the evaluation chip can be accessed without pausing, a parallel access function corresponding to the access speed can be realized by high-speed control of the memory, and the evaluation chip compatible with a high-speed microcomputer can be realized. Also, the memory can be accessed in the actual operation of the user program.

Even if the evaluation chip is not provided with an input signal and the address and data bus signals in the evaluation chip are always set to a high impedance during the empty cycle period, the parallel evaluation is performed without suspending the evaluation chip. Can be accessible.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram showing an emulator which is an embodiment of the present invention, FIG. 2 is a block diagram showing a parallel access control unit in this embodiment, and FIG. 3 is an explanatory diagram showing an operation sequence at the time of parallel access. Is.

First, the configuration of the emulator of this embodiment will be described with reference to FIG.

The emulator of the present embodiment substitutes the function of a microcomputer equipped with an evaluation chip in which there is an empty cycle with no external access depending on the flow of program instructions, and enables the debugging of a microcomputer application system. The evaluation chip 1 of the emulation microcomputer having the same function as that of the emulation target microcomputer.

The evaluation chip 1 includes an emulation control unit 3 for controlling emulation operation, a memory 4 used for controlling emulation operation, a break detection circuit 5 for detecting a user program execution stop condition, and an emulation execution via an emulation bus 2. It is connected to a trace memory 6 for acquiring the result and an emulation memory 7 that can be used by allocating it to an arbitrary address of the user system.

The evaluation chip 1 of the emulation microcomputer uses the / PREQ signal (input signal) 8 and / PREQ as synchronization signals for parallel access.
It has an ACK signal (output signal) 9.

The emulation bus 2 is further connected to a microcomputer (not shown) on a user system via a user interface section 10 and a user interface probe 11.

The host CPU 12 controls the entire emulator, and is connected to the system memory 14 and the I / O interface section 15 via the system bus 13. The I / O interface section 15 includes a man-machine interface CRT 16 and a disk 1.
7 is connected.

The host CPU 12 can access the emulation control unit 3, the memory 4, the break detection circuit 5, the trace memory 6, the emulation memory 7, and the parallel access control unit 18, and the evaluation chip 1 is used by the user when executing the emulation. A user program on the system or the emulation memory 7 can be executed.

The parallel access control unit 18, as shown in FIG. 2, is connected to the host CPU 1 via the system bus 13.
2, a system bus interface 19 for performing interface control when performing input / output from the I / O 2, a memory for performing interface control with the emulation bus 2, and a memory for performing I / O control with the memory 4 and the emulation memory 7 on the emulation bus 2; The control unit 20 has an interface function.

Further, the parallel access control unit 18 receives the / P based on the information transferred from the system bus interface 19 through the parallel control unit internal bus 21.
Synchronization with the evaluation chip 1 is performed by the REQ signal 8 and the / PACK signal 9, and the parallel access start timing is determined by the memory and emulation memory interface control unit 2.
A parallel access operation control unit (parallel access operation control means) 23 is provided for controlling the 0 by making the / START signal 22 active.

Next, with respect to the operation of this embodiment, a parallel access sequence will be described with reference to FIG.

First, the evaluation chip 1 is operating in synchronization with the system clock, and the evaluation chip status indicates the operating state of the evaluation chip 1. Further, the master on the emulation bus indicates that it has the bus right of the emulation bus 2, and the evaluation chip in the master on the emulation bus means that the evaluation chip 1 has the bus right of the emulation bus 2. It indicates that

First, the host CPU 12 notifies the parallel access control section 18 of an access request to the emulation memory 7. In response to this, the parallel access operation control unit 23 in the parallel access control unit 18 activates the / PREQ signal 8 for the evaluation chip 1.

Here, the evaluation chip 1 puts the address and data bus signals into a high impedance state when the / PREQ signal 8 is in an empty cycle during the active period, and at the same time, makes the / PACK signal 9 active.

The parallel access operation controller 23
After confirming that the / PACK signal 9 is in the active state, outputs the access destination address to the memory and emulation memory interface control unit 20 on the address bus. If the access request of the host CPU 12 is a read request, Take in. On the other hand, if it is a write request, data is output onto the emulation bus 2 during the parallel access period.

By the above operation, the parallel access function is realized at an access speed of about 1/2 of the memory access required for the parallel access function by the conventional bus division method, and the evaluation is equivalent to that of a high speed microcomputer. Even in the chip 1, parallel access can be realized without interrupting the user program.

Therefore, according to the emulator of this embodiment, since the evaluation chip 1 has the / PREQ signal 8 and the / PACK signal 9, the evaluation chip 1 is evaluated for the empty cycle existing during the active period. The address and data bus signals in the chip 1 are set to a high impedance state during the empty cycle period, and / P is set during the empty cycle period.
By activating the ACK signal 9 and reflecting the parallel access address and data to the emulation bus 2 through the memory and the emulation memory interface control unit 20, the evaluation chip 1 can be accessed without pausing and the user program The memory access can be performed in the actual operation of.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the emulator of this embodiment, the case where the evaluation chip 1 of the emulation microcomputer has the / PREQ signal 8 and the / PACK signal 9 has been described, but the present invention is limited to the above embodiment. Instead, it is applicable to the case of deleting the / PREQ signal.

Also in this case, the evaluation chip always activates the / PACK signal and sets the address and data signals to high impedance during the empty cycle period, and the equivalent parallel access function can be realized even with the specifications of such an evaluation chip. Is.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The evaluation chip is provided with an input signal and an output signal, and during the empty cycle period during which the input signal is generated during the active period, the address and data bus signals in the evaluation chip are set to a high impedance state, and at the same time, By providing the parallel access operation control means that activates the output signal, the emulator outputs the access destination address to the address bus after confirming that the output signal is in the active state, and the access request data from other than the evaluation chip is transmitted. Data can be taken in if a read request and data can be output to the data bus if a write request, so parallel access can be made possible without suspending the evaluation chip.

(2) In the above (1), without providing an input signal to the evaluation chip, the evaluation chip always puts the address and data bus signals in the evaluation chip into a high impedance state during the empty cycle period, and outputs the same. By activating the signal, parallel access can be realized without suspending the evaluation chip as in (1) above.

(3) By the above (1) or (2), the parallel access function corresponding to the access speed by the high speed control of the memory is realized, and the user program is interrupted even in the evaluation chip corresponding to the high speed microcomputer. Without doing so, it is possible to access the memory in the actual operation of the user program.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an emulator that is an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a parallel access control unit in the present embodiment.

FIG. 3 is an explanatory diagram showing an operation sequence during parallel access in this embodiment.

FIG. 4 shows an emulator as an example of conventional technology,
It is a block diagram which shows the outline of a parallel access function.

FIG. 5 shows an emulator, which is an example of conventional technology,
It is explanatory drawing which shows the general bus cycle sequence of an evaluation chip.

FIG. 6 shows an emulator which is an example of conventional technology,
It is explanatory drawing which shows the bus cycle sequence at the time of parallel access.

[Explanation of symbols]

1 Evaluation Chip 2 Emulation Bus 3 Emulation Control Unit 4 Memory 5 Break Detection Circuit 6 Trace Memory 7 Emulation Memory 8 / PREQ Signal (Input Signal) 9 / PACK Signal (Output Signal) 10 User Interface Unit 11 User Interface Probe 12 Host CPU 13 System bus 14 System memory 15 I / O interface section 16 CRT 17 Disk 18 Parallel access control section 19 System bus interface 20 Memory, emulation memory interface control section 21 Parallel control section Internal bus 22 / START signal 23 Parallel access operation control section (parallel Access operation control means)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Ota 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A microcomputer application system, which has a function equivalent to that of a microcomputer mounted in a system and substitutes the function of a microcomputer mounted with an evaluation chip in which an empty cycle without external access exists depending on the flow of program instructions. Of the evaluation chip, wherein the evaluation chip is provided with an input signal and an output signal for parallel access control, and an empty cycle period generated during the active period of the input signal is an address included in the evaluation chip. An emulator comprising parallel access operation control means for activating the output signal at the same time when the data bus signal is in a high impedance state. 2. The evaluation chip, without providing an input signal to the evaluation chip, always puts the address and data bus signals included in the evaluation chip into a high impedance state during an empty cycle period and simultaneously activates the output signal. The emulator according to claim 1, wherein 3. The address for an access request from a memory other than the evaluation chip to a microcomputer built-in memory mounted on the emulator and an emulation memory acting on behalf of a user side system memory,
3. The emulator according to claim 1, wherein the access destination address, data, and control signal are output during an empty cycle period when the data bus signal is in a high impedance state.