JPH08137628A - Disk array device - Google Patents

Abstract

PURPOSE: To realize a disk array device with excellent processing performance. CONSTITUTION: A count register circuit 3 stores a content of a preset frequency divider counter corresponding to each of disk devices 7-1 to 7-5. A rotation synchronization control circuit 1 generates a rotation synchronizing signal for each of the disk devices 7-1 to 7-5 based on an output of an oscillation circuit 2 and a content of the frequency divider counter of the count register circuit 3 and outputs. Each of the disk devices 7-1 to 7-5 performs read and write processing in a timing of the rotation synchronizing signal from the rotation synchronization control circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device, and in particular, it uses a plurality of small and inexpensive magnetic disk devices,
The present invention relates to a disk array device that simultaneously processes these magnetic disk devices in parallel.

[0002]

2. Description of the Related Art Conventionally, in this type of disk array device, "A Case for Redundant" is used.
Arrays of Inexpensive Di
sks (RAID) "(David A. Pattern)
son, Garth Gibson, and Rand
y H. Kats, Technical Report
UCB / CSD 87/391, December 1
987. There are five levels of disk array devices proposed in (1).

The first level (RAID-1) disk array device uses a mirror disk, which is a conventional conventional method. Since the mirror disk uses two data disks that store exactly the same data, the reliability is very high. Further, when reading from the data disk, the one with shorter seek time is accessed, which has an advantage that the access time is shorter than that of a normal disk.

However, since the data must be written to both the data disk and the check disk at the time of writing, the response time becomes slow. Also, only 50% of the entire disc can be used as a data disc.

In the second level (RAID-2) disk array device, a Hamming code used in a memory or the like is used. With conventional discs, it is difficult to know what is wrong with the disc. Therefore, a check disk is required to determine which disk is out of order and which one is out of order.

Therefore, in order to reduce the number of check disks as much as possible, data interleaving is performed on a group of several disks. For example, 4 check disks for 10 disks
5 check disks for 25 disks
You need one.

In the third level (RAID-3) disk array device, one check disk is used, and parity information is written in the check disk. This is because it has become possible to know which disk has a failure by adding an ECC function to the disk. In this case, the exclusive OR of the data on the data disk is calculated, and the result is written as parity information on one check disk.

In the fourth level (RAID-4) disk array apparatus, all disks in the group must be accessed in order to read / write one data in the third level disk array apparatus. On the other hand, by strobing data to the disks in the group by block interleaving, it is possible to process a plurality of data reads / writes at the same time.

In the fifth level (RAID-5) disk array device, the check data fixed on one check disk is distributed to the data disks. When a plurality of write processes come in the fourth-level disk array device, those write processes cannot be processed in parallel because the check disk is fixed, whereas in the fifth-level disk array device, the check process cannot be performed in parallel. By allocating the data in a distributed manner, it is possible to perform parallel processing of a plurality of write processes.

Since the above-mentioned first to third level disk array devices can obtain a high transfer rate by simultaneously accessing all the disks, it is suitable for processing a large amount of data at one time by a super computer or the like. .

However, the first-third level disk array devices are required to access a small amount of data.
Although only a small amount of data is transferred, all the disks are involved and processing efficiency deteriorates.

Therefore, the fifth level disk array device is arranged to disperse the parity data in each disk and to multiplex the read / write processing. Recently, the 5th targeting transaction applications
Level disk array devices are being commercialized.

[0013]

In the above-mentioned conventional fifth level disk array device, the parity data is distributed in each disk device to multiplex the read / write processing. Since it uses an inexpensive small-sized magnetic disk device that does not have a rotation synchronization function, it is a disk array product with poor processing performance.

Therefore, an object of the present invention is to solve the above problems and provide a disk array device having excellent processing performance.

[0015]

DISCLOSURE OF THE INVENTION A disk array device according to the present invention provides a plurality of single disk devices having a rotation synchronization function and a frequency division count value preset for each of the plurality of single disk devices. A holding means for holding and a control means for controlling to output a rotation synchronizing signal to each of the plurality of single disk devices based on the contents of the holding means are provided.

Another disk array device according to the present invention is
In addition to the above configuration, monitoring means for monitoring the data read / write operation for each of the plurality of single disk devices, and each of the plurality of single disk devices held by the holding means according to the monitoring result of the monitoring means And means for varying the frequency division count value corresponding to.

[0017]

The value of the frequency division count preset for each of a plurality of single disk devices having the rotation synchronization function is held in the count register circuit, and the plurality of single disks are stored based on the contents of the count register circuit. The disk drive is controlled to output a rotation synchronizing signal.

Further, by changing the value of the frequency dividing counter corresponding to each of the plurality of single disk devices according to a command from the microprocessor control circuit, while confirming the performance of each of the plurality of single disk devices, the plurality of single disk devices can be confirmed. The timing of the rotation synchronization signal distributed to each device can be changed. Therefore, a disk array device with excellent processing performance is realized.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Referring to the figure, a disk array device according to an embodiment of the present invention includes a rotation synchronization control circuit 1 and an oscillation circuit 2.
A count register circuit 3, a host interface control circuit 4, an array data control circuit 5, disk interface control circuits 6-1 to 6-5, a logical disk device 8, and a microprocessor control circuit 9. ing.

In the rotation synchronization control circuit 1, the oscillation output signal 112 generated in the oscillation circuit 2 and the count held in the count register circuit 3 corresponding to each of the single disk devices 7-1 to 7-5 in the logical disk device 8 are held. Based on the value 113, the rotation synchronization signal 1 to each of the single disk devices 7-1 to 7-5
11-1 to 111-5 are generated and output.

The host interface control circuit 4 controls the host interface 101 connected to a host computer (not shown). The array data control circuit 5 has a read data buffer 5a, a write data buffer 5b, and a read parity buffer 5c, stores data in these buffers, and processes the data.

The array data control circuit 5 is connected to the host interface control circuit 4 via the host data bus 102.
Connected to the array data bus 103-1 to 1-3-5
Through the disk interface control circuits 6-1 to 6-
5 connected to each.

Disk interface control circuit 6-1.
6-5 are disk interfaces 104-1 to 10
Each of the individual disk devices 7-1 to 7-5 is connected to each of the individual disk devices 7-1 to 7-5 of the logical disk device 8 via 4-5 and controls the disk interfaces 104-1 to 104-5. Data is written to and read from.

The microprocessor control circuit 9 is connected to the host interface control circuit 4 and the array data control circuit 5 via the control signal lines 105 and 106, and the control signal line 107.
The disk interface control circuits 6-1 to 6-5 are connected to the count register circuit 3 via -1 to 107-5, respectively. Further, the microprocessor control circuit 9 controls each circuit in the disk array device.

A read operation and a write operation of the disk array device according to the embodiment of the present invention will be described with reference to FIG.

When the host computer issues a data read command to the disk array device through the host interface 101, the microprocessor control circuit 9 detects that the data read command has been transferred to the host interface control circuit 4 through the host interface 101. At the same time, the microprocessor control circuit 9 receives the read start address and the number of read data sectors from the host interface control circuit 4.

The microprocessor control circuit 9 calculates the device numbers of the read single disk devices 7-1 to 7-5 and the read single disk address based on the read start address and the read data sector number from the host interface control circuit 4. .

The microprocessor control circuit 9 determines the array data buses 103-1 to 1-3-3 based on the device numbers of the individual disk devices 7-1 to 7-5 obtained by this calculation.
5 to instruct the array data control circuit 5 to establish a read data path between the host data bus 5 and the host data bus 102.

Next, the microprocessor control circuit 9 determines the device number obtained by calculation from the status information sent from the disk interface control circuits 6-1 to 6-5 through the control signal lines 107-1 to 107-5. It is determined whether the corresponding single disk devices 7-1 to 7-5 are accessible.

When the microprocessor control circuit 9 determines that it is accessible, the control signal lines 107-1 to 10-10.
Disk interface control circuit 6-1 through 7-5
6-5 gives the read start address and the number of read data sectors to the single disk devices 7-1 to 7-5.

In this case, the disk interface control circuits 6-1 to 6-5 use the read single disk addresses sent from the single disk devices 7-1 to 7-5 to read data buffers in the array data control circuit 5. 5a
Further, a read operation from the read data buffer 5a to the host computer is further performed.

If an instruction is sent from the microprocessor control circuit 9 to the disk interface control circuits 6-1 to 6-5 during this operation, the disk interface control circuits 6-1 to 6-5 will issue the instruction. Control signal line 107-
1 to 107-5 through the microprocessor control circuit 9
Send to.

When the individual disk devices 7-1 to 7-5 finish the read operation, the disk interface control circuit 6
-1 to 6-5 send status information indicating that access is possible to the microprocessor control circuit 9 through the control signal lines 107-1 to 107-5, and the data read command operation is completed.

Then, the write operation is performed by the single disk device 7
-1 to 7-5 to read old parity data from the parity data buffer 5c in the array data control circuit 5, from the single disk device 7-1 to 7-5 to the read data buffer 5a in the array data control circuit 5. Read operation of old data, write operation of new data from the host computer to the write data buffer 5b in the array data control circuit 5, result of exclusive OR of old parity data, old data and new data in the above operation Can be decomposed into four operations, that is, an operation of writing in the single disk devices 7-1 to 7-5.

First, in the case of the read operation of the old parity data, the host computer operates the host interface 101.
When a data write command is issued to the disk array device through the, the microprocessor control circuit 9 detects that the data write command has been transferred to the host interface control circuit 4 through the host interface 101. At the same time, the microprocessor control circuit 9 receives the write start address and the number of write data sectors from the host interface control circuit 4.

Based on the write start address and the number of write data sectors from the host interface control circuit 4, the microprocessor control circuit 9 determines the unit numbers and the unit disk addresses of the unit disk units 7-1 to 7-5 in which the old parity data exists. And calculate.

The microprocessor control circuit 9 determines the disk interface control circuit 6-1 based on the device numbers of the individual disk devices 7-1 to 7-5 obtained by this calculation.
6-5 to 6-5 through the control signal lines 107-1 to 107-5 based on the status information, the unit disk devices 7-1 to 7-corresponding to the device numbers obtained by the calculation.
5 determines whether or not it is accessible.

When the microprocessor control circuit 9 determines that it is accessible, the control signal lines 107-1 to 10-10.
Disk interface control circuit 6-1 through 7-5
6-5 gives the read start address and the number of read data sectors to the single disk devices 7-1 to 7-5.

In this case, the disk interface control circuits 6-1 to 6-5 use the read single disk addresses sent from the single disk devices 7-1 to 7-5 to read parity buffers in the array data control circuit 5. 5
Read operation to c is performed.

During this operation, when an instruction is sent from the microprocessor control circuit 9 to the disk interface control circuits 6-1 to 6-5, the disk interface control circuits 6-1 to 6-5 issue the instruction. Control signal line 107-
1 to 107-5 through the microprocessor control circuit 9
Send to.

When the individual disk devices 7-1 to 7-5 finish the read operation, the disk interface control circuit 6
-1 to 6-5 send control information indicating that the microprocessor control circuit 9 can be accessed through the control signal lines 107-1 to 107-5, and complete the old parity read operation.

In the case of the old data read operation, the microprocessor control circuit 9 uses the write start address and the number of write data sectors used in reading the old parity data, and the single disk device 7-1 in which the old data exists is present. The device number of 7-5 and the single disk address are calculated.

The microprocessor control circuit 9 determines the disk interface control circuit 6-1 based on the device numbers of the individual disk devices 7-1 to 7-5 obtained by this calculation.
6-5 to 6-5 through the control signal lines 107-1 to 107-5 based on the status information, the unit disk devices 7-1 to 7-corresponding to the device numbers obtained by the calculation.
5 determines whether or not it is accessible.

When the microprocessor control circuit 9 determines that it is accessible, the control signal lines 107-1 to 10-10.
Disk interface control circuit 6-1 through 7-5
6-5 gives the read start address and the number of read data sectors to the single disk devices 7-1 to 7-5.

In this case, the disk interface control circuits 6-1 to 6-5 send the read data buffers in the array data control circuit 5 from the single disk devices 7-1 to 7-5 based on the read single disk addresses. 5a
Read operation to.

If an instruction is sent from the microprocessor control circuit 9 to the disk interface control circuits 6-1 to 6-5 during this operation, the disk interface control circuits 6-1 to 6-5 will issue the instruction. Control signal line 107-
1 to 107-5 through the microprocessor control circuit 9
Send to.

When the single disk devices 7-1 to 7-5 finish the read operation, the disk interface control circuit 6
-1 to 6-5 send control information indicating that the microprocessor control circuit 9 is accessible through the control signal lines 107-1 to 107-5, and the old data read operation is completed.

Further, in the case of the write operation of new data from the host computer to the write data buffer 5b in the array data control circuit 5, the microprocessor control circuit 9 causes the host data bus 102 and the array data control circuit 5 to operate.
The array data control circuit 5 is instructed to establish a write data path between and. At the same time, the microprocessor control circuit 9 instructs the host interface control circuit 4 to receive write data from the host computer.

After confirming that the instructed data has been transferred from the host computer to the write data buffer 5b, the host interface control circuit 4 controls the control signal line 105.
Through this, the microprocessor control circuit 9 is notified of the end of the write operation of the new data in the write data buffer 5b.

Further, in the case of the operation of writing the result of the exclusive OR of the old parity data and the old data and the new data in the above operation to the single disk devices 7-1 to 7-5, the microprocessor control circuit 9 Calculates the device numbers and the unit disk addresses of the unit disk units 7-1 to 7-5 for writing new data based on the write start address and the number of write data sectors used in reading the old data.

The microprocessor control circuit 9 determines the disk interface control circuit 6-1 based on the device numbers of the individual disk devices 7-1 to 7-5 obtained by this calculation.
6-5 to 6-5 through the control signal lines 107-1 to 107-5 based on the status information, the unit disk devices 7-1 to 7-corresponding to the device numbers obtained by the calculation.
5 determines whether or not it is accessible.

When the microprocessor control circuit 9 determines that it is accessible, the control signal lines 107-1 to 10-10 are connected.
Disk interface control circuit 6-1 through 7-5
The write single disk address is transferred to 6-5.

Disk interface control circuit 6-1 to 6-1
6-5 performs a write operation to the single disk devices 7-1 to 7-5 based on the write single disk address that has been sent.

If an instruction is sent from the microprocessor control circuit 9 to the disk interface control circuits 6-1 to 6-5 during this operation, the disk interface control circuits 6-1 to 6-5 will issue the instruction. Control signal line 107-
1 to 107-5 through the microprocessor control circuit 9
Send to.

When the individual disk devices 7-1 to 7-5 finish the write operation, the disk interface control circuit 6
-1 to 6-5 send control information which means that the microprocessor control circuit 9 can be accessed through the control signal lines 107-1 to 107-5, and an exclusive OR of old parity data, old data and new data. The operation of writing the result of (3) to a single disk is completed.

As described above, the single disk device 7-1
To 7-5 to the parity data buffer 5c in the array data control circuit 5 for reading the old parity data, the single disk devices 7-1 to 7-5 to the read data buffer 5a in the array data control circuit 5 for the old data The result of the data read operation, the write operation of the new data from the host computer to the write data buffer 5b in the array data control circuit 5, and the exclusive OR of the old parity data and the old data and the new data are shown in the single disk device 7- The data write command operation is completed by sequentially executing a total of four operations of writing in 1 to 7-5.

FIG. 2 is a block diagram showing the configuration of the rotation synchronization control circuit 1 and the count register circuit 3 of FIG. 1, and FIG. 3 is a timing chart showing the operation of one embodiment of the present invention.

2 and 3, a count register circuit 3 for storing a frequency division counter for each single disk according to a command from the microprocessor control circuit 9 which is a feature of the disk array device of the present invention, and a division register circuit. Based on the signals from the oscillation circuit 2 that generates the original signal for the rotation, the count register circuit 3 and the oscillation circuit 2, the rotation synchronization signal 111- for the five single disk devices 7-1 to 7-5. Rotation synchronization control circuit 1 that outputs 1-111-5
Will be described in detail.

As shown in FIG. 2, the rotation synchronization control circuit 1 includes a single disk basic rotation synchronization signal generating circuit 11 for receiving a signal from the oscillation circuit 2 and generating a single disk basic rotation synchronization signal, and five single disks. Disk devices 7-1 to 7-5
Individual disk rotation synchronization control circuit 12-1 corresponding to each
.About.12-5.

The single disk rotation synchronization control circuit 12-1 includes a decoder (DECODER) 13-1 for decoding the value of the frequency division counter stored in the single disk count value registers 31 to 35 of the count register circuit 3, and a single disk. Flip-flops (F / F) 14-1, 15- that sequentially hold the output of the basic rotation synchronization signal generation circuit 11
1, ..., 18-1, the output of the single disk basic rotation synchronization signal generation circuit 11 and the flip-flop 14-1,
A NAND circuit 19- that gates the outputs of 15-1, ..., 18-1 according to the output of the decoder 13-1.
, 24-1, and NAND circuits 19-1, 20-1, 21-1, ..., 24-1 are subjected to NAND operation to perform rotation synchronization. And a NAND circuit 25-1 which outputs the signal 111-1.
Although not shown, the single disk rotation synchronization control circuits 12-2 to 12-5 are the single disk rotation synchronization control circuit 1
It has the same configuration as 2-1.

Therefore, the individual disk rotation synchronization control circuits 12-1 to 12-5 corresponding to the five individual disk devices 7-1 to 7-5 of the rotation synchronization control circuit 1 are stored in the count register circuit 3. The rotation synchronization signals 111-1 to 111-5 are output at the timing of the value of the frequency division counter. As a result, the read / write processing is performed at the timing of the rotation synchronization signals 111-1 to 111-5 from the rotation synchronization control circuit 1 in each of the five single disk devices 7-1 to 7-5.

For example, when writing data to the stand-alone disk device 7-1 and the stand-alone disk device 7-5, writing of the data is completed after each of the stand-alone disk devices 7-1 and 7-5 receives the data. If the time until the data is sent is sufficiently longer than the time until the array data control circuit 5 finishes sending the data, immediately after the end of sending the data from the array data control circuit 5 to the single disk device 7-1. A single disk device 7 is provided so that the array data control circuit 5 can send data to the single disk device 7-5.
By setting the value of the frequency division counter of -5, the data writing to the single disk device 7-5 can be started without waiting for the data writing to the single disk device 7-1.

That is, when the data transmission time from the array data control circuit 5 to the stand-alone disk device 7-1 is d, and the value of the frequency division counter of the stand-alone disk device 7-1 is a, the microprocessor control circuit 9 Instructs the count register circuit 3 so that the value of the frequency division counter of the single disk device 7-5 becomes a + d. In this case, the data transmission to the single disk device 7-5 is started while the data is being written to the single disk device 7-1.

That is, the conventional fifth level disk array device disperses the parity data in each disk device and aims at multiplexing of read / write processing.
Because it uses an inexpensive small-sized magnetic disk device that does not have a rotation synchronization function, it has become a disk array product with poor processing performance.

On the other hand, in the disk array device according to the embodiment of the present invention, a small magnetic disk device having a rotation synchronizing function is used, and the rotation synchronizing signals 111-1 to 111-1 delayed by the rotation synchronizing control circuit 1 for a predetermined time are used. Since 111-5 is distributed to each magnetic disk device (single disk devices 7-1 to 7-5), a disk array device having more excellent processing performance can be constructed.

Further, by changing the value of the frequency dividing counter corresponding to each of the individual disk devices 7-1 to 7-5 in accordance with the instruction from the microprocessor control circuit 9, the microprocessor control circuit 9 causes the single disk device 7- 1-7-
It is possible to change the timing of the rotation synchronization signals 111-1 to 111-5 to be distributed to the individual disk devices 7-1 to 7-5 while confirming the performance (overhead etc.) of each of the five.

In the above embodiment of the present invention, 5
Although it is composed of one single disk device 7-1 to 7-5, the logical disk device 8 can be configured with more or less than this number.

As described above, the value of the frequency division counter set in advance corresponding to each of the single disk devices 7-1 to 7-5 having the rotation synchronization function is held in the count register circuit 3, and the count register circuit 3 holds this value. Based on the contents of the register circuit 3, the rotation synchronization signal 111 is sent to each of the single disk devices 7-1 to 7-5.
By controlling the rotation synchronous control circuit 1 to output -1 to 111-5, it is possible to realize a disk array device having excellent processing performance.

[0070]

As described above, according to the present invention, the frequency division count value set in advance corresponding to each of the plurality of single disk devices having the rotation synchronization function is held, and the held contents are stored. Based on the control so that the rotation synchronization signal is output to each of the plurality of single disk devices, there is an effect that a disk array device having excellent processing performance can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a rotation synchronization control circuit and a count register circuit of FIG.

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 Rotation synchronous control circuit 2 Oscillation circuit 3 Count register circuit 4 Host interface control circuit 5 Array data control circuit 6-1 to 6-5 Disk interface control circuit 7-1 to 7-5 Single disk device 9 Microprocessor control circuit

Claims (3)

[Claims] 1. A plurality of single disk devices having a rotation synchronization function, and holding means for holding a preset frequency division count value corresponding to each of the plurality of single disk devices,
A disk array device comprising: control means for controlling a rotation synchronizing signal to be output to each of the plurality of single disk devices based on the contents of the holding means. 2. The control means is configured to output a rotation synchronization signal delayed by a predetermined time to each of the plurality of single disk devices.
The described disk array device. 3. A monitoring unit for monitoring a data read / write operation to each of the plurality of single unit disk devices, and each of the plurality of single unit disk devices held by the holding unit according to the monitoring result of the monitoring unit. 3. The disk array device according to claim 1, further comprising means for varying the frequency division count value.