JPH08130532A - Synchronizing replacement circuit for digital sound - Google Patents

Abstract

PURPOSE: To provide a digital sound synchronizing replacement circuit capable of erasing a decoded sound noise at the time of switching a read counter value and attaining digital sound synchronizing substitution by a compact and low speed circuit. CONSTITUTION: The synchronizing substitution circuit is provided with a write address counter 3, a read address counter 6, a slip monitor 8 for switching the read count value when the write count value of the counter 3 and the read count value of the counter 6 approach a previously set value, and a timing adjusting circuit 11 for switching the read count value at timing capable of preventing the generation of a noise. The circuit 11 is provided with a mute detector 9 and a judging device 10. The detector 9 detects a mute section in input sound data. The judging device 10 switches a read address in the mute section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital voice signal transmission device, and more particularly to a digital voice synchronous transfer circuit.

[0002]

2. Description of the Related Art With the widespread use of digital transmission lines in recent years, there has been a strong demand for a technique for synchronously transferring digital audio signals in digital audio signals by transferring digital signals between different transmission lines in a synchronous system.

FIG. 3 is a diagram showing an example of the configuration of a conventional digital voice synchronous transfer circuit. In the illustrated example, the digital voice synchronous transfer circuit includes a write address counter 3, a buffer memory 4, a read address counter 6, and a slip monitor 8. The input digital audio signal f input from the digital audio signal input terminal 1 is sequentially written in the buffer memory 4. Here, the write address a of the buffer memory 4 is output from the write address counter 3 which operates at the write clock synchronized with the input digital audio signal input from the write clock input terminal 2. The data g sequentially read from the buffer memory 4
Is output from the digital audio output terminal 7. Also,
The read address b of the buffer memory 4 is output from the read address counter 6 that operates with the write clock input from the read clock input terminal 5. On the other hand, the slip monitor 8 compares the write address a and the read address b, and outputs a switching signal c forcibly switching the read address to the read address counter 6 when they become the same value or the same value.

[0004]

In the digital voice synchronous transfer circuit according to the above-mentioned conventional example, data loss or data duplication occurs when the read address is switched. Therefore, if the data at the read address switching point is decoded as it is, noise is generated because the waveform is not continuous. Further, in data transmission other than voice, if a means such as re-sending of data is used, there will be no practical problem, but since the voice data must be kept in real time, it cannot be resent.

Further, in addition to the above-described digital voice synchronous transfer circuit, (a) a multipoint sampling method,
(A) A method using an oversampling digital filter, (c) a method of returning to analog voice and then transposing, etc. are conceivable. However, the methods of (a) and (a) above require a large circuit scale and operation. The speed must also be high, and the method of item (c) above has the drawback that quantization noise increases and speech quality deteriorates.

Therefore, a first technical object of the present invention is to provide a digital voice synchronous transfer circuit capable of preventing decoded voice noise when the read count value is switched.

A second technical object of the present invention is to provide a digital voice synchronous transfer circuit which can be realized by a small-scale and low-speed circuit.

[0008]

In the digital voice synchronous transfer circuit of the present invention, a buffer memory, a write address counter, a read address counter, a write count value of the write address counter, and a read of the read address counter. The present invention is characterized by comprising switching means for switching the read count value when the count value approaches a preset value, and timing adjusting means for switching the read count value at a timing at which noise can be prevented.

In the digital voice synchronous transfer circuit according to the present invention, the timing adjusting means includes a silence detector for detecting a silence section of the input voice data, and a determiner for switching a read address during the silence section. It is characterized by having.

Further, in the digital voice synchronous transfer circuit according to the present invention, the switching means constantly monitors a difference between the write count value and the read count value, and the difference becomes equal to or less than a preset value. At the time, it is determined that the occurrence of slip is approaching, and it comprises a slip monitor that outputs a slip approach signal to the determiner, and the silence detector detects the silence when the volume of the input voice signal is determined to be silence. The judging device outputs the read address switching signal only when the input slip approach signal is in the slip approaching state and the silent detection signal is in the silent section, and the read address counter reads the read signal. When the count value is switched, the difference between the write count value and the read count value is calculated by the slip monitor. It is characterized in that a higher value.

[0011]

In the present invention, the timing adjusting means comprises a silence detector and a judging device, and this silence detector detects the silent section of the input voice data. The determiner also switches the read address during the silent section. As a result, the read address count value is switched at a timing at which noise can be prevented.

[0012]

EXAMPLE An example of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an example of the configuration of a digital voice synchronous transfer circuit according to the present invention. 2 is a waveform diagram showing the operation of the digital voice synchronous transfer circuit of FIG. As shown in FIG. 1, a digital voice synchronous transfer circuit according to an embodiment of the present invention includes a buffer memory 4, a write address counter 3, a read address counter 6, a write count value and a read address of the write address counter 3. When the read count value of the counter 6 approaches a preset value, a slip monitor 8 is provided as a switch circuit for switching the read address count value, and a timing adjusting circuit 11 for switching the read count value at a timing capable of preventing noise. Is equipped with. The timing adjusting circuit 11 has a silence detector 9 connected to have the terminal 1 on the input side, the silence detector 9 and the slip monitor 8 on the input side, and a read address counter 6 on the output side. And the determination device 10 connected as described above.

The silence detector 9 detects the volume of the input audio signal f, for example, as shown in FIG.
When 1 or more continues, the silence detection signal d is output by a method such as determining silence.

The slip monitor 8 has a write address a.
And the read address b, that is, the difference between the write count value and the read count value is constantly monitored, and when the difference becomes equal to or less than a preset value, it is determined that the slip has approached, and the slip approach signal c Is output to the determiner 10.

The judging device 10 outputs the read address switching signal e only when the input slip approach signal c is in the slip approach and the silence detection signal d is in the silent section. In the read address counter 6, when the read address is switched, the difference between the write address a and the read address b becomes the set value of the slip monitor 8 or more.

Since the audio data when the read address is switched is in the silent section, audible noise does not occur in the decoded audio data.

It should be noted that the determination value for slip monitoring, the threshold Vth for detecting silence, and the protection time t1 are set to optimum values depending on the frequency of slip occurrence on the transmission path used and the frequency of silence occurrence in the audio data to be transmitted. It is necessary, and the write address switching amount is the protection time t1 for silence detection.
It goes without saying that you need to do the following:

[0019]

As described above, according to the present invention, a read counter is provided by adding a silence detector for detecting a silence section of input voice data as a timing adjustment circuit and a determiner for switching a read address during the silence section. This has the effect of eliminating the decoded audio noise when changing the value. In particular, in the transmission of program audio data for broadcasting, since the frequency of occurrence of silent sections can be predicted in advance (when switching programs, for example, several times / hour, several seconds / time), it can be easily applied.

Needless to say, the present invention can be realized by a small-scale and low-speed circuit as compared with the multipoint sampling method and the method using an oversampling digital filter.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a digital voice synchronous transfer circuit according to the present invention.

FIG. 2 is a waveform diagram showing the operation of the digital voice synchronous transfer circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional digital voice synchronous transfer circuit.

[Explanation of symbols]

 1 Digital voice input terminal 2 Write clock input terminal 3 Write address counter 4 Buffer memory 5 Read clock input terminal 6 Read address counter 7 Digital voice output terminal 8 Slip monitor 9 Silence detector 10 Judgment device 11 Timing adjustment circuit a Write address b Read address c Slip approach signal d Silence detection signal e Read address switching signal f Input voice signal

Claims (3)

[Claims] 1. A switching means for switching the read count value when a read count value of a buffer memory, a write address counter, a read address counter, and a write count value of the write address counter approach a preset value. And a timing adjusting means for switching the read count value at a timing at which noise can be prevented. 2. The digital voice synchronous transfer circuit according to claim 1, wherein the timing adjusting unit switches a silence detector that detects a silence section of the input voice data and the read count value during the silence section. A digital voice synchronous transfer circuit comprising a judging device. 3. The digital voice synchronous transfer circuit according to claim 2, wherein the switching means constantly monitors a difference between the write count value and the read count value, and the difference is equal to or less than a preset value. When it is determined that the occurrence of slip is approaching, it comprises a slip monitor that outputs a slip approach signal to the determiner, and the silence detector outputs silence when the volume of the input voice signal is determined to be silence. The detection signal is output, the judging device outputs the read address switching signal only when the input slip approach signal is in the slip approaching state and the silent detection signal is in the silent section, and the read address counter, When the read address is switched, the difference between the write count value and the read count value is set in the slip monitor. Synchronous handoff circuit of the digital speech characterized by a value or more.