JPH08125818A - Image processing unit - Google Patents

Abstract

PURPOSE: To attain write and read processing of image data to/from a storage means efficiently after image processing without so much load onto an MPU in the write and read processing of image to/from the storage means such as a line buffer after image processing. CONSTITUTION: The processing unit is provided with a compander 1 executing specific image processing to image data, a RAM 200 storing image data outputted from the compander 1 in the unit of a prescribed amount, a DMA controller 102 writing image data to the RAM 200 and reading image data from the RAM 200, and a microprogram control section 1600 being a means detecting image data left in the RAM 200, informing it to the MPU when the remaining image data are a prescribed amount or below and decreased more than by the preceding detection value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which handles image data or code data thereof, and particularly compression of image data, expansion of image code data, conversion of image data (enlargement / reduction) necessary for a facsimile machine or the like. ), An image processing device for converting image code data into another code.

[0002]

2. Description of the Related Art This type of image processing apparatus is required in a facsimile apparatus, other image communication apparatus, image file system and the like.

FIG. 39 shows an example of a conventional facsimile apparatus. In this facsimile apparatus, two compression / decompression devices (# 1) 8001 and (# 2) 8002 for decompressing received code data or image data and enlarging / reducing image data (image conversion) are provided. Image conversion device 8
003, which interface with both the system bus 8005 and the image bus 8006.

The received code data demodulated by the modem 8007 is buffered in the compressed data memory 8009 on the system bus 8005 and then decoded by, for example, the compression / expansion device (# 1) 8001, and the restored image data is restored to the image bus 8006. Upper image page memory 8010
Be deployed to. RAM8016 is used as a reference line memory.

When the image data of one page is restored and parameters such as the number of lines thereof are obtained, the enlargement / reduction ratio of this image data is determined and designated to the image conversion apparatus 8003. Then, the image conversion device 8003 executes enlargement / reduction processing of the image data on the image page memory 8010, and the processed image data is recorded image processing unit 80.
It is transferred to the printer 8012 via 11 and printed on the recording paper.

When a request for reading a transmission original is issued during the receiving operation, the transmission original image data read by the image scanner 8014 and processed by the read image processing unit 8015 is RAM (line buffer) on the image bus 8006. The other compression / decompression device (#
2) Coded by 8002. The coded data is stored in the compressed data memory 8009. RAM8016
Are used as an encoding line memory and a reference line memory.

Conventionally, such a compression / expansion device is shown in FIG.
The configuration was as shown in. In FIG. 40, 8050
Is an image bus unit for interfacing with the image bus, and 8051 is a system bus unit for interfacing with the system bus. Image data or code data is transferred through these bus units 8050 or 8051.
Input / output as 6-bit or 8-bit parallel word data.

Regarding the encoding process, the reference line changing pixel detecting unit 805 for detecting the changing pixel address of the reference line.
2, a coded line changed pixel detection unit 8053 that detects a changed pixel address of a coded line, a coding mode determination unit 8054 that determines a coding mode (vertical, horizontal, pass) using these changed pixel address information, A code table search unit 8055 that performs code allocation based on this determination result
And a code table (ROM) 8056. Regarding the decoding process, the decoding table search unit 8058 for code analysis, the decoding table (ROM) 8059, the starting point of the decoding line or the reference change pixel a0 address (ITU-
T Recommendation T. A0 address calculation unit 80 for calculating
60, an image data drawing unit 8061 for drawing the image data of the decoding line. Reference numeral 8062 denotes a control unit that monitors and controls the state of the entire compression / expansion device.

[0009]

In the conventional compression / decompression device configured as described above, in the case of the compression operation, the image data is input in units of one word, the change pixel address is detected, encoded, and encoded. Since a series of processing of outputting data is performed serially, the compression processing time is expressed by the following equation.

Processing time = image input time + encoding processing time + code output time (Equation 1) The encoding line memory and the reference line memory are placed in the external memory (RAM 8016 in FIG. 40) on the image bus. Access time is quite large. This bus access time determines the lower limit of the first term of Expression 1, and therefore there is a limit to the speedup. This is the first problem to be solved by the present invention.

Particularly, when a plurality of compression / decompression devices and further an image conversion device are placed on a common bus as in the example of the facsimile apparatus shown in FIG. The increase in processing time becomes remarkable.

When processing a coarse image, the second term of Equation 1
Since the time of the third term is smaller than that of the first term, the entire processing time is almost determined by the image input time of the first term. On the other hand, when processing a fine image, the encoding processing time of the second term increases, and since the code data also increases, the code output time of the third term also increases, so that the overall processing time is long. Further, the entire processing time greatly varies depending on the content of the processed image.

The same applies to the decompression operation. As is clear from the description of the operation of the facsimile apparatus shown in FIG. 39, when the image conversion of the restored image data is necessary, it is necessary to obtain the parameter for determining the enlargement / reduction ratio, and the image is restored until the entire page is restored. Cannot start conversion. Therefore, a large-capacity memory (image page memory 801 in FIG. 39) capable of accumulating one page of restored image data.
0) is required. Further, the image conversion device is independent of the compression / decompression device, and if an attempt is made to serially perform image conversion and compression / decompression processing, an external bus must be accessed for image conversion. There is a limit to the speed of processing. Further, the conventional compression / expansion device compresses or expands an image block consisting of one line or a plurality of lines as one processing unit upon activation from the host processor, and repeats this to process one page of image data. . During this time, DMA transfer of image data between an input / output device such as a scanner and a printer and the line buffer memory and management of the line buffer memory related thereto are required, but these processes are executed under the control of the host processor. There is.

Therefore, the second problem is that even if only the compression / decompression processing is speeded up, unless the processing load on the compression / decompression device of the host processor is reduced, the lower limit of the total processing time is determined by the sum of the startup waiting times. There is. In other words, the conventional compression / decompression device has a configuration that is easily affected by the environment in which it is used for high-speed processing, and there is a problem that the performance at the time of design cannot be sufficiently exerted in an actual environment.

The present invention has been made in view of the above problems, and is required in a facsimile machine or the like.
Image processing after being valued, that is, compression processing, decompression processing,
Provided is an image processing apparatus that executes image conversion processing, code conversion processing, DMA transfer processing of image data, etc. at high speed inside the apparatus without outputting the data being processed, and further reduces the processing load of the host processor. The main purpose is that. Further, according to the present invention, in the writing and reading processing to the storage means such as the line buffer after the image processing, it is possible to prevent the data to be read out during the image processing without being so heavy on the MPU and to be efficient. It is an object of the present invention to provide an image processing device capable of writing and reading image data to and from storage means after image processing.

[0016]

In order to achieve the above object, the present invention stores processing means for executing specific image processing on image data, and image data output from the processing means in predetermined units. Storage means, means for writing image data to the storage means and reading image data from the storage means, detection means for detecting image data remaining in the storage means, and remaining image data in advance. And a means for notifying the external device of this when the value is equal to or less than the predetermined value and is smaller than the previously detected value. The present invention is not limited to such a configuration. As can be understood from the description of the claims and the description of the entire specification, the present invention includes various aspects and has a characteristic configuration in each aspect.

[0017]

With the above-described structure, the image processing apparatus of the present invention can store data to be read in the middle of image processing without significantly burdening the MPU in the writing and reading processing to the storage means such as the line buffer after the image processing. It is possible to prevent the data from being lost, and to efficiently perform the writing and reading processing of the image data into the storage means after the image processing or the like.

[0018]

1 is a block diagram showing the schematic construction of an example of a compression / expansion device according to the present invention. The compression / expansion device 1 is an image processing device that combines a compression device, a decompression device, an image conversion (enlargement / reduction) device, a code conversion device, and a DMA transfer device.

Structure of Facsimile Machine FIG. 2 shows an example of a facsimile machine using the compression / expansion device 1. The compression / expansion device 1 is connected to the system bus 10 and the image bus 11. In FIG. 2, on the system bus 10, a processor block 13 including a microprocessor (MPU) and a DMA controller (DMAC) for controlling the entire facsimile apparatus and controlling the facsimile communication procedure, and a peripheral including a gate array such as an address decoder. A circuit block 14, a memory block 15 including a ROM and a RAM for storing control programs and data, a compressed data memory 16 mainly used for storing compressed data of a transmission document or a reception document,
An operation panel 18 including switches and a display for operating the facsimile machine, a modem 19 for modulating / demodulating line signals, and the like are also provided. 20 is a network control circuit (NC
U), through which the facsimile device is connected to a public telephone line network or the like.

The read image processing unit 2 is provided on the image bus 11.
1, a recording image processing unit 22 and a RAM 28. This R
The AM 28 is used as a line buffer for inputting / outputting image data by the compression / expansion device 1. The read image processing unit 21 processes the analog image signal input from the image scanner 23 and outputs it to the image bus 11, and has a RAM 27 as a work memory. The processing by the read image processing unit 21 includes A / D conversion for analog image signals, pseudo-correction for digital image signals, MTF correction (edge emphasis), and binary smoothing.
Image processing such as multilevel smoothing and error diffusion (halftone processing) is included.

The image scanner 23 scans a document and reads image information. The CCD image sensor 24,
The CCD image sensor 24 illuminates the original and gives an optical image.
The lens / light source unit 25 for forming an image on the document, and the reading mechanism control unit 26 for controlling the sub-scan feed mechanism for the document. The recording image processing unit 22 takes in the image data from the image bus 11 and supplies it to the laser beam printer (LBP) 29 for printing.

Overall Configuration of Compression / Expansion Device Next, referring to the system configuration shown in FIG.
The configuration of the compression / expansion device 1 will be described. In FIG. 1, 10
An image bus control unit 0 realizes an interface function with the image bus 11. 200 is a RAM,
Used as a line memory and parameter register for internal processing. This RAM 200 can also be accessed from the MPU (FIG. 2) of the processor block 13. Three
Reference numeral 00 is an internal bus DMA control unit for controlling DMA transfer to the RAM 200 by the internal data bus (BE data bus) 1700, and 400 is a system bus control unit for interfacing with the MPU (FIG. 2).

Reference numeral 500 is a working register used as various registers, and RAM is actually used. 600 to 800 are FIFO buffers for temporarily storing the change pixel address information of 16-bit width data, 1
Reference numeral 200 is an arithmetic logic operation unit used in connection with execution of internal processing, 1300 is an MH / MR / MMR decoder, 140
Reference numeral 0 is an image conversion unit that performs image conversion (enlargement / reduction) in the main scanning direction of the image, 1500 is an MH / MR / MMR encoder,
Reference numeral 1600 is a microprogram control unit for controlling the operation of the apparatus.

The changed pixel detection units 600 to 800 and F
The IFO buffers 900-1100 can also be included in the corresponding processing blocks 1300-1500. However, in this case, since the changed pixel detection unit 600 and the FIFO buffer 900 are shared by the two processing blocks 1300 and 1500, it is necessary to add the same two sets.

Reference numeral 1700 is a DMA control bus, which comprises a DMA transfer request signal line from each unit and a DMA transfer permission signal line to each unit. Internal data bus (BE data bus) 18
00 is a 16-bit bus mainly used for transferring image data. 1900 is also a 16-bit internal data bus (BC data bus), which is mainly used for transfer of encoded data. Although not shown in FIG. 1, a micro program control bus exists between the micro program control unit 1600 and each unit in the apparatus (see FIG. 6 and the like).

Configuration of Encoder FIG. 3 is a block diagram of encoder 1500. In FIG. 3, the changed pixel address control unit 1502 outputs the changed pixel address of the reference line from the FIFO buffer 900 to the FI.
The changed pixel addresses of the coding line are fetched from the FO buffer 1100, ordered, and input to the coding mode determination unit 1504. This encoding mode determination unit 15
Reference numeral 04 determines the encoding mode (pass, vertical, horizontal mode) from the input changed pixel address information. The code table search unit 1506 searches the internal code table based on the determination result of the coding mode and performs code allocation.

The packing processing unit 1508 outputs a variable length 16 bits / bit output from the code table search unit 1506.
Converts words to coded data (word packing), and performs internal data bus 1900 or 18 in word units.
Output to 00. Reference numeral 1510 is a main sequencer for overall control of the encoder 1500. The request for the DMA transfer with the internal RAM 200 is issued by the main sequencer 1510.
Issued more. 1512 to 1518 are corresponding functional blocks 1502-1 under the control of the main sequencer 1510.
It is a sub sequencer for controlling 508. Encoder 150
0 is also an internal data bus (BE data bus) 1800
A register 1520 in which the width of one line (the number of words of image data of one line) is set is provided with a counter 1522 for counting the number of codes of one line (the number of words of code data of one line). This counter 1522
Can be output to internal data bus 1800.

The micro program control unit 1600 is provided with an encoder 15 via a micro program control bus 1602.
It is possible to specify the encoding mode for 00, control such as activation, and obtain the state of the encoder 1500.

Decoder Configuration FIG. 4 is a block diagram of decoder 1300. In FIG. 4, the code shift unit 1302 shifts the code data fetched from the internal data bus (BC data bus) 1900 by the code length for which decoding has been completed, and always provides the code analysis unit 1304 with undecoded code data. Code analysis unit 1304
Searches the internal decoding ROM according to the code data and sends the decoded code to the drawing unit 1308.

The a0 address operation unit 1306 is a FIFO
An a0 address (see ITU-T Recommendation T.4), which is the standard change pixel address of the decoded line, is calculated from the change pixel address information of the reference line input from the buffer 900 and the decoded code input from the code analysis unit 1304. The drawing unit generates image data from the a0 address and color (white / black) information, and outputs the generated image data to the internal data bus (BE data bus) 1800 in units of words (16 bits).

Reference numeral 1310 is a main sequencer for controlling the entire decoder 1300, and reference numerals 1312 to 1318 are corresponding functional blocks 1 under the control of the main sequencer 1310.
It is a sub sequencer for controlling 302 to 1318. D
The MA transfer request is issued from the main sequencer 1310. The decoder 1300 also includes a comparator 1320 for detecting white data (words in which all bits are white bits) from the restored image data, and a continuous EOL for considering it as an RTC code.
A register 1322 in which the number and the restoration width of one line are set from the internal data bus (BE data bus) 1800,
324. Based on the comparison result by the comparator 1320, the main sequencer determines a white line (a line in which all bits are white pixels), and outputs the determination result to the microprogram control bus 1602 as a status signal.

Further, the main sequencer 1310 checks whether or not there is a decoding error for each line. The check result is output as a status signal. The microprogram control unit 1600 can control the decoder 1300 such as designation and activation of a decoding mode and state monitoring through the microprogram control bus 1602.

Structure of Image Conversion Unit FIG. 5 is a block diagram of the image conversion unit 1400. In FIG. 5, the register 1402 is a FIFO buffer 1000.
The register 1404 holds the change pixel address and the color information (B / W) to be input from the internal data bus (B
E data bus) 1800 is used to set the scaling rate. The multiplier 1406 multiplies the changed pixel address by the enlargement / reduction ratio to obtain the changed pixel address after the enlargement / reduction, and supplies it to the drawing unit 1408. The drawing unit 1408 generates scaled image data based on the given change pixel address and the color information given by the register 1402. This image data is stored in the register 14
The data is output to the internal data bus (BE data bus) 1800 in units of words via 10. Reference numeral 1412 is a register in which the 1-line width (word number) before conversion is set via the internal data bus 1800, and 1414 is a register for counting the 1-line width (word number) after conversion. 141
A sequencer 6 controls each unit in the image conversion unit 1400 and also issues a DMA transfer request.

Arrangement of Arithmetic and Logical Operation Unit, Working Register, etc. FIG. 6 shows an arithmetic and logic operation unit 1200, a working register (RAM) 500 and its peripheral configuration, and a connection configuration with other functional blocks. In FIG. 6, 12
Reference numeral 02 is a 16-bit ALU (including a shifter) that forms the center of the arithmetic logic operation unit 1200. As you can see from the figure, R
It is possible to load data from the AM 200 or the like into the ALU 1202, perform a necessary calculation, and write the calculation result in the RAM 200 or the like. In addition, scan and check the registers on the working register (RAM) 500
It can be done via U1202. 6, reference numerals 1204 and 1206 denote input registers 1207 and 1208 of the ALU 1202, selectors for selecting inputs of the ALU 1202, 1210 a local bus of the arithmetic logic operation unit 1200, and 1211 an output buffer to the local bus 1210. 1212 and 1213 are local buses 1
It is a buffer for data transfer between 210 and an internal data bus (BE data bus) 1800.

Reference numeral 1214 is the microprogram control bus 1
A decoder that decodes the peripheral address on 602 and outputs a control signal for the ALU 1202 peripheral, 1216 is an R / W control circuit (decoder) that controls the read / write of the working register 500, and 1218 is an address controlled by the microprogram controller 1600. Pointer, 122
Reference numeral 0 is a selector which selects the value of the address pointer 1218 or the address given from the microprogram control bus 1602 and outputs it to the address bus 1220.

Configurations of Micro Program Control Unit and System Bus Control Unit FIG. 7 is an explanatory diagram of configurations of the micro program control unit 1600 and the system bus control unit 400. This compression / expansion device 1 has two encoding and decoding processing channels each, and can perform processing by switching the channels on a line-by-line basis. In order to facilitate the execution of such processing, the system bus control unit 400 has a channel 0 (CH0)
There is a register set 402 for channel 1 and a register set 404 for channel 1 (CH1). The system bus control unit 400 also includes a system bus timing control unit 406.
And as shown in FIG. 1, the data buffers 408, D
An MA controller 410, a clock generator 412, etc. are also included.

The microprogram control unit 1600 has a general structure. In addition to a microROM 1601 storing a microprogram for processing various commands, a program counter 1603 for controlling the execution of the microprogram, a stack 1604, and a stack. Pointer 1605, instruction register 1606, instruction decoder 160
Including 7. The micro program control unit 1600 further includes a macro ROM 1608 storing the start address of the micro program for each macro command, and a selector 1609 for inputting the macro command set in the command register in the register sets 402 and 404 to the macro ROM 1608. , Micro ROM 1602
A multiplexer 1610 for switching the input of the above, a multiplexer 1611 for inputting a status signal on the microprogram control bus 1602 and an activation signal from the system bus control unit 400 to the multiplexer 1610 as a control signal.

Method of Using Internal RAM FIG. 8 is an explanatory diagram of a method of using the RAM 200. RAM
The linear address space of 200 is channel 0 (CH
0) parameter register set area 201, channel 1 (CH1) parameter register set area 204, and image memory area 206 are used. Parameter register set area 20 for each channel
2, 204 are divided into encoding command, decoding command, other commands, and parameter register areas 208 to 214 for DMA transfer.

The image memory area 206 is divided into a plurality of line memory areas, and the divided areas are used as various line memories according to processing contents, as will be described later with reference to FIGS.

Configuration of Image Bus Unit FIG. 9 is a block diagram of the image bus control unit 100.
The image bus control unit 100 includes a DMA controller 102 for DMA transfer of image data, an address counter 104, and a data buffer 106. Under the control of the image bus control unit 100, the following four types of image data can be DMA-transferred. a) Transfer from I / O device (read image processing unit 21) on image bus to memory (RAM 28) b) I / O from memory (RAM 28) on image bus
Transfer to device (recorded image processing unit 22) c) Transfer from memory (RAM 28) on image bus to compression / expansion device 1 d) Memory on image bus (RA from compression / expansion device 1)
M28) transfer The address counter 104 corresponds to 4 for each DMA transfer.
It is composed of a set of address registers 110 and an incrementer 112. Similarly, the DMA controller 102
Includes four sets of transfer number registers 114 and decrementer 11
6 is included. The DMA controller 102 also has a D
A priority control 118 and a timing control unit 120 for priority control of MA transfer are included.

Configuration Related to Line Memory FIGS. 10, 11 and 12 show the internal bus DMA controller 3.
00, the address register 50 defined on the working register 500 by the microprogram.
2 is a diagram for explaining the breakdown of the line memory 216 defined in the image memory area 206 of the RAM 2 and the RAM 200 and the corresponding relationship between them. 10 shows the case of encoded command processing, FIG. 11 shows the case of decoding command processing, and FIG. 12 shows the case of code conversion command processing. In the following description, when it is necessary to distinguish the address register 502 and the line memory 216, the name INPU shown in FIG. 10, FIG. 11 or FIG.
T to D1R are used.

The internal bus DMA control unit 300 has the same number of address counters (A to J) 30 as the line memories 216.
2. DMA for controlling DMA transfer between the RAM 200 and processing blocks such as the encoder 1500 and the decoder 1300
A control unit 304, a selector 306 for selecting the address counter 302, and the like are included. The area of the line memory 216 on the RAM 200, the address counter 302, and the address counter 502 have a one-to-one correspondence. Since the reference line line memories for the encoding process and the decoding process are for two channels, it is easy for the external MPU to operate so that the image processing device 1 has two encoders 1500 and two decoders 1300. Is.

FIG. 13 shows the structure of the address register 502 defined on the working register 500. IN
Although the PUT address register is shown as an example, the structure of other address registers 502 is similar. As shown, the lower 11 bits of the address register 502 are the start address of the line memory. Upper 4 bits (A
~ E) are flag bits, and their meanings are as follows. A: "1" indicates that the corresponding line memory has valid data. B: "1" indicates that the content of the corresponding line memory is reduction target data. When C: "1", the content of the corresponding line memory is the final line data. D: This flag has a different meaning depending on the command processing content. E: "1" indicates that the content of the corresponding line memory is the enlargement target data. The microprogram can operate and check these flag bits by using the arithmetic and logic operation unit 1200.

Operation of the compression / expansion device FIG. 2 shows the compression / expansion device 1 configured as described above.
The operation when used in the facsimile apparatus shown in FIG.

The input / output path of the image data of the compression / expansion device 1 is as follows. a) read image processing unit 21 → compression / expansion device 1 b) read image processing unit 21 → RAM 28 → compression / expansion device 1 C) compression / expansion device 1 → recorded image processing unit 22 d) compression / expansion device 1 → RAM 28 → recorded image processing The image bus control unit 100 of the compression / decompression device 1 supports the DMA transfer of such image data.
It is the DMA channel 1 that is transferred from the channel 0 and the RAM 28 to the recording image processing unit 22 (see FIG. 2).

Description of compression operation (outline) The MPU (FIG. 1) of the processor block 13 is
By issuing a macro command to the compression / expansion device 1, an operation instruction is given. The MPU first sets various registers in the system bus control unit 400. This also includes instructions for coded channels CH0 and CH1. After this register setting is completed, the encoded command is written in the command register 402A or 404B (FIG. 7) of the designated channel in the system bus control unit 400. This command passes through the selector 1609 to the macro ROM 1
It is decoded in 608 and the start address of the encoding program is output. Micro ROM from this address
The encoding program in 1601 is executed. Each processing block in the compression / expansion device 1 has a micro ROM 1601.
It is controlled by a program written in.

As described above, the line memory 216 and the address register 502 defined in the case of the encoded command processing are as shown in FIG. The contents or roles of each line memory are as follows. INPUT: Image data of input line (input buffer) CONVR: Image data of line before main scanning conversion CONVW: Image data of line after main scanning conversion CODING: Image data of encoded line BC1: Code data (output buffer) BC: Code Data (output buffer) C0R: reference line image data for encoding channel 0 C1R: reference line image data for encoding channel 1 D0R: reference line image data for decoding channel 0 D1R: decoding channel 1 Image data of reference line for reference (explanation along FIG. 16) FIG. 16 shows a simplified example of the flow of the encoding program. The compression operation will be described in detail along this flow. When the encoded command is issued, the parameters required in the process 2001 are loaded into the working register 500 from the parameter register set area 202 (CH0) or 204 (CH1) of the RAM 200. The start address of the area of the line memory 216 having the same name is set in the address register 502.

When a DMA transfer request (transfer request from the read image processing unit 21 to the RAM 28 or a transfer request from the RAM 28 to the recording image processing unit 22) on the image bus 11 is made in the processes 2002 and 2003, the DMA transfer is performed. Perform processing. If there is a DMA transfer request, the microprogram stores the start address in the start address register 110 of the image bus control unit 100 and the transfer number register 11
The number of transfer words is set to 4, each is activated, and the activation flag is set to "1" (FIG. 9). After that, the image bus control unit 100 executes the DMA transfer.

In the next step 2004, the compression / expansion device 1 is loaded from the RAM 28 (line buffer) on the image bus 11.
Is a process of inputting one line of image data to the INPUT line memory on the RAM 200.

(Description with reference to FIG. 17: image data input)
The flow of this image data input processing is shown in FIG. FIG.
7, the microprogram executes the processes 2101 and 21.
In 02, it is confirmed that the image bus control unit 100 is not in operation and the activation flag of the image bus control unit is in the reset state. If this can be confirmed, the process 210
In step 3, the address counter A (FIG. 10) in the internal bus DMA control unit 300 is loaded with I from the INPUT address register.
The start address of the NPUT line memory is set via the internal data bus 1800. In process 2104, the address of the external RAM 28 is set in one of the address registers 104 (FIG. 9) of the image bus controller 100. here,
It is assumed that image data is input through the path of the read image processing unit 21 → RAM 28 → compression / decompression device 1.

In step 2105, the image bus controller 10 is executed.
The number of words in one line is set in one of the transfer count registers 114 (FIG. 9) in 0. In processing 1706, the image bus control unit 100 is set to the memory read mode, and processing 210
7 is started, and the start flag is set to "1" in process 2108. After activation, the incrementer 112 increments the memory read address and the decrementer 116 decrements the transfer word number each time the image bus control unit 100 reads 1-word data. The image data read by the image bus control unit 100 is stored in the I / O on the RAM 200 via the internal data bus (BE bus) 1800.
It is transferred to the NPUT line memory. This transfer is executed by the image bus control unit 100 issuing a DMA transfer request to the RAM 200, and the DMA control unit 304 in the internal bus DMA control unit 300 giving the control right of the internal data bus 1800 to the image bus control unit 100. To be done. When 1-word image data is transferred to the INPUT line memory,
The address counter A in the internal bus DMA control unit 300 is also incremented.

The above operation is repeated until the number of transfer words set in the image bus control unit 100 becomes zero. During the transfer, the process 2101 returns immediately after the determination. When the transfer of one line is completed, the image data for one line is stored in the INPUT line memory. The process 2109 and subsequent processes are processes after one line is input. In process 2109, process 210
The start flag set in 8 is reset. Process 211
At 0, the start address of the external RAM 28 containing the next line is calculated. In process 2111, the number of processing lines to be continuously processed by the encoded command is decremented, and the number of remaining processing lines is calculated. In Process 2112, Process 2
Based on the result of 111, it is determined whether the line input immediately before is the final line. If the last line, processing 2113
Then, the C flag of the INPUT address register is set to "1". In process 2114, the A flag of the INPUT address register is set to "1". The states of the A flag and the C flag are passed to the subsequent processing in the process of exchanging the contents of the address register as described later.

FIG. 14 shows a state when one line of data is stored in the INPUT line memory.
Here, it is assumed that the INPUT line memory is the memory area 216A starting from the address XXX. When the image data is completely input, the A flag of the INPUT address register is set to "1", and it can be seen that there is valid data in the INPUT line memory. Since the CONVR address register indicates YYY and its A flag is "0", it can be seen that the CONVR line memory is vacant in the memory area 216B starting from the address YYY.

(Continuing the Description According to FIG. 16) The process returns to the flow of FIG. The microprogram I in step 2005
Check A = 1 in the NPUT address register, A =
If it is 1, in processing step 2006, A = 0 of the CONVR address register is checked. INPUT A = 1 and C
If A = 0 in ONVR, that is, if there is valid data in the INPUT line memory and the CONTVR line memory is empty, the contents of the INPUT address register and the CONTVR address register are exchanged in step 2007.

(Data Transfer between Line Memories) Data transfer between the line memories will be described with reference to FIGS. 14 and 15. FIG. 14 shows a state before execution of the process 2007. FIG. 15 shows address registers INPUT and CON.
This is the state after the contents of the VR have been exchanged. In FIG. 15, the CONVR address register indicates the start address XXX of the memory area 216, and the INPUT address register indicates the start address YYY of the memory area 216B.
This means that the data input to the INPUT line memory is passed to the CONVR line memory, and the empty area is passed to the INPUT line memory. As described above, since the method does not involve the actual data movement on the RAM 200, the data transfer between the line memories is instantaneously performed. (Continued from the description according to FIG. 16) The next process 2008 is a scaling (image conversion) process in the main scanning direction. In this process, the data in the CONVR line memory is converted to CO
Write to NVW line memory. In this process 2008, the microprogram makes the following settings before activating the image conversion unit 1400. Internal bus DMA control unit 30
Address counters CO in the address counters B and C in 0
The head address set in NVR and CONVW is loaded (FIG. 10). MPU of processor block 13
The scaling ratio set in the parameter register 208 in the RAM 200 according to FIG.
It is set in the register 1404 (FIG. 5). CONVR
The number of words in the line is set in the register 1412. After such initial setting, the microprogram is converted into the image conversion unit 1.
400 is activated, and the process 2008 is exited.

The image data in the CONVR line memory is DMA-transferred to the changed pixel detection unit 700 and converted into changed pixel data, and its address information is input to the register 1402. Registers 1402, 1 by multiplier 1406
The contents of 404 are multiplied to obtain the changed pixel address data after conversion. Based on this data and the color information in the register 1402, the drawing unit 1408 creates converted image data. The obtained converted image data is DMA-transferred to the CONVW line memory. In this case, the DMA transfer from the CONVR line memory and the DMA transfer method to the CONVW line memory are the same as the DMA transfer from the image bus control unit 100 to the RAM 200. When the transfer of one line is completed, A of the CONVW address register is
Set the flag to "1".

When reduction in the sub-scanning direction is required, determination is made as to whether or not the line data on the CONVW line memory is a thinning line and flag control is performed following the one-line main scanning conversion. The contents of this processing will be described later. When it is determined that the line is the thinning line, the A flag of the CONVW address register is not set. Process 2009, 20
10, whether or not there is valid data after conversion and the COD for encoding
It is determined whether the ING line memory is empty. C
When A = 1 of the ONVW address register and A = 0 of the CODING address register, the next processing 2011
By exchanging the contents of the address registers CONVW and CODING, and loading the exchanged start address into the corresponding address counter 302, the line memory C
Transfers data between ONVW and CODING. In the case of thinning lines, this exchange is not done.

The process 2012 is a process of encoding the data in the CODING line memory. The micro program is
If the encoder 1500 is not in operation, the encoding mode (MH, MR, MMR encoding, etc.) is set for the encoder 1500, and one line width is set in the register 1520.
Start up. However, in case of thinning line, CONVW
Since the A flag of the address register is "0", the encoder 1500 is not activated. Encoder 1500 activated
Encodes the image data of the CODING line memory using the encoded reference line memories C0R (CH0) and C1.
The data is read by referring to any data of R (CH1), and the result is written in the code data memory BC1. CODI
The internal bus DMA control unit 30 reads data from the NG line memory and writes data to the BC1 line memory.
Performed through 0. The operation of the internal bus DMA control unit 300 is the same as the case of data transfer from the image bus control unit 100 to the RAM 200.

The changed pixel address of the encoded line is detected by the changed pixel detecting section 800, and the changed pixel address of the reference line is detected by the changed pixel detecting section 600.
When the encoding of one line is completed, the A flag of the BC1 address register is set to "1". The reference line is updated by exchanging the contents of the CODING address register and the address counter C0R (CH0) or C1R (CH1). The microprogram is a process 2013,
When the end of encoding and the vacancy of the BC line memory are confirmed in 2014, the address registers BC1 and B1 are processed in processing 2015.
By exchanging the contents of C, the line memory BC
1. The data of BC is transferred.

In process 2016, code data is output from the BC line memory to the system bus 10 by DMA transfer. At this time, it is necessary to know the code amount to be output, but at the end of encoding, the counter 152 in the encoder 1500
The code amount can be known by referring to the contents of 2 (FIG. 3). In step 2017, it is determined whether or not the encoding of the set number of lines has been completed. If not, the process returns to step 2002.
If the encoding is completed, the process of the encoding command is completed after waiting for all the code data to be output outside in step 2018. The end of the encoding command is determined by whether or not the encoding of the final line with the C flag set to "1" has been completed. The state of the C flag propagates through the address register as follows. INPUT, C = 1 → CONVR, C = 1 If C = 1 in CONVR, after the image conversion is completed CONV
W, C = 1 → CODING, C = 1 (Summary of compression operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, the image data input process (process 2004), image conversion process (process 2008), encoding process (process 2012), and code data output process (process 2016) are performed in parallel. Operate. Further, in parallel with this, DMA transfer (process 2002, process 2003) on the image bus side can be performed. Therefore, the compression processing time of the main compression / expansion device 1 can be approximately expressed by the following equation. Processing time = max {image input time, image conversion time, encoding time, code output time} (Equation 2) FIG. 18 shows how to use the line memory in the encoding command processing. As can be seen from this figure, the line memories INPUT and CONVR are used in a toggle, the line memories CONVW, CODING and C0R / C1R are used in a circulating manner, and the line memories BC1 and BC are used in a toggle. When the main scanning conversion is not performed, the data in the CONVW line memory is directly transferred to the CODING line memory, as shown in FIG. Further, although the image data is input from the image bus 11 side in the above description, the compression / expansion device 1 can also input the data to be encoded from the system bus 10 as shown in FIG. Similarly, in the above description, the encoded data is RA
Although it is output to the system bus 10 via the M200, it is also possible to directly output to the system bus 10 from the encoder 1500.

(Outline) MPU of the processor block 13
First, various registers for decoding command processing are set. In this, decoding channels 0, 1 (CH
0, CH1) designation is also included. After the completion of this register setting, the MPU writes the decryption command in the command register 402A or 404A in the system bus control unit 400. This command is decoded by the macro ROM 1608 and the start address of the decoding program is output. The decoding program in the micro ROM 1601 is executed from this address.

As already described, the line memory 216 and the address register 502 defined in the case of the decoding command processing are as shown in FIG. The contents or roles of each line memory are as follows. DECODE: Image data of restored line D0R: Image data of reference line for decoding channel 0 D1R: Image data of reference line for decoding channel 1 CONVR: Image data of line before conversion CONVW: Image data of line after conversion OUT2: Output Line buffer OUT1: Output line buffer OUT: Output line buffer Code data is line memory D0R (CH0) or D1
The data restored by decoding with reference to the data of R (CH1) is expanded in the DECODE line memory. When the decoding of one line is completed, the contents of the DECODE line memory are transferred to the line memory D0R or D1R and are referred to when decoding the next line. At the same time, the contents of the line memory D0R or D1R are stored in the line memory CONV.
It is passed to R for image conversion. Image conversion is CO
This is performed for the data in the NVR line memory, and the converted image data is written in the CONVW line memory.

The converted data in the CONVW line memory is OU immediately after the OUT2 line memory is empty.
Passed to T2 line memory. The data in the OUT2 line memory is immediately transferred to the OUT1 line memory if the OUT1 line memory is empty. If the OUT line memory is empty, the data in the OUT1 line memory is
Immediately, this data is output to the OUT line memory and output to the outside. In this way, CONVW, OUT2, OU
Each T1 and OUT line memory is a line-by-line FIFO
Acts as a buffer. (Description along FIG. 19) FIG. 19 shows an example of the flow of the decryption program. The decryption command processing will be described along this flow. In process 3001, as an initial setting,
RAM 200 for parameters required for decryption command processing
The working register 500 is loaded from the parameter register set 202 (CH0) or 204 (CH1) in the inside.

One line is decoded in the process 3002, which will be described later in detail with reference to FIG.

In process 3003, the A flag of the DECODE address register is checked to determine whether the restoration of one line is completed. In process 3004, it is determined whether the CONVR line memory is empty. DECODE
If A = 1 of the E address register and A = 0 of the CONVR address register, the address register CONVR and the address register D0R or D1R are processed in processing 3005.
Of the address register D0R or HD1R and the address register DECODE in processing 3006.
The contents of are exchanged and data is exchanged between line memories. As a result, the line memory D0R or D1R
The data you just restored is now crossed and you are ready to restore the next line. The data that has been used as a reference line is passed to the CONVR line memory, and the memory area of the data that has been converted is passed to the DECODE line memory. Now you are ready to restore the next line and the next image conversion.

In steps 3007 and 3008, the presence / absence of data to be converted and the availability of the CONVW line memory are checked. In process 3009, the image conversion unit 1400 performs image conversion in the main scanning direction. The contents of this process are the same as the process 2008 of FIG. Further, when sub-scanning direction conversion is necessary, thinning line determination and flag control are performed subsequent to main scanning conversion, the details of which will be described later.

Process 3010 is control of the line buffer. The details will be described later with reference to FIG. Processing 30
At 11, the presence or absence of data to be output is checked. Process 3
At 012, the data of the OUT line memory is externally output. In processes 3013 and 3014, D on the image bus side
When there is a request for MA transfer, the transfer process is performed.
This is the same as the processes 2002 and 2003 shown in FIG.

In step 3015, the end of the decryption command is determined, and if the end condition is not satisfied, step 3002
Return to The conditions for ending the decryption command are as follows. (1) Decoding processing for the set number of lines has been completed (2) RTC code has been detected (3) Decoding error has been detected in MMR decoding processing The data transferred to the CONVR line memory in preparation for the conversion command is returned to the line memory D0R or D1R.

(Description along FIG. 20: 1-line decoding)
FIG. 20 is a flow of the 1-line decoding process 3002 of FIG. In process 3101, the status signal indicating that the decoder 1300 is in operation is checked. If it is not in operation, in step 3102, the decoder 13
Check the start flag of 00. If it is confirmed that the startup flag is set (started), process 31
03, and if the activation flag is reset, proceed to processing 3115. When the decoder 1300 is in operation, it immediately returns.

The processing flow when the decoder 1300 is not in operation is as follows. In process 3115, the decoder 13
In order to prepare for starting 00, the address counter A and the address counter I or J in the internal bus control unit 300 are
Address register DEC on working register 500
The contents of ODE and address register D0R or D1R are loaded respectively.

Thereafter, these address counters are automatically incremented each time one word is accessed in response to a DMA transfer request from the decoder 1300, and a write address of the restored data and a read address of the reference line data are designated. In process 3116, the number of words of one line is set in the register 1324 of the decoder 1300 and the internal register (not shown) of the reference line change pixel detection unit 600. After such preparation, the decoder 1300 is activated in step 3117 and the decoder 1300 is started in step 3118.
Set the start flag of "1" to "1" and return. The above is the line head processing.

After the process 3103, the decoder 1300 is set to 1
The data for the line is decrypted and the restored data is DECODE
It is a processing part after being obtained in the line memory. Process 31
In 03, the activation flag set in process 3118 is reset. The process 3104 checks the status signal of the decoder 1300, which indicates whether there was a decoding error. If there is a decryption error, a decryption error process is performed in process 3119. For example, a process of replacing the line having an error with the immediately preceding line or the white line is performed. If there is no decoding error, error-free data has been restored in the DECODE line memory, and therefore processing 3105 is performed to indicate this.
The A flag of the DECODE address register is set to "1".

In the process 3106, the status signal of the decoder 1300 indicating that the restored line is a white line (all pixels are white) is checked. Each time the decoder 1300 restores one word, the comparator 1320 (FIG. 4) checks whether or not the data is white data, and when one line is decoded, it is determined from the status signal that the line is a white line by a microprogram. You can check on the side. If it is a white line, process 31
At 07, increment the counter for counting the continuous white lines at the top of one page or the counter for counting the continuous white lines at the bottom of the page (any counter is provided on working register 500) To do.

In step 3108, the status signal of the decoder 1300 indicating whether the RTC code is detected is checked. In process 3109, it is determined whether to output the restored data to the outside. This judgment is made by register set 402 (CH0) or 40 in the system bus control unit 400.
4 (CH1) by referring to a specific register. The contents of the bits of this register are set by the MPU of the processor block 13. If it is a line that is not output, in step 3110, DECODE
The B flag of the address register is set to "1". B
When the data is output to the line for which the flag is set, the data is ignored and is not output to the outside. By such control, it is possible to perform control such that the MPU side cuts the white line at the upper end or the lower end of the page.

In process 3112, the number of lines to be continuously processed set by the MPU is decremented to obtain the number of remaining lines. Then, in process 3113, the number of remaining lines is checked, and if it is 0, then in process 3114 DECO
Set the C flag indicating the last line of the DE address register to "
Set to 1 ″. If the number of remaining lines is not 0, the process immediately returns.
Is incremented. With this counter value, the number of lines on one page can be obtained. The number of lines can be set in the RAM2 by the microprogram when the processing of one page is completed.
00 in the decoding command parameter register area 210 for the corresponding channel. This area can be directly accessed from the MPU.

(Description of FIG. 21: Line Buffer Control) FIG. 21 is a flowchart of the process 3010 (line buffer control) of FIG. In processes 3201 and 3202, CO
After confirming that A = 1 of the NVW address register and A = 0 of the OUT2 address register, the contents of the address registers CONVW and OUT2 are exchanged in process 3203.

As a result, the data in the CONVW line memory enters the OUT2 line memory, and the empty area extends to the CONVW line memory. The flag states of the address register are A = 1 for OUT2 and A = 0 for CONVW.

Data exchange between the line memories OUT2 and OUT1 is performed in processes 3208, 3204 and 3205.
Line memory OU in processing 3209, 3206, 3207
Data is exchanged between T1 and OUT. Process 3207
The A flag of the OUT address register is set to "1". With the above processing, CONVW, OUT2, OUT
Each of the line memories 1 and OUT is used as a line-by-line FIFO buffer.

(Description According to FIG. 22: Image Data Output)
FIG. 22 is a flow of the image data output process 3012 of FIG. In process 3301, the image bus control unit 3301
Check whether or not is in operation, and if it is in operation, return. If it is not operating, it is checked in process 3302 whether the activation flag of the image bus control unit 100 is set. If the activation flag is "1", it means that the image bus control unit 100 has been activated and is not in operation. Therefore, the process proceeds to the line end process of process 3311 and thereafter.

If it has not been started, the line head processing is started. In processing 2303, the B flag of the OUT address register is checked to determine whether to output the data of the OUT line memory. If the B flag is not "1", the data is data to be output, so preparation for output by the DMA transfer is made. First, in process 3304, the start address is loaded from the OUT address register into the address counter 302 corresponding to the OUT line memory in the internal bus DMA control unit 300. In processing 3305, the image bus control unit 1
External RAM 2 in one of the address counters 104 in 00
Set 8 addresses. In process 3306, the number of words in the output line is set in one of the transfer word number registers 114 in the image bus control unit 100. In process 3307,
The operation mode of the image bus control unit 100 is set. Here, the memory write mode is set. Then, in process 3308, the image bus control unit 100 is activated. In process 3309, the start flag in the memory write mode of the image bus control unit 100 is set to "1", and the process returns.

If the B flag is "1" in the process 3303, the data is not output, and the A flag of the OUT address register is reset to "0" in the process 3310 to ignore the contents of the OUT line memory. . Line thinning is achieved by this processing. The process 3311 and subsequent processes are line end processes. In process 3311, the activation flag of the image bus control unit 100 set in process 3309 is reset. In process 3312, the E flag of the OUT address register is checked to determine whether the output line is the enlargement target line in the sub-scanning direction. If the line is not the enlargement target line (E = 0), the second output of the data in the OUT line memory is unnecessary, so the process 33
At 13, the A flag of the OUT address register is set to "0", and the OUT line memory is released. If the line is an enlargement target line (E = 1), the E flag of the OUT address register is reset in process 2314. The A flag is "
1 ″, this data is output again, and as a result, enlargement in the sub-scanning direction (line interpolation) is achieved. In process 3315, the external RA is output to output the next line.
Update the address of M28 and return.

The determination of the end of the decoding command is made based on whether or not the data in which the C flag is set to "1" is output. The C flag (final line flag) is propagated as follows by exchanging the address register. DECODE, C = 1 → CONVR, C = 1 CONVR, C = 1 after image conversion is completed CONV
W, C = 1 → OUT, C = 1 (Summary of decompression operation) As described above, the internal RA
After the line memory on the M200 is clogged with data, a decoding process (process 3002) and an image conversion process (process 300) are performed.
9), the image data output process (process 3012) operates in parallel. Further, DMA transfer processing on the image bus side (processing 3
013, process 3014) can also operate in parallel with this.

Therefore, the expansion processing time of the compression / expansion device 1 can be approximately expressed by the following equation. Processing time = max {decoding time, image conversion time, image data output time} (Equation 3) FIG. 23 shows how to use the line memory in the decoding command processing. As you can see from this figure, DECOD
The E, D0R / D1R, and CONVR line memories are cyclically used, and CONVW, OUT2, OUT1, and O are used.
Each line memory of the UT is also used cyclically.

Description of Code Conversion Operation Next, the code conversion operation will be described. This code conversion is to input a certain code data and convert it to another code data. For example, conversion from MR code to MMR code.

In the case of the code conversion operation, the code data to be converted is input from the system bus 10, decoded by the decoder 1300, and the restored data is written in the DECODE line memory. By the decoding operation already described, C
The data in the ONVR line memory is converted into an image. Up to this point, the decompression operation is exactly the same. After that, CONVW
The data in the line memory is the target of encoding. After that, the compression operation is exactly the same.

The above decoding, image conversion, and coding processes can be repeated in order for each line to convert the code data for one page into another code.

In the case of this code conversion processing, the address register 502 and the line memory 216 shown in FIG. 12 are defined as already described. FIG. 25 is an explanatory diagram of how to use the line memory.

FIG. 24 is a flow of the code conversion program. Since the processes having the same numbers as those in the flow of FIG. 16 or FIG. 19 have the same contents, the description thereof will be omitted. The following can be easily understood from the flow of FIG. a) Decoding process, image conversion process, encoding process, and two DMA transfer processes on the image bus side operate in parallel. b) Even if a decoding error occurs, the decoding error is checked and the decoding error process (process 3119 in FIG. 20) is performed in the 1-line decoding process (process 3002). The conversion is performed. Therefore, the coded data after conversion does not include a decoding error. In the code conversion operation or decompression operation, the number of lines in one page and the number of continuous white lines at the upper and lower edges of the page are obtained in the decoding process (process 3002) (processes 3120 and 3107 in FIG. 20), and the operation ends. At this point, it is stored in the decryption command parameter register area 210 on the RAM 200. MPU reads these parameters,
It can be used to determine the scaling ratio and cut lines at the top and bottom edges of the page.

Description of image conversion (reduction) in the sub-scanning direction Reduction in the sub-scanning direction is realized by thinning out one line every constant number of lines, and enlargement in the sub-scanning direction copies one line every constant number of lines. It is realized by (interpolation).
Here, the reduction operation in the sub-scanning direction will be described in detail centering on the method of determining thinning lines.

FIG. 26 is a conceptual diagram of the processing of the sub-scanning direction conversion operation. Related parameters (working register 5
00 are provided in the registers 551 to 557 prepared as follows) (however, for channel 0). C0-VCONV (sub-scan conversion rate): register 551 C0-VCWRK (work register): register 552 CONVW Each time valid data of one line is obtained in the line memory, 16-bit ALU 1202 is used to C0-VCON
V is integrated. This integrated value is C0-VCWRK. The line in which the carry occurs when the ALU 1202 overflows when integrated is the target of thinning.

The carry of the 16-bit ALU 1202 comes out once every 65536 / (C0-VCONV) lines. If M = 65536 / (C0-VCONV), one line is thinned out to M lines on average, and the reduction ratio R is R = (M-1) / M = 1- (1 / M).

From this relationship, the MPU of the processor block 13 determines C0-VCONV from the reduction ratio R and sets this value in the compression / expansion device 1.

FIG. 27 (a) is an explanatory view of the integration process of C0-VCONV, which is the image line and the integrated value C0 on each line.
-VCWRK is shown side by side. In the example shown here, since carry occurs on the fifth line, this line is set as a thinning line.

Such an algorithm is conventionally known. Note that the determination of the copy line in the case of enlargement in the sub-scanning direction can also be performed by the same algorithm, and the integration process is shown in FIG. 27 (b). Fifth
Since the carry appears on the line, the fifth line becomes the expansion target line. In the case of the enlargement process in the encoded command, this line is encoded twice.

Coordination of Command Processing and DMA Transfer Processing Next, based on the above description of operation, the decoding processing will be described for the internal processing of the compression / expansion device such as encoding and decoding and the cooperation processing of DMA transfer of image data. Will be described as an example.

Generally, in a facsimile machine, a series of processes for restoring the received encoded data and transferring the decoded data to the recording unit is performed by using a two-sided buffer memory as shown in FIG. Writing the decoded data to the buffer memory and reading it from the buffer memory by DMA transfer are executed by using different buffer memories as toggles. That is, assuming that the memory capacities of the buffer A and the buffer B are L lines, first, the image data of L lines is restored and written in the buffer A. When the write operation of the buffer A is completed, the DMA transfer of the data of the buffer A is started.
At the same time, the decoding operation moves to the buffer B. By repeating this, the image data for one page is decoded and the DMA transfer is performed.

In this method, the MPU DMs every L line.
It is necessary to give instructions to the compression / expansion device for the decoding process and the DMA transfer (issue macro command) while synchronizing the A transfer process and the decoding process. Further, in general, the number of restored lines of one page is not a multiple of the buffer size L lines, so in the page edge processing after detecting the RTC code, the number of lines of image data written in the buffer memory is calculated, Exception processing such as resetting the number of transfer lines must be executed.

As another method, the buffer memory on one side is cyclically used so that the write address pointer indicating the data write position and the read address pointer indicating the data read position do not overtake each other. There is a method. When this method is applied to the compression / decompression device of this embodiment, the two address pointers are both MP
U will manage it. In order to prevent two address pointers from overtaking each other, the MPU activates the compression / decompression device when a free area of one line or more is created in the buffer memory, and when DMA transfer accumulates one or more lines of data, transfers the data. Need to control to start. In this method, since the address pointers do not pass each other over each other, it is difficult to control the continuous write and read operations over a plurality of lines to the buffer memory, and basically write data for each line. And will control the reed. Therefore, the control load of the MPU is greater than that of the two-sided buffer switching method, and the activation waiting time of the compression / expansion device is also increased accordingly.

Assuming a process of previously accumulating one page of encoded data in the memory and restoring and recording the encoded data at high speed, no matter how the decoding process of the compression / expansion device is speeded up, every L line, or A command waiting time is generated for each line, and the processing time can be suppressed from below by the sum of the waiting times. Therefore, reducing the processing load of the MPU on the compression / decompression device is an essential issue to be solved for high-speed processing.

(Description of this system) FIGS. 29 to 32 are conceptual diagrams of a buffer memory control system of this system. First, the outline of the operation will be described. FIG. 29 shows a memory area for the DMA channel 1 provided inside the RAM 28. T
1-MTOPA, T1-MENDA, T1-WPOIN
T and T1-STRA are parameter register areas 2
14 (FIG. 8). T1-MTOPA and T1-MENDA are the start address and end address of the memory area, and this range is cyclically used as a line buffer. T1-WPOI
NT and T1-STRA are two address pointers. T1-WPOINT is a write address of the memory, and in the decoding command, one line of the restored image is written from the position of T1-WPOINT. On the other hand, T1-
STRA indicates an address for reading data from the memory, and the DMA channel 1 reads data for one line from the address of T1-STRA. The predetermined value shown in FIG. 29 is set in advance in the parameter register 2 like other parameters.
Register value defined in No. 14, T1-WPOIN
It represents the minimum distance between T and T1-STRA.

Using the parameters thus defined, the microprogram of the compression / expansion device 1 executes T1-
The DMA transfer process and the decoding process are cooperatively controlled so that the WPOINT and T1-STRA do not overtake each other. The shaded area between T1-WPOINT and T1-STRA is untransferred data.

FIG. 30 shows the temporal variation of the untransferred data amount DSIZE in the line buffer. t
1, t2, etc. indicate the timing of activating the DMA transfer. The micro program calculates DSIZE when activating a DMA transfer of image data, and when it is smaller than a predetermined value and smaller than the previous DSIZE, MP is calculated.
An interrupt (IRQ) is generated for U. The reason will be described later. The interrupt generation condition is a case where the following two conditions are both satisfied.

DSIZE ≦ predetermined value ΔDSIZE <0 Here, ΔDSIZE is a difference value between the untransferred data amount calculated this time and the untransferred data amount calculated last time. Therefore, as shown in the figure, an interrupt is generated at ti and ti + 1, but at ti + 2, an interrupt is not generated because ΔDSIZE> 0. In this way, when the amount of untransferred data inside the line buffer matches the above two conditions, the MPU performs interrupt processing, so that the data to be read in the middle of the processing can be processed without much load on the MPU. It is possible to prevent the data from being lost and to efficiently perform the writing and reading processing of the line buffer.

34 to 37 are flow charts of the microprogram for the above processing. The cooperation between the decoding process and the DMA transfer process will be described in detail with reference to these figures.

(Description According to FIG. 34: Image Bus DM
A transfer processing channel 1) FIG. 34 shows processing 301 of FIG.
4 (image bus DMA transfer processing channel 1) is shown. A process 4001 checks whether the MPU issues a DMA transfer request. DMA channel 1
The transfer request signal is a bit provided in a register inside the CH1 register set 404 (FIG. 7) of the system bus control unit. The MPU activates DMA transfer by setting this bit to "1". In process 4002,
The status signal of the image bus section showing that the DMA channel 1 is operating is checked. A process 4003 checks whether or not a flag bit indicating that the image bus unit is activated in order to start the transfer of the DMA channel 1 by the microprogram is ON. This flag bit is set inside the working register 500. Process 400
2 and processing 4003, it is determined whether the line transfer is started or ended.

Process 4004 is process 4005, 4006.
Is a judgment to make only once at the beginning of block transfer, and the flag set inside is checked. Processing 40
05, processing 4006, and processing 4007 are line transfer start processing. In process 4005, the number of transfer words for one line is set in the transfer number register 114 (FIG. 9) of the image bus unit. In process 4006, the MPU sets the parameter register 2
The number of transfer lines preset to 14 (FIG. 8) is loaded into the working register 500. Processing 40
Reference numeral 04 is a check of the internal flag bit for setting only once in one transfer unit. In process 4007, DM
Set the start address T1-STRA of the A channel 1. As will be described later with reference to FIG. 35, the image bus unit is activated inside this process.

When the activation flag is 1, that is, when the transfer of one line is completed, the processing proceeds to processing 4008 and thereafter.
The process 4008 and subsequent processes are line transfer termination processes. A process 4008 resets the activation flag set in the process 4003. In process 4009, each time one line is transferred,
The number of transfer lines loaded in the process 4006 is decremented. A process 4010 is to judge whether or not the transfer of the number of lines to be transferred (block transfer) is completed. When the block transfer is completed, in process 4011 an interrupt indicating that is issued to the MPU. A process 4012 updates the start address every time one line is transferred.

FIG. 35 is an operation flow chart for explaining the process 4007 more specifically. Process 4101 is MP
The method of controlling the buffer memory designated by U is determined. The method described with reference to FIGS. 29 to 33 is referred to as pointer control here, and is limited to this case below. In process 4102, it is determined whether the two address pointers match. In process 4103, the amount of data in the buffer DSIZE
Is calculated. The process 4104 is the image bus control unit 100.
The start address T1-STRA of the DMA transfer is set to the start address 110 (FIG. 9) of FIG. Process 4105
Instructs the image bus control unit to start the DMA channel 1 operation. Since the operation of the DMA channel 1 is started by the process 4105, the internal flag indicating this is set in the process 4106. This flag is processed 400
Checked in 3.

If the pointers match in process 4102, the process moves to processes 4107 and 4108 to determine whether the pointers match due to buffer full or match in the initial state. In the buffer full state, the pointer is in the state shown in FIG. 30, for example, and in the initial state it is in the state shown in FIG. In the buffer full state (FIG. 30) in which T1-WPOINT has overtaken T1-STRA, DMA transfer can be activated, and the process proceeds to step 4104. Process 41
In the initial state (FIG. 31) as determined by 08, the transfer data is not yet accumulated in the buffer, so that the DMA transfer is not started. When it is neither buffer full nor initial state,
The decryption process is completed, and T1-STRA becomes T1-WPOI.
Process 410 because it has caught up with NT (FIG. 32)
At 9, an interrupt indicating that is issued to the MPU.

The identification of the buffer full state, the initial state, the decoding command end state, etc. can be performed by referring to an appropriately set internal flag. FIG. 36 shows the internal processing of the processing 3308 in the image output processing flow shown in FIG. FIG. 35 shows the read pointer T-STR.
In contrast to the control of A, FIG. 36 shows the control of the write pointer T1-WPOINT.

Process 4201 is similar to process 4101. If the two pointers do not match in processing 4202, T1-WPO is added to the image bus section in processing 4203.
The INT is set, and the process 4204 is activated. Process 420
If the pointers match with each other in step 2, it is determined in step 4205 whether or not it is in the initial state. If it is not the initial state, T1-WPOINT has caught up with T1-STRA, and the image output operation is stopped because there is no free area in the buffer memory. If the address pointer is separated when the DMA transfer process proceeds and the microprogram next performs the process 4202, the image output operation is activated through the process 4203 at that time. The value of the write pointer T1-WPOINT is set to the processing 3315 (FIG. 2) each time the data output of one line is completed.
Updated in 2). (Stopping and Resuming Decoding Process Accompanying Stop of Image Output Operation) If the process 4205 is not in the initial state, the image bus operation is not started, so the image output operation is temporarily stopped. The stop of the image output operation means that the data in the OUT line memory shown in FIG. 23 is not read. When the image output operation is stopped, FIG. 21 and FIG.
As can be seen from 2, the A flag of CONVW is in the "1" state, and the main scanning conversion process is in the waiting state. Then, the A flag of CONVR remains "1", as shown in FIG.
Since the processing 3005 and the processing 3006 are not executed, DECODE and A = 1 remain. Therefore, the decoder is not activated by the determination of the process 3121 in FIG. 20, and the decoding process is temporarily stopped.

However, as shown in FIG. 23, since the line memory between the OUT line memory and the DECODE line memory functions as a line buffer, stopping the output operation does not lead to stopping the immediate decoding operation. When the image output operation is restarted and OUT and A = 0 and the internal line memory becomes empty, DECODE and A = 0 are set, and the decoding process is restarted. This decoding process is stopped and restarted by the A flag being propagated only by the data exchange process between the line memories, and as a result, the data flow is controlled.

The code data for one page re-encoded by the code conversion process (FIG. 24) is stored in the memory 16 (FIG. 2).
Stored in the MPU, the MPU can know the number of restored lines of one page before starting decoding.
The number of lines is set in the decoder and a decoding command is issued. When the decoding processing for the set number of lines is completed, T-POINT stops as shown in FIG. 32, and T1-ST
RA catches up with it, and processes 4102 and 4 in FIG.
The DMA transfer is also completed through 107, processing 4108, and processing 4109. Thus, by issuing the decryption command once, the decryption of one page and the DMA transfer to the recording unit can be executed.

When the coded data is received from the communication line, or when the received coded data for one page is stored in the memory and then decoded and transferred to the recording unit, the number of lines of one page is decoded. Although it is unknown at the start of conversion, since the page size and resolution are known through the communication procedure, the MPU sets the number of processing lines in the decoder to be several times larger than the actual number. In this case, the process 3108 of FIG.
According to the determination of RTC code detection, the C flag indicating the end of the decoding process is set in the process 3114, and the decoding command ends in the process 3015 of FIG. When the decryption command ends, T-WPOINT stops, so T1-STRA catches up with it and process 4 in FIG.
The DMA transfer is also completed through 102, processing 4107, processing 4108, and processing 4109. Even in this case, the MPU
By issuing the decryption command once, the decryption of one page and the DMA transfer to the recording unit can be executed.

FIG. 37 shows the inside of the process 4103. This processing is related to the time-division multiplexing processing for switching the encoding / decoding multiple channels in line units, which will be described below. In process 4301, the untransferred data amount D in the buffer
Calculate SIZEi. The subscript i indicates the calculated value at the time of starting the DMA transfer of the i-th line. In process 4302, the calculation result is stored in the register inside the working register 500. In processing 4303, it is determined whether the first condition of Expression 4 is satisfied. If so, processing 4304 determines in DSIZE.
The difference value of is calculated, and in process 4305 it is determined whether the second condition of Expression 4 is satisfied. If the condition of Expression 4 is satisfied, an interrupt indicating that is issued to the MPU in process 4306. As can be seen from FIG. 35, the DMA transfer does not stop even if the interrupt is issued in the process 4306.

The decoding process and the DMA transfer process have been described above as examples. In the case of encoding processing, DMA channel 0
Since the write pointer of 1 precedes and the read pointer of encoding follows it, the relationship of the address pointer is opposite to that in the case of decoding, but the same can be realized. Also,
These processes are not limited to the above command processing contents because they have a relationship of read / write of the buffer memory for command processing inside the compression / expansion device and DMA transfer between the input / output device and the buffer memory.

Buffer Memory Control and Time Division Multiplexing Processing It has already been described that the compression / expansion device 1 can execute two channels for each of the encoding processing and the decoding processing. MPU is
By combining these channels, the compression / expansion device 1 can be made to execute the time-division processing on a line-by-line basis.

FIG. 35 shows an embodiment of time division multiplexing processing using the compression / expansion device 1. Here, an example of time division processing of the code conversion processing and the decoding operation is shown. Encoding / decoding Channel conversion is performed on channel 0, and decoding is performed on channel 1 side. In the figure, is a code conversion operation, in which the code data accumulated in the compressed data memory 16 is decoded (), and if necessary, image conversion processing is performed to code and stored again in the compressed data memory 16 (). In the figure, in the code conversion process of, the code data stored in the compression memory is already decoded and written in the line buffer # 1 provided in the RAM 28. Is a DMA transfer process from the line buffer. The cooperation of the processes of and is as described above.

It is assumed that the processing of FIG. 35 is executed by the facsimile machine shown in FIG. Since data is supplied to the LBP 29, it is assumed that a constant speed is required for the transfer and the page cannot be stopped. Moreover, RAM28
Is a line buffer, and page memory is not used. In such a situation, the priority of the transfer process is highest.

In the conventional compression / expansion apparatus, even if the decoding speed of one line is always higher than the recording speed of one line of LBP29, the code conversion and decoding are performed in order to execute the above processing. A plurality of compression / decompression devices 8001 and 8002 (FIG. 39) are required for this.

The decoding of the compression / expansion device 1 is designed so that it can be executed at an average processing speed of about 10 times the recording speed of the LBP by the means already described. Therefore, T1-WPOINT shown in FIG.
On average 10 times faster than TRA, T1-STR
Catch up with A and the buffer is full. Although not shown in the flowchart, the MPU can easily notify this state by means such as an interrupt. In this state, the MPU interrupts the decoding process, issues a code conversion command to the compression / expansion device 1, and switches the processing content. Since the transfer of FIG. 35 is stopped during the execution of the code conversion process, T1-STRA is set to T1-WPOI.
Approaching NT. When the condition of Expression 4 is satisfied, the MPU receives an interrupt from the compression / decompression device 1 and
Know that the transfer data has decreased in the buffer.

The MPU interrupts the code conversion processing at an appropriate timing and issues a decoding command. When decoding starts, the amount of data in the buffer starts to increase. In this case, even if the amount of data is less than or equal to the predetermined value, the difference value becomes positive, and the underflow of the buffer memory is avoided, so no interrupt is issued.

The MPU can execute the time-division processing of code conversion and decoding by repeating the above processing. Formula 4
The predetermined value of is to secure the time required from the MPU receiving the interrupt until the command is switched. This value may be determined based on a value obtained by dividing the command switching processing time by the one-line decoding time of the compression / expansion device 1.

The present invention is not limited to the embodiments described above. According to the present invention, it is possible to realize an apparatus that performs at least one of compression, decompression, and code conversion at high speed. Further, the compression / expansion device according to the present invention is most suitable for an image communication device represented by a facsimile device, but is also suitable for an image file system and other similar image processing applications in a system or device. It should be noted that although the writing to the memory and the DMA transfer after the decoding processing are described in the present embodiment,
It goes without saying that it can also be used for writing to the memory after reading a document, encoding processing after reading, and recording processing.

[0125]

As is apparent from the above description, the present invention has the following effects.

By the command processing such as encoding, decoding and code conversion and the cooperative processing of the DMA transfer of the image data, M
One page of image data can be processed by issuing one command from the PU.

By the cooperative processing of the command processing and the DMA transfer, the processing load of the MPU can be reduced, the command waiting time of the compression / expansion device can be shortened, and the high speed processing can be performed.

The compression / expansion device detects the remaining amount of the buffer memory, and when the value becomes a predetermined value or less, it has means for notifying the MPU, so that the underflow control of the buffer memory can be easily performed. Further, when a plurality of processes are being executed, when one of the image processes is informed, the MPU switches to the other image process and performs the process, so that the plurality of image processes can be efficiently realized. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a compression / decompression device according to the present invention.

FIG. 2 is a block diagram showing an example of a facsimile apparatus using the compression / expansion device according to the present invention.

FIG. 3 is a block diagram of an encoder.

FIG. 4 is a block diagram of a decoder.

FIG. 5 is a block diagram of an image converter.

FIG. 6 is a block diagram of an arithmetic logic operation unit and its peripherals.

FIG. 7 is a block diagram of a micro program control unit and a system bus control unit.

FIG. 8 is an explanatory diagram of how to use the internal RAM.

FIG. 9 is a block diagram of an image bus control unit.

FIG. 10 is a line memory for processing encoded commands,
Illustration of address counter and address register

FIG. 11: Line memory for decoding command processing,
Illustration of address counter and address register

FIG. 12 is an explanatory diagram of a line memory, an address counter, and an address register for processing a code conversion command.

FIG. 13 is a diagram showing the contents of an address register.

FIG. 14 is a diagram showing a state before executing data transfer between line memories.

FIG. 15 is a diagram showing a state after data is transferred between line memories by exchanging contents of address registers.

FIG. 16 is a flowchart of a compression operation.

FIG. 17 is a flowchart for inputting image data.

FIG. 18 is a diagram showing usage and data flow of a line memory during compression operation.

FIG. 19 is a flowchart of a decompression operation.

FIG. 20 is a flowchart of 1-line decoding.

FIG. 21 is a flowchart of line buffer control.

FIG. 22 is a flowchart of image output.

FIG. 23 is a diagram showing how the line memory is used and the data flow during decompression operation.

FIG. 24 is a flowchart of a code conversion operation.

FIG. 25 is a diagram showing how the line memory is used and the data flow during a code conversion operation.

FIG. 26 is an explanatory diagram of parameters for image conversion in the sub-scanning direction.

FIG. 27 (a) is an explanatory diagram of a thinning line determination method for reducing the sub-scanning direction, and (b) is an explanatory diagram of a thinning line determination method for expanding the sub-scanning direction.

FIG. 28 is an explanatory diagram of a conventional buffer memory control method.

FIG. 29 is an explanatory diagram of a buffer memory control method by the compression / expansion device of the present invention.

FIG. 30 is a diagram showing a state where the pointers match when the buffer is full.

FIG. 31 is a diagram showing a state where the pointers match in the initial state.

FIG. 32 is a diagram showing a state in which T1-STRA catches up after the decoding process.

FIG. 33 is a diagram for explaining fluctuations in the amount of data in the buffer memory.

FIG. 34 is a flowchart of DMA transfer.

FIG. 35 is a flowchart showing the subroutine of FIG. 34.

FIG. 36 is a flowchart showing the subroutine of FIG. 35.

FIG. 37 is a flowchart showing a method for checking the buffer amount.

FIG. 38 is an explanatory diagram of time division multiplexing operation.

FIG. 39 is a block diagram showing an example of a conventional facsimile apparatus.

FIG. 40 is a block diagram of a conventional compression / expansion device.

[Explanation of symbols]

 1 Compression / Expansion Device 10 System Bus 11 Image Bus 13 MPU 16 Compressed Data Memory 21 Read Image Processing Unit 22 Recorded Image Processing Unit 28 RAM 102 DMA Controller 104 Address Counter 200 Internal RAM 216 Line Memory

Claims (6)

[Claims] 1. A processing means for executing specific image processing on image data, a storage means for storing image data output from the processing means for each predetermined unit, and writing of the image data to the storage means, and A means for reading out image data from the storage means, a detection means for detecting the image data remaining in the storage means, and the remaining image data is less than or equal to a predetermined value set in advance and decreased from the previous detection value. An image processing apparatus having a means for occasionally notifying this to an external device. 2. A second predetermined value, which is a value smaller than the predetermined value, is set, and the reading of the image data is stopped when the remaining image data reaches the second predetermined value. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. 3. A reading unit for reading a document and outputting image data, a storage unit for storing image data output from the reading unit in predetermined units, and an image output in predetermined units from the storage unit. Processing means for encoding the data, detecting means for detecting the image data remaining in the storage means a plurality of times within a page unit, and the remaining image data is less than or equal to a predetermined value, and more than the previous detected value. An image processing apparatus having means for notifying an external device of the decrease. 4. Processing means for restoring coded image data, storage means for storing image data output from the processing means in predetermined units, and images output from the storage unit in predetermined units. Recording means for printing data, detection means for detecting image data remaining in the storage means a plurality of times within a predetermined unit, and remaining image data is less than or equal to a predetermined value that has been previously determined, and less than the previous detected value. An image processing apparatus having means for notifying an external device of this when the above. 5. A processing means for restoring encoded image data, a storage means for storing image data output from the processing means for each predetermined unit, and writing of the image data to the storage means and the storage. A means for reading out image data from the means, a detecting means for detecting the image data remaining in the storage means, and a remaining image data which is equal to or less than a predetermined value and which is smaller than the previously detected value. And a means for notifying this to an external device, wherein the processing means stops the restoration processing when the RTC signal is detected from the restored image data. 6. A first processing means for performing specific image processing on image data, a second processing means for performing image processing different from the first processing means, and the first processing means. Storage means for storing image data output for each predetermined unit, means for writing image data to the storage means and reading image data from the storage means, and detecting image data remaining in the storage means Detection means,
An image having means for switching the execution of the image processing from the first processing means to the second processing means when the remaining image data is equal to or less than a predetermined value and which is smaller than the previous detected value. Processing equipment.