JPH08124795A - Multilayered capacitor - Google Patents

Multilayered capacitor

Info

Publication number
JPH08124795A
JPH08124795A JP6262452A JP26245294A JPH08124795A JP H08124795 A JPH08124795 A JP H08124795A JP 6262452 A JP6262452 A JP 6262452A JP 26245294 A JP26245294 A JP 26245294A JP H08124795 A JPH08124795 A JP H08124795A
Authority
JP
Japan
Prior art keywords
conductive film
capacitor
multilayer capacitor
capacitors
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6262452A
Other languages
Japanese (ja)
Inventor
Akira Uchida
彰 内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6262452A priority Critical patent/JPH08124795A/en
Publication of JPH08124795A publication Critical patent/JPH08124795A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE: To provide a multilayered capacitor wherein the mounting density on a circuit board is improved. CONSTITUTION: Two capacitors are formed between conductive films 12, 13 formed on a dielectric sheet 10 and a conductive film 31. Two capacitors are formed between conductive films 22, 23 formed on a dielectric sheet 20 and a conductive film 31.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高密度実装に用いられ
る積層コンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor used for high density mounting.

【0002】[0002]

【従来の技術】従来より、例えば電子機器の高周波ノイ
ズ対策として、その電子機器の回路基板に形成された複
数の信号ラインとグラウンドとの間に、コンデンサ素子
がそれぞれ1つずつ内蔵された積層コンデンサが多数実
装されており、これら多数の積層コンデンサで高周波ノ
イズをグラウンドにバイパスすることにより電子機器の
誤動作等が防止される。このような電子機器の回路基板
の実装密度を向上させるために、これら多数の積層コン
デンサとして小型のものが使用されている。
2. Description of the Related Art Conventionally, for example, as a countermeasure against high frequency noise in electronic equipment, a multilayer capacitor having one capacitor element built in between each of a plurality of signal lines formed on a circuit board of the electronic equipment and a ground. Are mounted in a large number, and high frequency noise is bypassed to the ground by a large number of these multilayer capacitors, so that malfunction of the electronic device can be prevented. In order to improve the packaging density of the circuit board of such electronic devices, a small number of these multilayer capacitors are used.

【0003】[0003]

【発明が解決しようとする課題】しかし、積層コンデン
サを小型に製造する際、現状の製造工程において、例え
ば積層コンデンサの外形寸法が1.0mm(幅)×0.
5mm(奥行き)以下になると、ハンドリング性、寸法
精度の管理が困難となり、積層コンデンサの生産性が低
下する。またこのような外形寸法の積層コンデンサを回
路基板に実装するにあたっては、その積層コンデンサ
の、回路基板に対する取付寸法精度の管理が困難とな
り、回路基板の生産性も低下する。このため回路基板に
積層コンデンサを高密度に実装するのは容易でなく、問
題がある。
However, when manufacturing a multilayer capacitor in a small size, in the current manufacturing process, for example, the external dimensions of the multilayer capacitor are 1.0 mm (width) × 0.
When the thickness is 5 mm (depth) or less, it becomes difficult to control the handling property and dimensional accuracy, and the productivity of the multilayer capacitor decreases. Further, when mounting a multilayer capacitor having such an external dimension on a circuit board, it becomes difficult to control the accuracy of the mounting dimension of the multilayer capacitor on the circuit board, and the productivity of the circuit board also decreases. Therefore, it is not easy to mount the multilayer capacitors on the circuit board with high density, which is problematic.

【0004】本発明は、上記事情に鑑み、回路基板への
コンデンサの実装密の向上が図られた度積層コンデンサ
を提供することを目的とする。
In view of the above circumstances, it is an object of the present invention to provide a multilayer capacitor each time the mounting density of the capacitor on the circuit board is improved.

【0005】[0005]

【課題を解決するための手段】上記目的を達成する本発
明の積層コンデンサは、 (1)グラウンドに接続される第1の導電膜 (2)その第1の導電膜を挾持する第1および第2の誘
電体シート (3)その第1および第2の誘電体シートそれぞれの、
上記第1の導電膜側とは反対側の面上それぞれに形成さ
れた、上記第1の導電膜との間にコンデンサを形成する
複数の第2の導電膜、およびその第2の導電膜どうしの
間に介在する、グラウンドに接続される第3の導電膜 を備えたことを特徴とするものである。
Means for Solving the Problems A multilayer capacitor according to the present invention which achieves the above object is (1) a first conductive film connected to the ground (2) first and second conductive films sandwiching the first conductive film. 2 dielectric sheet (3) of each of the first and second dielectric sheets,
A plurality of second conductive films, which are formed on the surface opposite to the first conductive film side and form a capacitor between the second conductive films, and the second conductive films. It is characterized in that it is provided with a third conductive film which is interposed between and connected to the ground.

【0006】[0006]

【作用】本発明の積層コンデンサは、上記構成により、
第1および第2の誘電体シートそれぞれに形成された複
数の第2の導電膜と、第1の導電膜との間に、複数のコ
ンデンサが形成される。この積層コンデンサを回路基板
に実装すると複数のコンデンサが実装されることとな
り、例えば従来の、1個のコンデンサが形成された積層
コンデンサで複数実装する場合と比較し、回路基板の、
積層コンデンサが占める面積が小さくて済む。このた
め、コンデンサの、回路基板への実装密度の向上が容易
に図られる。また、1個の積層コンデンサを回路基板に
実装すると、複数のコンデンサが一度に実装されるた
め、実装の手間が軽減され、回路基板の生産性が向上す
る。
The multilayer capacitor of the present invention has the above structure.
A plurality of capacitors are formed between the plurality of second conductive films formed on each of the first and second dielectric sheets and the first conductive film. When this multilayer capacitor is mounted on a circuit board, a plurality of capacitors are mounted. For example, in comparison with a case where a plurality of conventional multilayer capacitors are formed, one capacitor is mounted on the circuit board.
The area occupied by the multilayer capacitor can be small. Therefore, the mounting density of the capacitors on the circuit board can be easily improved. Further, when one multilayer capacitor is mounted on the circuit board, a plurality of capacitors are mounted at one time, which reduces mounting time and improves the productivity of the circuit board.

【0007】また、本発明の積層コンデンサでは、コン
デンサを形成する第2の導電膜どうしの間にグラウンド
に接続される第3の導電膜が配置されているため、コン
デンサ間のクロストークも防止される。
Further, in the multilayer capacitor of the present invention, since the third conductive film connected to the ground is arranged between the second conductive films forming the capacitors, crosstalk between the capacitors is also prevented. It

【0008】[0008]

【実施例】以下、本発明の実施例について説明する。図
1は、本発明の積層コンデンサの一実施例としての4素
子積層コンデンサの、誘電体シートを積層順に並べた図
である。図1に示す5枚の誘電体シート10,20,3
0,40,50それぞれは、互いに同形同大の方形状の
誘電体シートである。
Embodiments of the present invention will be described below. FIG. 1 is a diagram in which dielectric sheets of a four-element multilayer capacitor as an example of the multilayer capacitor of the present invention are arranged in the stacking order. Five dielectric sheets 10, 20, 3 shown in FIG.
Each of 0, 40, and 50 is a rectangular dielectric sheet having the same shape and size.

【0009】誘電体シート10には、互いに電気的に絶
縁され3分割されたうちの中央の部分に、誘電体シート
10の長手方向の2辺に延出された端部11a,11b
を有する導電膜11が形成されている。この導電膜11
は、本発明にいう第3の導電膜に対応しており、グラウ
ンドと接続される。また、この導電膜11の両側に導電
膜12,13がそれぞれ形成されている。それら導電膜
12,13は、誘電体シート10の、互いに対向する角
に端部12a,13aをそれぞれ有している。これらの
導電膜12,13は、本発明にいう第2の導電膜に相当
する。
The dielectric sheet 10 is electrically insulated from each other and divided into three parts. At the central portion of the dielectric sheet 10, the end portions 11a and 11b are extended to two sides in the longitudinal direction of the dielectric sheet 10.
The conductive film 11 having is formed. This conductive film 11
Corresponds to the third conductive film referred to in the present invention and is connected to the ground. Conductive films 12 and 13 are formed on both sides of the conductive film 11. The conductive films 12 and 13 have ends 12a and 13a at corners of the dielectric sheet 10 that face each other. These conductive films 12 and 13 correspond to the second conductive film according to the present invention.

【0010】誘電体シート20には、誘電体シート10
の導電膜11,12,13に対応する位置に導電膜2
1,22,23がそれぞれ形成されている。導電膜21
は、本発明にいう第3の導電膜に相当し、誘電体シート
20の長手方向の2辺に延出された端部21a,21b
を有している。この導電膜21はグラウンドに接続され
る。また導電膜22,23は、本発明にいう第2の導電
膜に相当し、端部12a,13aが形成された角とは異
なる角に対応する、誘電体シート20の角に端部22
a,23aをそれぞれ有している。
The dielectric sheet 20 includes the dielectric sheet 10
The conductive film 2 at positions corresponding to the conductive films 11, 12, and 13 of
1, 22, 23 are formed respectively. Conductive film 21
Corresponds to the third conductive film according to the present invention, and the end portions 21a and 21b extended to two sides in the longitudinal direction of the dielectric sheet 20.
have. The conductive film 21 is connected to the ground. In addition, the conductive films 22 and 23 correspond to the second conductive film according to the present invention, and the end portions 22 at the corners of the dielectric sheet 20 corresponding to the corners different from the corners at which the end portions 12a and 13a are formed.
a and 23a respectively.

【0011】誘電体シート30には、誘電体シート10
の導電膜11,12,13を含めた大きさを有する導電
膜31が形成されている。この導電膜31は、導電膜1
1の幅寸法と同じ寸法の端部31a,31bを有してい
る。また導電膜31はグラウンドに接続される。尚この
導電膜31は、本発明にいう第1の導電膜に相当する。
The dielectric sheet 30 includes the dielectric sheet 10
The conductive film 31 having a size including the conductive films 11, 12, and 13 is formed. The conductive film 31 is the conductive film 1
It has end portions 31a and 31b having the same width dimension as that of No. 1. Further, the conductive film 31 is connected to the ground. The conductive film 31 corresponds to the first conductive film according to the present invention.

【0012】誘電体シート40,50は、導電膜が形成
されていない誘電体シートである。図2は、図1に示す
誘電体シートが互いに積層され、電極が形成された4素
子積層コンデンサの外観斜視図、図3は、その4素子積
層コンデンサの等価回路図である。図2に示す4素子積
層コンデンサを図1に示す誘電体シート10,20,3
0,40,50と対照すると、導電膜11の端部11a
と導電膜30の端部31aと、さらに導電膜21の端部
21aとが電極63で接続されている。また、導電膜1
1の端部11bと導電膜30の端部31bと、さらに導
電膜21の端部21bとが電極73で接続されている。
さらに導電膜12の端部12a,導電膜13の13aが
電極61,62にそれぞれ接続されており、導電膜22
の端部22a,導電膜23の端部23aが電極71,7
2にそれぞれ接続されている。
The dielectric sheets 40 and 50 are dielectric sheets having no conductive film formed thereon. 2 is an external perspective view of a four-element multilayer capacitor in which the dielectric sheets shown in FIG. 1 are laminated on each other and electrodes are formed, and FIG. 3 is an equivalent circuit diagram of the four-element multilayer capacitor. The four-element multilayer capacitor shown in FIG. 2 has the dielectric sheet 10, 20, 3 shown in FIG.
In contrast to 0, 40 and 50, the end portion 11a of the conductive film 11
The end portion 31a of the conductive film 30 and the end portion 21a of the conductive film 21 are connected by the electrode 63. In addition, the conductive film 1
The end portion 11b of No. 1 and the end portion 31b of the conductive film 30 are connected to the end portion 21b of the conductive film 21 by an electrode 73.
Further, the end portion 12a of the conductive film 12 and the conductive film 13a of the conductive film 13 are connected to the electrodes 61 and 62, respectively.
Of the electrodes 71 and 7
2 are connected to each.

【0013】このような4素子積層コンデンサを図3に
示す等価回路と対照すると、導電膜12および導電膜1
3と、導電膜31とからコンデンサ81およびコンデン
サ82が形成される。また、導電膜22および導電膜2
3と、導電膜31とからコンデンサ83およびコンデン
サ84が形成される。また、導電膜11,21は導電膜
31と接続され、クロストークを防止する役割を担って
いる。
Contrasting such a four-element multilayer capacitor with the equivalent circuit shown in FIG. 3, the conductive film 12 and the conductive film 1 are compared.
The capacitor 81 and the capacitor 82 are formed from 3 and the conductive film 31. In addition, the conductive film 22 and the conductive film 2
3 and the conductive film 31 form a capacitor 83 and a capacitor 84. The conductive films 11 and 21 are connected to the conductive film 31 and have a role of preventing crosstalk.

【0014】この実施例では、1個の積層コンデンサに
4個のコンデンサ81,82,83,84が形成されて
いるため、1個のコンデンサ素子が形成された積層コン
デンサを回路基板に4個実装する場合と比べ、積層コン
デンサ3個分の実装スペースが不要となり、その分、回
路基板へのコンデンサの実装密度が向上する。
In this embodiment, since four capacitors 81, 82, 83, 84 are formed on one multilayer capacitor, four multilayer capacitors each having one capacitor element are mounted on the circuit board. As compared with the case where the mounting is performed, the mounting space for three multilayer capacitors is not required, and the mounting density of the capacitors on the circuit board is improved accordingly.

【0015】[0015]

【発明の効果】以上説明したように、本発明によれば、
1個の積層コンデンサに複数のコンデンサが形成された
ものであるため、この積層コンデンサを回路基板に実装
すると、コンデンサの、回路基板への実装密度の向上が
図られるとともに実装コストの低減も図られる。
As described above, according to the present invention,
Since a plurality of capacitors are formed on one multilayer capacitor, mounting this multilayer capacitor on a circuit board can improve the mounting density of the capacitors on the circuit board and reduce the mounting cost. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の積層コンデンサの一実施例としての4
素子積層コンデンサの、誘電体シートを積層順に並べた
図である。
FIG. 1 is a diagram showing an example of a multilayer capacitor according to an embodiment of the present invention.
It is the figure which arranged the dielectric sheet of the element multilayer capacitor in order of lamination.

【図2】図1に示す誘電体シートが互いに積層され、電
極が形成された4素子積層コンデンサの外観斜視図であ
る。
FIG. 2 is an external perspective view of a four-element laminated capacitor in which the dielectric sheets shown in FIG. 1 are laminated with each other and electrodes are formed.

【図3】4素子積層コンデンサの等価回路図である。FIG. 3 is an equivalent circuit diagram of a 4-element multilayer capacitor.

【符号の説明】[Explanation of symbols]

10,20,30,40,50 誘電体シート 11,12,13,21,22,23,31 導電膜 11a,11b,12a,13a,21a,21b,2
2a,23a,31a,31b 端部 61,62,63,71,72,73 電極 81,82,83,84 コンデンサ
10, 20, 30, 40, 50 Dielectric sheet 11, 12, 13, 21, 22, 23, 31 Conductive film 11a, 11b, 12a, 13a, 21a, 21b, 2
2a, 23a, 31a, 31b Ends 61, 62, 63, 71, 72, 73 Electrodes 81, 82, 83, 84 Capacitors

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 グラウンドに接続される第1の導電膜
と、 該第1の導電膜を挾持する第1および第2の誘電体シー
トと、 該第1および第2の誘電体シートそれぞれの、前記第1
の導電膜側とは反対側の面上それぞれに形成された、前
記第1の導電膜との間にコンデンサを形成する複数の第
2の導電膜、および該第2の導電膜どうしの間に介在す
る、グラウンドに接続される第3の導電膜とを備えたこ
とを特徴とする積層コンデンサ。
1. A first conductive film connected to the ground, first and second dielectric sheets sandwiching the first conductive film, and each of the first and second dielectric sheets, The first
A plurality of second conductive films, each of which is formed on a surface opposite to the conductive film side, forming a capacitor between the first conductive film and the second conductive films. A multilayer capacitor comprising: an intervening third conductive film connected to the ground.
JP6262452A 1994-10-26 1994-10-26 Multilayered capacitor Withdrawn JPH08124795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6262452A JPH08124795A (en) 1994-10-26 1994-10-26 Multilayered capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6262452A JPH08124795A (en) 1994-10-26 1994-10-26 Multilayered capacitor

Publications (1)

Publication Number Publication Date
JPH08124795A true JPH08124795A (en) 1996-05-17

Family

ID=17375988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6262452A Withdrawn JPH08124795A (en) 1994-10-26 1994-10-26 Multilayered capacitor

Country Status (1)

Country Link
JP (1) JPH08124795A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
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US6331926B1 (en) 1997-04-08 2001-12-18 Anthony A. Anthony Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6373673B1 (en) 1997-04-08 2002-04-16 X2Y Attenuators, Llc Multi-functional energy conditioner
US6498710B1 (en) 1997-04-08 2002-12-24 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6509807B1 (en) * 1997-04-08 2003-01-21 X2Y Attenuators, Llc Energy conditioning circuit assembly
US6580595B2 (en) 1997-04-08 2003-06-17 X2Y Attenuators, Llc Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning
US6603646B2 (en) 1997-04-08 2003-08-05 X2Y Attenuators, Llc Multi-functional energy conditioner
US6636406B1 (en) 1997-04-08 2003-10-21 X2Y Attenuators, Llc Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning
US6650525B2 (en) 1997-04-08 2003-11-18 X2Y Attenuators, Llc Component carrier
US6687108B1 (en) 1997-04-08 2004-02-03 X2Y Attenuators, Llc Passive electrostatic shielding structure for electrical circuitry and energy conditioning with outer partial shielded energy pathways
US6738249B1 (en) 1997-04-08 2004-05-18 X2Y Attenuators, Llc Universal energy conditioning interposer with circuit architecture
US6995983B1 (en) 1997-04-08 2006-02-07 X2Y Attenuators, Llc Component carrier
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
WO2018199220A1 (en) * 2017-04-26 2018-11-01 京セラ株式会社 Multiple laminated ceramic capacitor
JP2021057589A (en) * 2019-09-24 2021-04-08 株式会社村田製作所 Electronic component module and using method of electronic component module

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6738249B1 (en) 1997-04-08 2004-05-18 X2Y Attenuators, Llc Universal energy conditioning interposer with circuit architecture
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
US6498710B1 (en) 1997-04-08 2002-12-24 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6509807B1 (en) * 1997-04-08 2003-01-21 X2Y Attenuators, Llc Energy conditioning circuit assembly
US6580595B2 (en) 1997-04-08 2003-06-17 X2Y Attenuators, Llc Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning
US6594128B2 (en) 1997-04-08 2003-07-15 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6603646B2 (en) 1997-04-08 2003-08-05 X2Y Attenuators, Llc Multi-functional energy conditioner
US6331926B1 (en) 1997-04-08 2001-12-18 Anthony A. Anthony Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6650525B2 (en) 1997-04-08 2003-11-18 X2Y Attenuators, Llc Component carrier
US6687108B1 (en) 1997-04-08 2004-02-03 X2Y Attenuators, Llc Passive electrostatic shielding structure for electrical circuitry and energy conditioning with outer partial shielded energy pathways
US6636406B1 (en) 1997-04-08 2003-10-21 X2Y Attenuators, Llc Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning
US6995983B1 (en) 1997-04-08 2006-02-07 X2Y Attenuators, Llc Component carrier
US9373592B2 (en) 1997-04-08 2016-06-21 X2Y Attenuators, Llc Arrangement for energy conditioning
US6373673B1 (en) 1997-04-08 2002-04-16 X2Y Attenuators, Llc Multi-functional energy conditioner
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
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