JPH08116532A - Image decoding system and device therefor - Google Patents

Abstract

PURPOSE: To provide the image decoding system and the device in which the control of insertion of decoding start time information representing a time for starting decoding corresponding to each frame into a bit stream, storing the resulting information to a buffer memory and reading of the bit stream based on the stored decoding start time information and starting of decoding corresponding to each frame is easily conducted. CONSTITUTION: A reference time is measured by an STC counter section 32, a VBS/DTS insert section 34 inserts decoding start time information representing a time to start decoding of each frame to a bit stream based on the reference time. Then the bit stream is stored in a buffer memory 12 and a read control section 36 reads the bit stream stored in the buffer memory 12 and controls the start of reading the bit stream stored based on the decoding start time information included in the bit stream.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding system and apparatus, and more particularly to starting decoding when inputting a bit stream containing encoded image data and decoding the image data. The present invention relates to an image decoding system and apparatus for inserting power time information into a bitstream.

[0002]

2. Description of the Related Art Conventionally, when transmitting or accumulating image data represented by a digital signal, encoding is performed to reduce the data amount of the image data. As a coding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image data. As a method of utilizing the temporal correlation, there is a method of encoding a difference between two consecutive screens (frames) or detecting a motion of an image to perform motion compensation. On the other hand, as a method of utilizing the spatial correlation, the image is divided into blocks of a predetermined size (for example, 8 pixels in each of the vertical and horizontal directions), the image data in the blocks is orthogonally transformed, and the transform coefficient is scanned. There is a method in which variable length coding is performed after conversion (for example, rearranging from low frequency components to high frequency components).

In recent years, MPEG (Moving Picture Exper) has been used as an image coding method that uses the above two methods together.
t group) is promoting standardization under "ISO /
"Generic Coding of" IEC13818-2 "
In "Moving Pictures and Associated Audio", a provisional recommendation of an image encoding method (hereinafter referred to as MPEG2) is made.

Regarding this MPEG2, M shown in FIG.
An image decoding device equipped with PEG2 is known.
As shown in FIG. 7, this image decoding apparatus includes a buffer memory control unit 11, a buffer memory 12, a variable length decoder 21, a scan converter 22, an inverse quantizer 23, and an inverse DCT.
The input bitstream 100 including the encoded image data, which is composed of the unit 24, the motion compensation image reproducing unit 25, and the prediction frame memory 26, and reproduces the reproduced image 20.
It outputs 0.

Next, the decoding operation of the image decoding apparatus shown in FIG. 7 will be described. First, the input bitstream 1
00 is sequentially stored in the buffer memory 12 under the control of the buffer memory control unit 11. On the other hand, the image data read from the buffer memory 12 is variable length decoded by the variable length decoder 21. There are two types of image data, one is variable length coded and the other is fixed length coded, and both are variable length decoder 21.
Shall be decrypted by. Next, after the order of the image data is rearranged by the scan converter 22, it is inversely quantized by the inverse quantizer 23. Then the inverse DCT
Inverse discrete cosine transform is performed by the unit 24. When the inter-frame difference data is received, the motion compensation image reproduction unit 25 reads the reference data from the prediction frame memory 26, adds the reference data to the received data, writes the reproduction image in the prediction frame memory 26, and outputs the reproduction image 200. To do.
On the other hand, when the data encoded in the frame is received, the received data is directly written in the prediction frame memory 26 and the reproduced image 200 is output.

There are two control methods for starting the decoding of each frame. The first method for starting the decoding of each frame is to use the timing information 101 added in the system stream such as the MPEG2 program stream or transport stream. This system stream is configured by multiplexing a video stream, an audio stream and other information in one bit stream. The video stream, the audio stream, and the like are separated by the MPEG system decoder and supplied to the video decoder, the audio decoder, and the like.

In this way, the video input bit stream 100 and the timing information 101 as shown in FIG.
Is obtained. As the timing information 101, an SCR (System Clock Rsference) representing a reference time (which is called SCR in the program stream and PCR in the transport stream, which will be collectively referred to as SCR hereinafter),
DTS (Decoding Time Stam) representing the decoding start time information
p), PTS (Presentation T) indicating the display start time information
ime Stamp). Note that DTS is information that is given only when it is different from PTS, and when DTS and PTS are the same, only PTS is given. Therefore, although the decoding start time information can be known from the DTS or PTS, the decoding start time information will be given by the DTS on behalf of both. For time measurement, an STC counter is provided in the image decoding device, and the SCR is
The C counter is set and the 27 MHz reference clock given from the system decoder is counted up.
The input DTS is stored inside the buffer memory control unit 11. Here, in order to start decoding of each frame, the data stored in the buffer memory 12 is controlled to start reading at the time when STC and DTS match.

On the other hand, the second method for starting the decoding of each frame is to use the VBV delay information in the picture header added to the beginning of each frame in the input bitstream 100. The VBV delay information is given by the count number when the delay time from writing the picture header to the buffer memory 12 until reading it again is counted with the reference clock of 90 KHZ. In addition, VBV
The delay information represents buffer delay information indicating the delay due to the buffer memory 12.

Here, the bit rate of the input bit stream 100 is R and the picture header is the buffer memory 12.
Letting B be the buffer storage amount after reading (from the time when the data of the frame of interest is read), there is a relationship of VBV delay = 90000 × B / R (Equation 1).

Next, the operation of the first decoding start control example for controlling the start of decoding using the VBV delay information will be described with reference to FIG. First, the write header analysis unit analyzes the picture header of the input bitstream 100 to obtain VBV delay information, and then stores the VBV delay information in the VBV delay register unit. Further, the write control unit outputs a write signal for notifying the timing of writing the picture header to the buffer memory 12 to the counter unit. The counter unit activated by the write signal counts up the 90 KHZ reference clock. Here, when the counter value of the counter unit matches the VBV delay value stored in the VBV delay register unit, the matching circuit outputs the decoding start signal to the read control unit. Next, the read control unit restarts reading the bitstream data from the buffer memory 12 when the decoding start signal is input. Variable length decoder 2
After the decoding for one frame is completed at 1, the reading of the bit stream data from the buffer memory 12 is interrupted and the decoding start signal corresponding to the next frame is waited for.

Next, the operation of the second decoding start control example for controlling the start of decoding using the VBV delay information will be described with reference to FIG. First, the read control unit reads the picture header from the buffer memory 12, and the read header analysis unit analyzes the picture header to obtain the VBV delay information. At this point, the reading from the buffer memory 12 is interrupted. Here, the decoding start buffer amount calculation unit, to which the VBV delay information is input, calculates the buffer storage amount B based on the above (Equation 1). The bit rate R is assumed to be obtained from the sequence header in advance. On the other hand, the buffer storage amount calculation unit obtains the actual actual buffer storage amount b of the buffer memory 12 from the write address obtained from the write control unit and the read address obtained from the read control unit. Here, when the input bitstream 100 is sequentially written in the buffer memory 12, the actual buffer storage amount b
When the matching circuit detects that the actual buffer storage amount b becomes equal to the buffer storage amount B, the matching circuit outputs a decoding start signal. Next, the read control unit that has received the decoding start signal restarts reading the bitstream data from the buffer memory 12.

When the start of decoding is controlled using DTS, there is an advantage that audio data and image data can be easily synchronized. However, if the DTS is not available, the VBV delay information must be used to control the start of decoding. Therefore, it is preferable that the image decoding apparatus can control the start of decoding using the DTS and VBV delay information.

As for the image decoding system and apparatus, the "image decoding apparatus" described in Japanese Patent Application No. 6-36755 has been reported. This is to separate / discard zero stuffing, user data, etc. that are not directly related to the decoding of image data.

[0014]

However, in the first decoding start control example shown in FIG. 8 of the related art, although the buffer memory 12 can store image data for a plurality of frames. , As shown in FIG.
Since there is only one V delay register section and one counter section, the VBV delay information for a plurality of frames cannot be managed. Therefore, the decoding start corresponding to the first frame can be controlled, but the decoding start cannot be controlled based on the VBV delay information corresponding to the second frame. .

It is also possible to control the start of decoding based on the VBV delay information corresponding to the first frame, and start decoding of each frame from the next frame at equal intervals according to the frame rate. However, there is a problem that decoding cannot be performed if the intervals at which decoding is started are not equal, such as in an edited bitstream.

Further, in order to control the start of decoding based on the VBV delay information for each frame, it is necessary to provide a plurality of VBV delay register sections, counter sections and coincidence circuits, which complicates the circuit and control. There was a problem that became. However, in the second decoding start control example shown in FIG. 9 of the related art, since the decoding start buffer amount calculation unit needs a multiplier and a divider, the circuit configuration becomes complicated. was there.

Further, in the conventional "image decoding device" described in Japanese Patent Application No. 6-36755, when zero stuffing and user data which are not directly related to the decoding of image data are separated / discarded. However, there is a problem that monitoring of unnecessary data separated / discarded by the buffer accumulation amount calculation unit becomes complicated. Therefore, the present invention generates decoding start time information representing the time to start decoding corresponding to each frame based on the reference time, inserts this decoding start time information into the bitstream, and stores it in the buffer memory. After the storage, the stored bitstreams are sequentially read, and control is performed so as to start reading the bitstream including the stored image data based on the decoding start time information included in the bitstreams. An object of the present invention is to provide an image decoding system and device that can easily perform control for starting decoding corresponding to a frame.

[0018]

According to the first aspect of the present invention,
In order to solve the above problems, in an image decoding method in which a bitstream including encoded image data is input and the image data is decoded, a reference time is measured and each frame is decoded based on the reference time. Decoding start time information indicating the time to start decoding is inserted into the bitstream, a bitstream including the decoding start time information is stored, the stored bitstream is sequentially read, and the bitstream is read. Is controlled so as to start the reading of the bit stream including the image data stored based on the decoding start time information included in.

In order to solve the above-mentioned problems, the invention according to claim 2 is the invention according to claim 1, in which buffer delay information representing a delay due to a buffer set in a bitstream containing image data and the bitstream of the bitstream. It is characterized in that the decoding start time information is generated based on one of the decoding start time information which is the additional information and the display start time information which is the additional information of the bitstream.

In order to solve the above-mentioned problems, the invention according to claim 3 is the invention according to claim 1 or 2, wherein the buffer delay information indicating the delay due to the buffer set in the bit stream containing the image data is decoded. The decoding start time information is replaced and the decoding start time information is inserted into the bitstream. In order to solve the above-mentioned problems, the invention according to claim 4 is the invention according to claim 1, wherein the decoding start time information included in the sequentially read bitstreams matches the measured reference time. In this case, a read start signal indicating the start of read is generated.

In order to solve the above-mentioned problems, the invention according to claim 5 measures a reference time in an image decoding apparatus for inputting a bit stream including encoded image data and decoding the image data. Reference time measuring means, and decoding start time information insertion for inserting into the bitstream decoding start time information indicating the time to start decoding of each frame based on the reference time measured by the reference time measuring means Means, a buffer memory means for storing a bitstream including decoding start time information, and a bitstream stored in the buffer memory means are sequentially read out, and based on the decoding start time information included in the bitstream. Read control for starting the reading of the bit stream containing the image data stored in the buffer memory means. Characterized by comprising a control means.

In order to solve the above-mentioned problems, the invention according to claim 6 is the invention according to claim 5, wherein buffer delay information indicating a delay due to a buffer set in a bitstream containing image data, and the bitstream of the bitstream. Decoding start time information generating means for generating decoding start time information based on one of the decoding start time information that is the additional information and the display start time information that is the additional information of the bitstream is provided. Is characterized by.

In order to solve the above-mentioned problems, the invention according to claim 7 is the invention according to claims 5 to 6, wherein the buffer delay information representing the delay due to the buffer set in the bit stream containing the image data is decoded. A decoding start time information replacing unit that replaces the decoding start time information and inserts the decoding start time information into the bitstream is provided.

In order to solve the above-mentioned problems, the invention according to claim 8 is the invention according to claim 5, wherein the decoding start time information contained in the bit stream read from the buffer memory means is the reference time. When it coincides with the reference time measured by the measuring means, the read control means is provided with a read start signal generating means for generating a read start signal indicating a read start.

In order to solve the above-mentioned problems, the invention of claim 9 is characterized in that, in the invention of claims 1 to 8, the decoding start time information is represented by a 16-bit length.

[0026]

According to the first aspect of the present invention, in the image decoding system for inputting the bit stream including the encoded image data and decoding the image data, the reference time is measured and based on the reference time. Decoding start time information indicating the time to start decoding of each frame is inserted into the bitstream, a bitstream including the decoding start time information is stored, and the stored bitstream is sequentially read, Based on the decoding start time information included in the bitstream, control is performed to start reading of the bitstream including the image data stored.

According to a second aspect of the invention, in the first aspect of the invention, buffer delay information indicating a delay due to a buffer set in a bitstream including image data, and decoding start which is incidental information of the bitstream. The decoding start time information is generated based on any one of the time information and the display start time information that is additional information of the bitstream.

In the invention according to claim 3, claims 1 and 2
In the described invention, the buffer delay information indicating the delay due to the buffer set in the bitstream containing the image data is replaced with the decoding start time information, and the decoding start time information is inserted into the bitstream. In the invention according to claim 4, in the invention according to claim 1, when the decoding start time information included in the sequentially read bit stream matches the measured reference time, the read start is performed. A read start signal is generated.

According to a fifth aspect of the present invention, in an image decoding apparatus for inputting a bit stream including encoded image data and decoding the image data, based on the reference time measured by the reference time measuring means. Decoding start time information indicating the time when decoding of each frame is started is inserted into the bitstream by the decoding start time information inserting means. Next, the bit stream including the decoding start time information is stored in the buffer memory means. The read control means sequentially reads the bitstream stored in the buffer memory means, and based on the decoding start time information contained in the bitstream, the bitstream containing the image data stored in the buffer memory means. Control to start reading.

According to a sixth aspect of the invention, in the fifth aspect of the invention, the buffer delay information indicating the delay due to the buffer set in the bitstream containing the image data by the decoding start time information generating means, the bitstream. Decoding start time information is generated based on one of the decoding start time information, which is the additional information of the above, and the display start time information, which is the additional information of the bitstream.

According to the invention of claim 7, claims 5 to 6 are provided.
In the invention described above, the decoding start time information is replaced by replacing the buffer delay information indicating the delay due to the buffer set in the bitstream including the image data by the decoding start time information replacing means with the decoding start time information. Is inserted into the bitstream. According to the invention of claim 8,
In the invention according to claim 5, when the decoding start time information contained in the bit stream read from the buffer memory means coincides with the reference time measured by the reference time measuring means, a read start signal. The generating means generates a read start signal indicating the start of reading to the read control means.

According to the invention of claim 9, claims 1 to 8
In the invention described above, the decoding start time information is represented by a 16-bit length.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. First, the system configuration of the image decoding apparatus will be described. FIG. 1 is a system configuration diagram of an image decoding apparatus which is an embodiment of the present invention. As shown in FIG. 1, the image decoding apparatus includes a buffer memory control unit 110, a buffer memory 12, a variable length decoder 21, a scan converter 22, an inverse quantizer 23, an inverse DCT unit 24, and a motion compensation image reproduction. Part 2
5 and the prediction frame memory 26.

The buffer memory control unit 110 controls to sequentially store the input bitstream 100 in the buffer memory 12 and to sequentially read out the bitstream stored in the buffer memory 12. The buffer memory 12 sequentially accumulates the input bitstream 100 and outputs the accumulated bitstream in the first-in first-out order. The variable length decoder 21 includes a buffer memory 1
The variable-length coded image data or the fixed-length coded image data read from No. 2 is variable-length decoded.
The scan converter 22 rearranges the order of the decoded image data.

The dequantizer 23 dequantizes the reordered image data to restore DCT coefficients. Reverse D
The CT unit 24 performs an inverse discrete cosine transform on the DCT coefficient.
When the inter-frame difference data is input, the motion compensation image reproduction unit 25 reads the reference data from the prediction frame memory 26, adds the reference data to the input data, writes the reproduction image in the prediction frame memory 26, and outputs the reproduction image 200. To do. On the other hand, when the data encoded in the frame is input, the input data is written as it is in the prediction frame memory 26 and the reproduced image 200 is output.

The predictive frame memory 26 stores the reproduced image 200 as a result of adding the inter-frame difference data and the reference data read from the predictive frame memory 26 in the motion compensation image reproducing section 25, and is encoded within the frame. The stored image data is stored as it is. Figure 2 is MP
It is a figure which shows the hierarchical structure of EG2 image data.

As shown in FIG. 2, the MPEG2 image data is hierarchically structured by a sequence layer, a GOP layer, a picture layer, a slice layer, a macroblock layer and a block layer. The sequence layer is composed of a series of screen groups having the same attributes. The GOP layer is composed of the minimum unit of the screen group which is a unit of random access. The picture layer is composed of attributes common to one screen. The slice layer is composed of information common to small screens obtained by subdividing one screen. The macroblock layer is
It is composed of information common to the pixel blocks obtained by further dividing the slice layer. The block layer is composed of DCT transform coefficients.

FIG. 3 is a diagram of a multi-processing system of the picture layer. As shown in FIG. 3, the picture layer includes a PSC (Picture Start Code) indicating a start synchronization code of the picture layer, a TR (Temporal Reference) indicating a display order number, a PCT (Picture Coding Type) indicating a picture type, Buffer delay information VD (VBV Delay) indicating the initial state of the buffer at random access, FPFV (Full Pel) indicating whether the accuracy of the forward motion vector is an integer unit or a half pixel unit
Forward Vector), FFC (Forward F Code) indicating the forward motion vector search range, and FPBV (Full Pel) indicating whether the accuracy of the backward motion vector is an integer unit or a half pixel unit.
Backward Vector), BFC (Backward F Code) indicating the backward motion vector search range, EBP (Extra Bit Picture) indicating the presence / absence of other picture information, Picture Coding Extension (Picture Coding Extension), Quantization matrix function Extension (QM Extension), Picture Display Extension (Picture Display Extension), Picture Space Scalable Extension (Picture Spatial Scal)
and the picture temporal scalable function extension part (Picture Temporal Scalable Extension), and is followed by the slice layer one layer below.

(Embodiment 1) This embodiment (claims 1, 2,
4, 5, 6, 8) can be applied to the image decoding apparatus described in FIG. In this embodiment, a characteristic part of the present invention (claims 1, 2, 4, 5, 6, 8) will be specifically described. FIG. 4 is a block diagram of the buffer memory control unit 110 of the image decoding apparatus which is an embodiment of the present invention.

As shown in FIG. 4, the buffer memory control unit 110 includes a write header analysis unit 31 and an STC counter unit 3.
2, DTS generator 33, VBV / DTS inserter 34, write controller 35, read controller 36, read header analyzer 37
And an STC / DTS comparison unit 38. The write header analysis unit 31 analyzes the picture header in the input bitstream 100 of the picture layer shown in FIG. 3 to obtain VD as VBV delay information, and then stores the VBV delay information in the DTS generation unit 33.

The STC counter section 32 is normally SCR-e.
300-ary 9-bit counter called xt and SCR-
It is composed of a 33-bit counter called base. The SCR-ext counts up the 27 MHz reference clock, and when it reaches 300, outputs a 90 KHZ trigger clock to the SCR-base counter. SCR
-Base is counted up by the clock of 90 KHZ after being preset to the system time reference reference value SCR. In this way, the STC counter unit 32 measures the reference time value and outputs it to the DTS generation unit 33. Note that S
If the CR value is not included in the timing information 101, the STC counter unit 32 is assumed to be free-running.

When the DTS generator 33 is set to the VBV mode by the DTS / VBV mode signal,
The VBV delay information transferred from the write header analysis unit 31 and the reference time value representing the current time transferred from the STC counter unit 32 are added to obtain the generated DTS which is the decoding start time information. On the other hand, when the DTS mode is set by the DTS / VBV mode signal, the DTS in the system stream is directly used as the generated DTS. Here, in the system stream, for a frame to which a DTS is not given, the DT generated by adding the STC counter value corresponding to one frame period determined from the frame rate to the DTS of the immediately preceding frame.
Get S. When the previous one is a field image, the generated DTS is obtained by adding the STC counter value corresponding to one field period. When the DTS and PTS in the system stream are different, the given PTS is used as it is as the generated DTS.

The VBV / DTS insertion unit 34 inserts the generated DTS generated by the DTS generation unit 33 into the bitstream 100. The write control unit 35 uses VBV / DT
Control for sequentially writing the bitstream output from the S insertion unit 34 into the buffer memory 12 is performed. The read control unit 36 sequentially reads the bitstream written in the buffer memory 12 in a first-in first-out order. When the read interrupt signal is input from the read header analysis unit 37, the read control unit 36 interrupts the reading of the bitstream from the buffer memory 12. Also, STC / DT
When the decoding start signal is input from the S comparison unit 38,
The read control unit 36 starts reading the bitstream from the buffer memory 12.

The read header analysis unit 37 outputs a read interruption signal to the read control unit 36 after detecting the generated DTS in the picture header of the bit stream read from the buffer memory 12 via the read control unit 36. Reading of the bit stream from the buffer memory 12 is interrupted. Next, the read header analysis unit 37 analyzes the generated DTS and outputs the generated DTS value to the STC / DTS comparison unit 38.

The STC / DTS comparison unit 38 compares the generated DTS value analyzed by the read header analysis unit 37 with the reference time output from the STC counter unit 32, and if they match each other, outputs a decoding start signal. The data is output to the read control unit 36 to start reading the bitstream from the buffer memory 12. FIG. 5 is a diagram showing a temporal change of the buffer occupancy rate in the buffer memory 12 of the image decoding apparatus according to the embodiment of the present invention.

The operation of the image decoding apparatus which is an embodiment of the present invention will be described below with reference to FIG. In FIG. 5, the horizontal axis represents time, and the vertical axis represents the buffer occupancy rate of the bit stream data accumulated in the buffer memory 12. In addition, V is generated by the DTS / VBV mode signal.
It is assumed that the BV mode is set.

First, the write header analysis unit 31 shown in FIG.
Is the input bitstream 10 of the picture layer shown in FIG.
After the picture header in 0 is analyzed and VD is obtained as VBV delay information, the VBV delay information is stored in the DTS generator 33. Next, since the DTS generator 33 is set to the VBV mode, it adds the VBV delay information transferred from the write header analyzer 31 and the reference time value representing the current time transferred from the STC counter 32. Then, the generated DTS which is the decoding start time information is obtained.

Next, the VBV / DTS insertion unit 34 causes the DT
The generated DTS generated by the S generation unit 33 is inserted into the bitstream 100. Next, the bit stream output from the VBV / DTS insertion unit 34 is written into the write control unit 3
At 5, the writing is sequentially started to the buffer memory 12. Next, in the buffer memory 12, as shown in FIG. 5, the bit stream is sequentially written with the header information H1 of the first frame as the head. At this point, the generated DTS1 obtained by adding the VBV delay information 1 (d1) and the reference time value (STC1) representing the current time transferred from the STC counter unit 32 is inserted into the header information H1.
Next, in the header information H2 of the second frame, the generated DTS2 obtained by adding the VBV delay information 2 (d2) and the reference time value (STC2) representing the current time transferred from the STC counter unit 32 is inserted. .

On the other hand, the read control unit 36 sequentially reads the bit streams written in the buffer memory 12 in the first-in first-out order and outputs them to the read header analysis unit 37. Next, the read header analysis unit 37 detects the generated DTS1 inserted in the header information H1 of the bitstream read from the buffer memory 12 via the read control unit 36, and then outputs the read interrupt signal to the read control unit. The data is output to 36 and the reading of the bit stream from the buffer memory 12 is once interrupted. Next, the read header analysis unit 37 generates the generated DTS.
1 is analyzed and the DTS1 value generated is analyzed by the STC / DTS comparison unit 3
Output to 8.

Next, the STC / DTS comparing section 38 operates as shown in FIG.
At the point P1 shown in (1), if the generated DTS1 value analyzed by the read header analysis unit 37 and the reference time value output from the STC counter unit 32 are compared and they match,
The decoding start signal is output to the read control unit 36. Next, since the decoding start signal is input from the STC / DTS comparison unit 38, the read control unit 36 starts reading the bitstream from the buffer memory 12 at point P1.

The bit stream read from the buffer memory 12 is input to the variable length decoder 21 via the read control unit 36 and the read header analysis unit 37. Next, the variable length decoder 21 uses the buffer memory 12
The variable-length coded image data or the fixed-length coded image data read from is variable-length decoded, and the order of the image data decoded by the scan converter 22 is rearranged. Next, the inverse quantizer 23 inversely quantizes the rearranged image data to restore the DCT coefficient, and the inverse D
The CT unit 24 performs inverse discrete cosine transform on the DCT coefficient.

Next, when the data immediately after the header information H1 encoded in the frame is input, the motion compensation image reproducing unit 25 writes the input data as it is in the prediction frame memory 26 and outputs the reproduced image 200. . On the other hand, when the inter-frame difference data immediately after the header information H3 and H4 is input, the reference data is read from the prediction frame memory 26, added with the input data, and then the reproduced image is written into the predicted frame memory 26 to reproduce the reproduced image 200. Output.

Thus, in this embodiment (claim 1),
In an image decoding method in which a bitstream including encoded image data is input and the image data is decoded, the reference time is measured by the STC counter unit 32 and V
The BS / DTS inserting unit 34 inserts the decoding start time information indicating the time when the decoding of each frame starts based on the reference time into the bitstream. Next, the bit stream including the decoding start time information is stored in the buffer memory 12
The bit stream stored in the buffer memory 12 is sequentially read by the read control unit 36, and the reading of the bit stream including the image data stored based on the decoding start time information included in the bit stream is started. Control to do.

Therefore, the decoding start time information of each frame is obtained based on the reference time and inserted into the bit stream, and the bit including the image data stored based on the decoding start time information included in the bit stream is included. Since the control is performed so as to start the reading of the stream, it is possible to facilitate the control when starting the reading of the bit stream from the buffer memory. Further, even when the image data of a plurality of frames is stored in the buffer memory, the decoding start time information corresponding to each frame can be inserted, so that the frame unit for reading the bitstream from the buffer memory is started. Control can be facilitated.

Thus, in this embodiment (claim 2),
Buffer delay information (for example, VBV delay information) indicating a delay due to a buffer set in a bitstream including image data by the DTS generation unit 33, decoding start time information that is additional information of the bitstream, and additional information of the bitstream. Generated DTS that is decoding start time information based on any one of the display start time information
Generate

Therefore, since the decoding start time information is generated based on the reference time measured by the STC counter section,
It is possible to manage time that is highly consistent with the system clock. As described above, in the present embodiment (claim 4), when the generated DTS which is the decoding start time information included in the sequentially read bitstreams matches the STC which is the measured reference time, , The STC / DTS comparison unit 38 generates a read start signal indicating the start of reading, so that the read control unit 36 can control to sequentially start reading the bit streams stored in the buffer memory 12, and the bit from the buffer memory can be controlled. It is possible to facilitate control when starting reading of the stream.

Thus, in this embodiment (claim 5),
In an image decoding device for inputting a bitstream containing encoded image data and decoding the image data,
The VBV / DTS inserting unit 34 (decoding start time information inserting unit) outputs decoding start time information indicating the time when decoding of each frame is started based on the reference time measured by the STC counter unit 32 (reference time measuring unit). ) To insert into the bitstream. Next, the bit stream including the decoding start time information is stored in the buffer memory 12 (buffer memory means). The buffer memory 12 (buffer memory means) by the read controller 36 (read control means)
The bitstreams stored in the buffer are sequentially read, and the bitstream including the image data stored in the buffer memory 12 (buffer memory means) is read based on the decoding start time information included in the bitstreams. Control.

Therefore, the decoding start time information of each frame is obtained based on the reference time and inserted into the bit stream, and the bit including the image data stored based on the decoding start time information included in the bit stream is included. Since the control is performed so as to start the reading of the stream, it is possible to facilitate the control when starting the reading of the bit stream from the buffer memory. Further, even when the image data of a plurality of frames is stored in the buffer memory, the decoding start time information corresponding to each frame can be inserted, so that the frame unit for reading the bitstream from the buffer memory is started. Control can be facilitated. As described above, in the present embodiment (claim 6), the buffer delay information indicating the delay due to the buffer set in the bitstream including the image data by the DTS generator 32 (decoding start time information generator),
A generated DTS that is decoding start time information is generated based on either one of the decoding start time information that is additional information of the bitstream and the display start time information that is additional information of the bitstream.

Therefore, since the decoding start time information is generated based on the reference time measured by the STC counter section,
It is possible to manage time that is highly consistent with the system clock. As described above, in the present embodiment (claim 8), the generation D which is the decoding start time information included in the bit stream read from the buffer memory 12 (buffer memory means).
If TS matches STC which is the reference time measured by the STC counter unit 32 (reference time measuring means), S
Since the TC / DTS comparing unit 38 (reading start signal generating means) generates a reading start signal indicating the reading start to the reading control unit 36 (reading control means), the reading control unit 36 stores the bit stream stored in the buffer memory 12. Can be controlled so as to start reading sequentially, and control when starting reading of the bitstream from the buffer memory can be facilitated.

(Embodiment 2) This embodiment (claims 3 and 7) can be applied to the image decoding apparatus described in FIG. 1 as in Embodiment 1. In this embodiment, the present invention (claim 3,
The characteristic part of 7) will be specifically described. FIG. 6 shows a buffer memory control unit 1 of an image decoding apparatus which is an embodiment of the present invention.
It is a block block diagram of 10.

As shown in FIG. 6, the VBV / DTS replacing section 44 is a new component in this embodiment in addition to the configuration of the image decoding apparatus shown in FIG. VBV
The / DTS replacing unit 44 deletes the VBV delay information in the bitstream and replaces the generated DTS transferred from the DTS generating unit 33 instead. The bit stream thus obtained is written in the buffer memory 12 via the write controller 35.

The operation from the write header analysis unit 31 to the write control unit 35 of the image decoding apparatus according to the embodiment of the present invention will be described below with reference to FIG. First, the write header analysis unit 31 shown in FIG. 5 analyzes the picture header in the input bitstream 100 of the picture layer shown in FIG.
After VD is obtained as the delay information, VD is input to the DTS generator 33.
Save BV delay information. Next, the DTS generator 33
Since the VBV mode is set, the VBV delay information transferred from the write header analysis unit 31 and the reference time value representing the current time transferred from the STC counter unit 32 are added to obtain the decoding start time information. Get the generated DTS.

Next, the VBV / DTS replacing section 44 deletes the VBV delay information in the bit stream, and replaces it with D
The generated DTS transferred from the TS generation unit 33 is replaced.
Then, the write control unit 35 sequentially starts writing the bitstream output from the VBV / DTS replacing unit 44 into the buffer memory 12. The rest of the description is the same as that of FIG.

As described above, in the present embodiment (claim 3),
The buffer delay information indicating the delay due to the buffer set in the bitstream including the image data by the VBV / DTS replacing unit 44 is generated DT which is the decoding start time information.
Substitute S for inserting the generated DTS, which is the decoding start time information, into the bitstream. Therefore, when the decoding start is controlled based on the DTS information, the DTS is set to VBV
By replacing the delay information with the delay information and inserting it into the stream, the control for starting the reading of the bitstream from the buffer memory can be facilitated, and the control method based on the VBV delay information and the control method based on the DTS information can be decoded by the same image. It can be realized in an integrated device.

Thus, in this embodiment (claim 7),
The VBV / DTS replacing section 44 (decoding start time information replacing means) replaces the buffer delay time information representing the delay time due to the buffer set in the bitstream containing the image data with the generated DTS which is the decoding start time information. Then, the decoding start time information is inserted into the bitstream.

Therefore, when the decoding start is controlled based on the DTS information, by replacing the DTS with the VBV delay information and inserting the stream into the stream, the control for starting the reading of the bit stream from the buffer memory can be facilitated. In addition, the control method based on the VBV delay information and the control method based on the DTS information can be integrally realized in the same image decoding device.

(Third Embodiment) This embodiment (Claim 9) can be applied to the image decoding apparatus described in FIG. 1 as in the first embodiment. In this embodiment, a characteristic part of the present invention (claim 9) will be specifically described. As shown in FIG. 4, the STC counter unit 32 is usually called SCR-ext 300.
9-bit counter and 3 called SCR-base
It is composed of a 3-bit counter. SCR-ext
Counts up 27 MHz reference clock to 300
90KHZ trigger clock when SCR-ba
output to the se counter. After the SCR-base is preset to the system time base reference value SCR, 90
It is counted up by the clock of KHZ. in this way,
The STC counter unit 32 measures the reference time value and DTS
Output to the generation unit 33. If the SCR value is not included in the timing information 101, the STC counter unit 3
2 shall be self-propelled.

Next, the counter value of SCR-base or a part thereof is set to the DTS generator 33 and STC / DTS.
It is output to the comparison unit 38. Since the counter value of SCR-base is composed of 33 bits, the DTS generator 3
In step 3, the 33-bit DTS in the system stream can be added to obtain a 33-bit generated DTS. Therefore, the VBV / DTS inserting unit 34 inserts the 33-bit generated DTS. In addition, the VBV shown in FIG.
The / DTS replacing section 44 deletes the 16-bit VBV delay information and inserts the 33-bit generated DTS.

However, in SCR-base,
The time that can be measured by the counter up to 16 bits using the 90 KHZ clock is about 0.728 seconds. this is,
This corresponds to about 22 frame periods in the NTSC system video format, and generally, there is no stream that allows such a delay amount. Therefore, the generated DTS
There is no practical problem even if only the lower 16 bits of 33 bits are used. When using the 16-bit generated DTS, the VBV / DTS replacing section 44 deletes the 16-bit VBV delay information and inserts the generated DTS having the same number of bits, so that the replacement can be easily performed. At the same time, byte alignment of the bit stream (a group of various data is in units of bytes) is held, which facilitates the decoding process.

As described above, in the present embodiment (claim 9),
Since the generated DTS, which is the decoding start time information, is represented by a 16-bit length, it is possible to easily insert the decoding start time information into the bitstream, and the VB in the bitstream can be easily inserted.
It can be easily replaced with V delay information.

[0071]

Therefore, according to the present invention, the decoding start time information of each frame is obtained based on the reference time and inserted into the bit stream, and based on the decoding start time information included in the bit stream. Since the control is performed so as to start the reading of the bitstream including the stored image data, the control when starting the reading of the bitstream from the buffer memory can be facilitated.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an image decoding apparatus that is an embodiment of the present invention.

FIG. 2 is a diagram showing a hierarchical structure of MPEG2 image data.

FIG. 3 is a diagram of a multiple processing system of a picture layer of MPEG2 image data.

FIG. 4 is a block configuration diagram of a buffer memory control unit 110 of an image decoding apparatus that is an embodiment of the present invention.

FIG. 5 is a diagram showing a temporal change of a buffer occupancy rate in the buffer memory 12 of the image decoding apparatus which is an embodiment of the present invention.

FIG. 6 is a block configuration diagram of a buffer memory control unit 110 of an image decoding apparatus that is an embodiment of the present invention.

FIG. 7 is a diagram showing a conventional image decoding apparatus equipped with MPEG2.

FIG. 8 is a block diagram of a buffer memory control unit 11 of a conventional image decoding device.

FIG. 9 is a block configuration diagram of a buffer memory control unit 11 of a conventional image decoding device.

[Explanation of symbols]

 12 Buffer Memory 21 Variable Length Decoder 22 Scan Converter 23 Inverse Quantizer 24 Inverse DCT Section 25 Motion Compensated Image Reproduction Section 26 Prediction Frame Memory 31 Write Header Analysis Section 32 STC Counter Section 33 DTS Generation Section 34 VBV / DTS Insertion unit 35 Write control unit 36 Read control unit 37 Read header analysis unit 38 STC / DTS comparison unit 11, 110, 111 Buffer memory control unit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ryuji Nishito 4-36-19, Yoyogi, Shibuya-ku, Tokyo Within Graphics Communications Laboratories, Inc. (72) Inventor Kaiku Kawamura 4-chome, Yoyogi, Shibuya-ku, Tokyo 36-19 No. 19 in Graphics Communications Laboratories, Inc. (72) Inventor Norihiko Nagai 4-36-yoyogi, Shibuya-ku, Tokyo No. 36-19 in Graphics Communications Laboratories, Inc. (72) Inventor Katsumi Goto 4-36-19 Yoyogi, Shibuya-ku, Tokyo Within Graphics Communications Laboratories, Inc. (72) Inventor Shigeru Komatsu 4-36-19 Yoyogi, Shibuya-ku, Tokyo Graphics Communications, Inc. Laboratories in the

Claims (9)

[Claims] 1. An image decoding system for inputting a bit stream containing encoded image data to decode the image data, measuring a reference time, and decoding each frame based on the reference time. Decoding start time information indicating a start time is inserted into the bitstream, a bitstream including the decoding start time information is stored, the stored bitstream is sequentially read, and included in the bitstream. An image decoding system characterized by controlling to start reading a bitstream including image data stored based on the decoding start time information. 2. Buffer delay information representing a delay due to a buffer set in a bitstream containing image data,
The decoding start time information is generated based on one of decoding start time information that is additional information of the bitstream and display start time information that is additional information of the bitstream. The image decoding method according to item 1. 3. Replacing buffer delay information indicating a delay due to a buffer set in a bitstream including image data with the decoding start time information, and inserting the decoding start time information in the bitstream. The image decoding method according to claim 1 or 2, characterized in that: 4. A read start signal indicating a read start is generated when the decoding start time information contained in the sequentially read bit stream matches the measured reference time. The image decoding method according to claim 1. 5. An image decoding apparatus for inputting a bit stream containing encoded image data and decoding the image data, wherein a reference time measuring means for measuring a reference time and measurement by the reference time measuring means. Decoding start time information inserting means for inserting decoding start time information indicating the time to start decoding of each frame based on the reference time, into the bit stream, and a bit stream including the decoding start time information. And a buffer memory unit for storing the bit stream stored in the buffer memory unit, and including the image data stored in the buffer memory unit based on the decoding start time information contained in the bit stream. And a read control means for controlling to start reading of the bit stream. Apparatus. 6. Buffer delay information representing a delay due to a buffer set in a bitstream containing image data,
Decoding start time information generating means for generating decoding start time information based on one of the decoding start time information which is additional information of the bitstream and the display start time information which is additional information of the bitstream. The image decoding apparatus according to claim 5, further comprising: 7. Decoding in which buffer delay information indicating a delay due to a buffer set in a bitstream including image data is replaced with the decoding start time information and the decoding start time information is inserted into the bitstream. 7. The image decoding apparatus according to claim 5, further comprising an encoding start time information replacing unit. 8. When the decoding start time information included in the bit stream read from the buffer memory means matches the reference time measured by the reference time measuring means, the read control means reads the information. The image decoding apparatus according to claim 5, further comprising a read start signal generating means for generating a read start signal indicating the start. 9. The image decoding system and apparatus according to claim 1, wherein the decoding start time information is represented by a 16-bit length.