JPH0798362A - Ic test method with eb tester - Google Patents

Abstract

PURPOSE:To detect a defective element with no design information such as computer aided design (CAD) data by applying the same test signal to an element under test and a good element, and comparing the measured wave-forms on the same wiring. CONSTITUTION:An electron beam is radiated to a good element and an element under test, and the same test signal is applied to them from a signal generator. Secondary electrons corresponding to the potentials of wiring patterns 23a-23e are detected. This detection is made for each test cycle of the test signal and once on each wiring. Detection levels on the wiring patterns 23a-23e of the good element and the element under test are stored respectively in a wave-form file. The potential wave-forms thus obtained are compared with those on the corresponding wiring patterns of the good element and the element under test. A defective element is detected from the cycle of the test signal when the measured wave-form of the good element and the measured wave-form of the element under test are noncoincident.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor integrated circuit such as an LSI using an EB (electron beam) tester.

[0002]

2. Description of the Related Art Conventionally, when narrowing down a failure point inside an IC using an EB tester, data used when designing the IC is received from a CAD (electronic computer aided design device) database, and which IC Analysis work was in progress while deciding whether to measure the wiring. However, the design data of the IC may not be available at the quality control department or the place where testing is performed by contract.

In such a case, a method called the DFI method has been conventionally used. That is, as shown in FIG. 4A, while scanning an arbitrary region 11 of the IC device under test with an electron beam 12, each point is irradiated with an electron beam pulse, and
The second electron is detected, and the image is processed by the image processor 13 to obtain the area 1
A grayscale image corresponding to the secondary electron intensity of each point 1 is obtained. At this time, a test signal (pattern) is repeatedly input to the IC device under test, and for example, as shown in FIG. 4B, the electron beam pulse 15 is irradiated once to each point in the region 11 for each period T ₀ of the test pattern 14. To do. A case of irradiating an electron beam pulse 15 in FIG first period T ₁ in 4B, the secondary electrons successively detected from each point in every first period T ₁ of the test pattern 14, detection for each point of the region 11 Then, the electron beam pulse 15 is generated every second cycle T ₂ of the test pattern 14.
Are irradiated, and the light spots are sequentially shifted to perform measurement.

In this way, each cycle of the test pattern 14
T₁, T₂, T₃,, ...
The detected strobe potential contrast image (hereinafter strobe
Image) Im₁, Im₂, Im₃,… Is obtained. This
An IC device under test (a defective IC
Child) and a non-defective IC element. Both strobe images
The same period T_iIC device under test
If is a defective product, different strobe images will be obtained. Figure 5
Strobe image I of the IC device under test (defective product) as shown in
m₁, Im₂, Im₃,, and strobe image of non-defective IC element
Im₁′, Im₂′, Im₃′, ... with the same period
Of each corresponding position pixel of₁, I
s₂, Is₃,…make. In this figure, the cycle T₁, T ₂，
... is the same as the test strobe image and the non-defective strobe image,
T_s, A mismatched portion appears inside the area 11, and the period T_d
Can see how the disagreement reached the edge of Region 11.
It

[0005]

In order to obtain a high-quality strobe image, electron beam pulse irradiation and secondary electron detection are performed a plurality of times at each image position of the strobe image, and the average is taken to obtain the S / N ratio. When the size of the stroboscopic image is 512 × 512 pixels, the detection is 260,000 times, and it takes a long time to acquire all the data. In particular, if the length of the test signal (pattern) 14 is long, the data acquisition time becomes long, and if the averaging process is performed to improve the S / N, the average number of times becomes long, which is not practical.

If the time required to acquire all the data becomes extremely long as described above, there is a possibility that elements constituting the electron optical system and the electrical system may drift during that time. The strobe image and the strobe image obtained at the end cannot be correlated with each other, and the DFI method cannot be correctly executed. Further area 11
To obtain a strobe image, but if there is a protective film on the IC element, electrons are charged in the protective film by electron beam irradiation scanning, and adjacent scanning lines of the same wiring pattern are scanned on the previous scanning line. The secondary electrons in the scan by the next scanning line cannot be correctly detected by charging the electrons based on the above.

[0007]

According to the present invention, the wiring pattern of the IC element under test is displayed as an image by an EB tester, and each wiring of the display wiring pattern is labeled, and the IC element under test and its non-defective product. The same test signal is applied to the IC element, and the potential waveform of each wiring is measured by an EB tester. A defect analysis is performed by comparing the measured waveforms of the same wiring of the IC element under test and the good IC element.

For the IC element under test and the non-defective IC element, the potentials thereof are displayed as a grayscale image of the corresponding wiring pattern at a plurality of time points of the measured waveform. Alternatively, a plurality of time points of differences in measured waveforms of the same wiring of the IC element under test and the non-defective IC element are displayed as grayscale images of the wiring pattern.

[0009]

Embodiments of the present invention will be described with reference to the drawings. As shown in FIG. 1, first, a non-defective element and an element under test (defective element) are mounted on the same test stand in the EB tester (S ₁ ). This test stand is designed so that the same test signal (test pattern) can be simultaneously supplied from one test signal generator to both mounted elements.

Next, initial setting for obtaining a static image is performed (S ₂ ). That is, the sample (good element, defective element) is irradiated with an electron beam, and secondary electrons emitted at that time are detected,
A static image having light and shade according to the detected amount is displayed, and contrast, brightness, focus, staking, averaging, etc. are adjusted so that a good quality static image is displayed on the display unit. The magnification at this time is adjusted so that the width of the wiring pattern of the element is at least several pixels. Also, align the positions and directions of both elements.

When this adjustment is completed, the test table is moved to select the scanning area during the test, and the selected areas of the non-defective element and the element under test are scanned with electron beams while scanning the respective parts. A static image, that is, an image of each wiring pattern is obtained (S ₃ ). For example, as shown in FIG. 2A, the region 11 in the chip upper surface of the good (test) IC element 21 is selected, and the detected secondary electrons are taken into the image processor,
Noise removal and histogram processing are performed to binarize (S ₄ ), and the wiring pattern image 22 for the region 11 is shown in FIG.
As shown in B, the wiring portion 23 and the other portion (semiconductor portion) 24 have different densities, and in this example, the wiring portion 23 having a high density is obtained.

Based on the obtained wiring pattern image 22, the position and direction (alignment) of the non-defective device and the device under test are aligned.
Is performed so that the designated same spot can always be easily irradiated with the electron beam (S ₅ ). Next the mode of selection of manual setting mode or automatically setting the electron beam irradiation point at potential waveform measurement and inspection (S _6).
When automatic mode is selected, wiring pattern image (binary image)
Then, pattern recognition is performed by histogram processing to recognize the wiring pattern (wiring portion) 23 (S ₇ ).

Labeling is performed on each of the recognized wiring patterns 23, and for example, as shown in FIG. 2B, the wiring patterns 23a, 23b, 23c, 23 are arranged from left to right.
d, 23e and sequentially give the label (S _8). Probing points one point on each of these wiring patterns 23 a - 23 e, that is, as the electron beam irradiation point, and stores the probing point to a file (S _9). When manual mode is selected in step S _6, and selects the probing points in its manually stores the respective points in the file (S _9). Determining these probing points and putting them in the file is done only for non-defective devices.

In order to reduce the electron beam irradiation mistake on the probing point determined in this way, the electron beam is irradiated in the X direction or the Y direction about each probing point from the memory file of the probing point. The process of moving, detecting the edge of the wiring pattern, recognizing the edge, detecting the center of the wiring pattern in the width direction, and irradiating this point with an electron beam to enable accurate probing. It is carried out (S _10). The detected potential is different between the center and the edge of the wiring pattern,
This problem is solved as described above.

Next, the non-defective element and the element under test are irradiated with an electron beam at the probing point determined as described above, and the non-defective element and the element under test are subjected to the same test pattern from the test signal generator. It was generated application, detecting secondary electrons corresponding to the potential of the wiring patterns 23a~23e at that time (S _11). This detection is performed for each test cycle of the test pattern, and once for each wiring, and each wiring pattern 23a-2 of the non-defective element and the element under test is tested.
For each of the 3e, the detected voltage level is stored in the waveform files 26 and 27, respectively. The relationship between the test pattern and the electron beam irradiation is the same as the conventional one, and is performed as shown in FIG. 4B, for example, but the electron beam irradiation is performed not for each pixel but for each wiring pattern.

The potential waveforms thus obtained are compared with respect to the corresponding wiring patterns of the non-defective device and the device under test. For example, when the measured waveform of the non-defective element for the wiring pattern 23a is as shown in FIG. 3A and the measured waveform of the element under test is as shown in FIG. You can know the _n- 2th cycle, and the defective wiring is the wiring pattern 2.
In 3a, it can be known that the defect is the T _{n− 2} cycle-th cycle on the time axis.

Since the wiring pattern image (static image) of the region under test 11 is obtained in advance, the potential waveform of the test waveform of each test cycle T ₀ , T ₁ , T ₂ , ... The density corresponding to each potential is determined by the wiring pattern 23a,
23b, ... Wiring pattern images (referred to as strobe images) given to each of them are non-defective elements, as shown in FIGS.
The device under test is created (S ₁₃ ). It is also possible to simultaneously display and compare the strobe images 28 ₀ , 28 ₁ , 28 ₂ , ... Of these non-defective devices and the strobe images 29 ₀ , 29 ₁ , 29 ₂ , ... Of the device under test (S ₁₄ ). This finds a physical defect.

Further, non-defective element strobe images 28 ₀ , 28 ₁ ,
28 ₂ , ..., Strobe images of the device under test 29 ₀ , 29 ₁ ,
By creating the difference images 31 ₀ , 31 ₁ , 31 ₂ , ... With 29 ₂ , ..., It is also possible to know the propagation state of the defect by the display method close to the conventional method described in FIG. This difference image 3
Waveform file 2 is used to create 1 ₀ , 31 ₁ , 31 ₂ , ...
6 and 27, the difference between the measured waveforms of the corresponding wiring patterns is obtained, and the potential in each test cycle of the difference waveform of each wiring pattern is superimposed on the corresponding wiring pattern of the wiring pattern image by the grayscale information. create.

Not only the measurement in which the electron beam irradiation is performed once for each measurement point every time the test pattern is run once,
Accelerate the measurement by the so-called multi-sampling method, in which electron beam irradiation is performed at multiple cycle positions that are shifted in time so that the measurement results do not affect each other while the test pattern is running once. You can also Further, it is possible to improve the S / N by averaging the measurement results by performing the measurement in the same test cycle a plurality of times for the same measurement point by running the test pattern a plurality of times.

[0020]

As described above, in the present invention, the wiring pattern image is first obtained and the measurement point is recognized from the wiring pattern image, so that the failure analysis can be performed without design information such as CAD data. . Moreover, for each wiring pattern, if there is no change in the input / output state, use the same potential at any position of the wiring pattern,
For each wiring pattern, the waveform measurement is performed with one measurement point, so the measurement time is significantly shorter than when measuring the data at each pixel point. Therefore, the same point can be measured multiple times. The S / N can be improved. The data amount is, for example, 260 kB when it is calculated for each pixel in the related art, whereas it is 1 kB in the present invention.
It's done.

Further, since the measurement time is short, the drift of the elements such as the electron optical system and the electric system can be ignored at the initial and final stages of the measurement, and the correct measurement can be performed. Further, since the same wiring pattern is set to one measurement point instead of measurement for each pixel, the electron beam is not irradiated adjacent to one measurement point, and therefore the protective film is also affected by charging. hard.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention.

FIG. 2A is a diagram showing an example of a relationship between an IC of a sample and a measurement region 11 at one time, and B is a diagram showing an example of an irradiation pattern image.

3A and 3B are diagrams showing examples of measurement waveforms, and C is a diagram showing a re-trained strobe image and a difference image thereof.

4A is a diagram showing a procedure for obtaining a strobe image by a conventional EB tester, and FIG. 4B is a diagram showing an example of a relationship between a test pattern and electron beam irradiation.

FIG. 5 is a diagram for explaining failure tracking using a conventional strobe image and a difference image thereof.

Claims (3)

[Claims] 1. A step of displaying a wiring pattern of an IC element under test as an image by an EB tester, a step of labeling each wiring of the display wiring pattern, and an IC element under test and its non-defective IC element, An EB tester comprising the steps of applying the same test signal and measuring the potential waveform of each wiring with an EB tester, and comparing the measured waveforms of the same wiring of these IC element under test and non-defective IC element. IC test method by. 2. The method according to claim 1, further comprising a step of displaying potentials of a plurality of time points of a waveform measured for the IC device under test and the non-defective IC device as grayscale images of a corresponding wiring pattern. IC test method by EB tester. 3. The method according to claim 1, further comprising a step of displaying a plurality of time points of difference in measured waveforms of the same wiring of the IC element under test and the non-defective IC element as a grayscale image of the wiring pattern. IC test method by EB tester.