JPH0795855B2 - SCH phase detector for PAL signal - Google Patents

Description

The present invention relates to an SCH phase detecting device for detecting whether or not the SCH phase (phase relationship between a subcarrier and a horizontal synchronizing signal) of a PAL video signal is within a certain standard. It is about.

2. Description of the Related Art For example, when combining two or more video signals in a switcher or VTR editing, if the SCH of each video signal does not match, the change in color tone and the horizontal direction of the image at the signal switching point A decrease such as a shift occurs. Therefore, it is necessary to detect whether the SCH of the video signal is within a certain standard.

A conventional SCH phase detecting device satisfying such conditions is disclosed in, for example, Japanese Patent Laid-Open No. 62-237883.

FIG. 4 shows a block diagram of a conventional SCH phase detector. In the figure, 1 is a color video signal input terminal, 2 is an APC circuit, and a signal SSC phase-synchronized with a subcarrier of the color video signal is obtained at its output.
Reference numeral 3 denotes a sync signal separation circuit, which separates the horizontal sync signal SH from the color video signal. A color frame detection circuit 4 outputs a color framing signal SCF serving as a reference for detecting the SCH phase. A D flip-flop 5 is supplied with the color framing signal SCF at the D input terminal and the horizontal synchronizing signal SH at the clock terminal. Reference numerals 6 and 7 denote delay circuits. The delay circuit 6 delays the output signal of the D flip-flop 5 by a predetermined time T1 and outputs a pulse P1, and the delay circuit 7 further delays the pulse P1 by a time T2 and outputs a pulse P2. To do. Reference numerals 8 and 9 denote D flip-flops. The D input terminal thereof is supplied with the signal SSC phase-synchronized with the subcarrier, the clock terminals thereof are supplied with the pulses P1 and P2, and the respective output terminals thereof are supplied with the pulses P1 and P2. The polarity of the signal synchronized with the subcarrier phase at the rising edge of is output. These output signals S1 and S2 are supplied to the decoder 10, the range of the SCH phase is determined, and the result is output from the output terminal 11.

The operation of the conventional SCH phase detection device configured as described above will be described below.

For example, in the case of the NTSC system, the color field is 4 fields as shown in FIG. 5A, and the color framing signal SCF is a signal of period 4TV which rises in the first field as shown in FIG. 5B. This color framing signal SCF is latched by the horizontal synchronizing signal and delayed by the delay circuit 6 for a predetermined time T1, and its rising time is the time from the horizontal synchronizing signal.
A pulse P1 delayed by T1 is obtained. The pulse P1 is further delayed by the time T2 in the delay circuit 7 to obtain a pulse P2 (D in the figure). FIG. 6 shows the relationship between the pulses P1 and P2 shown in FIG. 6 and the signal SSC phase-synchronized with the subcarrier.
B in FIG. 4 shows pulse P2, and C to F in FIG.
It shows two different phase relationships. In the case of FIG. 6C, the signals S1 and S2 are “1” and “1”, respectively, “0” and “1” in FIG. D, “0” and “0” in FIG. They are "1" and "0". Here, the SCH detection range can be adjusted by changing the delay times T1 and T2. For example, SCH is from -30 ° to +3
To set the signals S1 and S2 to "1" and "1" in the range of 0 °, when T2 is input to the video signal of SCH 0 at 1/3 (93nS) of the cycle of SSC, pulse P1, The midpoint of the rising edge of P2 is the signal SS
Adjust so that it comes to the midpoint of the positive part of C.

However, in the above configuration, the SCH phase is detected by the NTS.
Once in 4 fields in the C method and once in 8 fields in the PAL method, and compared with this, the period of the subcarrier is very short, NTSC method 279nS, PAL method 226nS. It is difficult to accurately observe the relative relationship between the subcarrier and the first and second detection points with a simple measuring instrument, and complicated adjustment is required to determine the times T1 and T2.
In particular, in the case of the NTSC system, the relationship between the subcarrier and the horizontal sync signal is the same every two lines, but in the case of the PAL system, there is a slight deviation from line to line, and the same condition occurs only once in eight fields. Therefore, it is difficult to directly observe the relationship between the subcarrier and the horizontal sync signal. Further, in the case of the NTSC system, the SCH is detected once every four fields, but in the case of the PAL system, it is once every eight fields. Because of the stability of the detection, the response will be delayed because the determination will be made several more times.

In view of the above points, the present invention aims to provide a PAL-type SCH phase detection device that solves such a conventional problem, has a large number of detections, and is easy to set and adjust the SCH phase detection range. .

Means for Solving the Problems The present invention provides a means for obtaining a color framing signal that serves as a reference for detecting a SCH phase, a signal phase-synchronized with a subcarrier of a PAL system color video signal, and horizontal synchronization of the color video signal. A signal having a time difference of TA with respect to the signal and phase-synchronized with the subcarrier at the detection point set by the first pulse of the period 2TH or 4TH divided by 2 or 4 in synchronization with the color framing signal. And a second pulse having a time difference of a constant period TB with the same period as the vertical synchronizing signal or a vertical pulse having a time difference of a constant time TB with the vertical synchronizing signal and synchronizing with the color framing signal. The second pulse having a period of 2TV, which is divided by two, and a means for forming a third pulse by delaying the second pulse by a predetermined time TC,
A means for determining the range of the SCH phase from the polarity of the detection point at the timing determined by the second and third pulses.

Effect The present invention has the above-described configuration to obtain the polarity signal of each detection point of the signal period 2TV at the sampling period 2nTH, and adjust the time TA or TB while observing the polarity signal and the second and third pulses. The detection point can be set by
The SCH phase discrimination range can be set accurately by changing the time TC.

FIG. 1 is a block diagram of a PAL type SCH phase detection device according to an embodiment of the present invention shown in FIG. In the figure,
Reference numeral 1 is an input terminal for a color video signal, 2 is an APC circuit, and a signal SSC phase-synchronized with a subcarrier of the color video signal is obtained at an output thereof. Reference numeral 3 denotes a sync signal separation circuit, which separates the horizontal sync signal SH and the vertical sync signal SV from the color video signal. A color frame detection circuit 4 outputs a color framing signal SCF serving as a reference for detecting the SCH phase. The period is 8 TV in the case of PAL system. Reference numeral 12 is a polarity detection circuit, which includes a frequency dividing circuit 13, a delay circuit 14, and a D flip-flop 15. The frequency dividing circuit 13 divides the horizontal synchronizing signal into four while synchronizing with the color framing signal, and the delay circuit 14 delays the output of the frequency dividing circuit 13 by a predetermined time TA and outputs a pulse PH. The signal SSC is supplied to the D input terminal of the D flip flop 15, the pulse PH is supplied to the clock input terminal, and the output terminal thereof is a signal phase-synchronized with the subcarrier of the color video signal at the detection point determined by the pulse PH. The polarity signal SP is obtained. A pulse forming circuit 16 outputs a pulse PV1 having a constant relationship with the vertical synchronizing signal. Reference numeral 17 denotes a delay circuit which delays the pulse PV1 by a predetermined time TC and outputs a pulse PV2. Reference numerals 18 and 19 denote D flip-flops. The D input terminal thereof is supplied with the polarity detection circuit 12 output signal SP, the clock terminals thereof are supplied with the pulses PV1 and PV2, and the respective output terminals are supplied with the pulses PV1 and PV2. Signal at rising
Signals S1 and S2 obtained by sampling SP are output. These output signals are supplied to the decoder 20, the range of the SCH phase is determined, and the output signal is output from the output terminal 21. 22 is an observation terminal for observing the output of the polarity detection circuit 12 and 23 is an observation terminal for observing the output of the delay circuit 17.

The operation of the SCH phase detection device of this embodiment configured as described above will be described below.

In the case of the PAL system, the color field is 8 fields as shown in FIG. 2A, and the color framing signal SCF
Is the cycle of rising in the first field as shown in FIG.
8 TV signal. Further, there is a relationship of FSC = (1135/4 + 1/625) FH between the horizontal sync frequency FH and the vertical sync frequency FV, and FH = 625FV / 2 subcarrier frequency FSC and the horizontal sync frequency FH.

Now, assuming that 8 fields of the PAL system color field are one unit, and adding a number to each line in the 8 fields starting from the first line of the first field (called line 1), the final line becomes 2500. In the polarity detection circuit 12, the frequency divider circuit 13 synchronizes with the color framing signal SCF
By dividing, for example, lines 1, 5, 9, ..., 2497 are selected and output. The reason for thinning the lines is that in line 1, the phase between the subcarrier and the horizontal synchronization signal is 0 degree, line 2 is 270.576 degrees, line 181.152 degrees, and line 5 is 2.30 degrees.
It is 4 degrees, and when expressed by a general formula, on line L, D = (0.576 ° + 270 °) * (L-1) (L is an integer), but if D is thinned out every four lines, D1 = 0.576 ° * (L-1) (L = 4a-3) D2 = 0.576 ° * (L-1) + 270 ° (L = 4a-2) D3 = 0.576 ° * (L-1) + 180 ° (L = 4a-1) D4 = 0.576 ° * (L-1) + 90 ° (L = 4a) However, a is an integer from 1 to 625, which is a signal of 625 lines, that is, two field periods. Therefore, the signal whose polarity is detected every four lines of the signal SSC is also a signal of cycle 2TV.

FIG. 2C shows the output SP of the polarity detection circuit 12, and the phase of this signal with respect to the vertical synchronizing signal SV can be freely set by changing the delay time TA of the delay circuit 14. Further, this phase changes by the same amount when the SCH of the input video signal changes. Therefore, the SCH of the input video signal can be determined by detecting this phase amount. The detection accuracy in this case is 2.034 °.

The pulse forming circuit 16 outputs a signal pulse PV1 phase-synchronized with the vertical synchronizing signal SV. This cycle can be TG or 2TV. However, at the time of TV, the sign of the output SP of the polarity detection circuit 12 is inverted in the odd / even field, so that it is necessary to synchronize the decoder 20 with the color framing signal SCF to determine the polarity. Further, in the case of 2TV, it is necessary to synchronize the frequency division by 2 with the color framing signal SCF. Also, the pulse P
The rising timing of V1 may have a fixed relationship with the vertical synchronizing signal SV. Let this time be TB. Fig. 2D
Indicates the pulse PV1 in the case of the period 2TV. FIG. 6E shows an output signal pulse PV2 of the delay circuit 17 obtained by delaying the pulse PV1 by the time TC. The relationship between C, D and E in FIG. 2 is when the D flip-flops 18 and 19 output signals S1 and S2 are "1" and "1", respectively. Here, the SCH detection range can be adjusted by changing the delay times TA, TB, TC. For example, in order to set the signals S1 and S2 to "1" and "1" in the range of SCH from -45 ° to + 45 °, TC is set to 1/4 (156TH) of the output period of the polarity detection circuit 12, S
When a video signal of CH 0 is input, TA or TB may be adjusted so that the midpoint of the rising edges of the pulses PV1 and PV2 is at the midpoint of the positive portion of the polarity detection circuit 12 output. The value of either one of TA and TB which is not used for adjustment may be 0. Further, since TC may be set in TH units, it can be accurately set without adjustment using a counter or a mono-multivibrator.

As described above, according to this embodiment, the detection period is 2 fields, and the SCH discrimination range is the time T while observing the observation terminals 22 and 23.
It can be easily set by adjusting A or TB and TC.

FIG. 3 is another example of the configuration of the polarity detection circuit 12 in FIG. 1, which includes a frequency divider circuit 24, a delay circuit 14, a frequency divider circuit 25, a D flip-flop 15, and a switching circuit 26. The frequency dividing circuit 24 divides the horizontal synchronizing signal SH by two, and the delay circuit 14 divides the horizontal synchronizing signal SH by two.
The output is delayed by TA for a predetermined time and a pulse PH1 is output. Further, the frequency dividing circuit 25 divides the pulse PH1 into two and outputs the pulse PH2. Here, the frequency dividing circuits 24 and 25 are synchronized with the color framing signal SCF. D of D flip-flop 15
The output signal SSC of the APC circuit 2 is supplied to the input terminal, the pulse PH1 is supplied to the clock input terminal, and the polarity signal of the signal phase-synchronized with the subcarrier of the color video signal at the detection point determined by the pulse PH1 is supplied to the output terminal. SSC is obtained. The switching circuit 26 switches the two outputs of the D flip-flops 15 having opposite polarities by using the pulse PH2 as a control signal and outputs the signal SP.

As a result, the sampling cycle of the polarity detection circuit becomes 2TH, and the SCH phase discrimination accuracy is 1.152 degrees, which is double that in the case of FIG.

As described above, according to the present invention, the sampling period
Polarity signal of each detection point of signal period 2TV is obtained with 2nTH, and time TA is observed while observing this polarity signal and the second and third pulses.
By adjusting, it becomes easy to set the detection point. Further, the time TB for setting the SCH phase discrimination range is a value from TV / 4 to TV / 3 in TH units, which can be set accurately using a counter or a monomatic vibrator. Further, the detection cycle is 2 TV or 4 TV, and the number of times of detection is 4 times or 8 times that of the conventional method, so that the detection response can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of a SCH phase detection device according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram thereof, FIG. 3 is a block diagram showing another example of the configuration of a polarity detection circuit, and FIG. FIG. 5, FIG. 6 and FIG. 6 are block diagrams of the SCH phase detector of FIG. 1 ... color video signal input terminal, 2 ... APC circuit, 3
...... Synchronous signal separation circuit, 4 ...... Color frame detection circuit, 12 ...... Polarity detection circuit, 13,24,25 ...... Division circuit, 14,1
7 ... Delay circuit, 15,18,19 ... D flip-flop, 16
...... Pulse forming circuit, 20 …… Decoder, 21 …… Output terminal, 22,23 …… Observation terminal, 26 …… Switching circuit.

Claims (1)

[Claims] 1. A means for obtaining a signal phase-synchronized with a subcarrier of a PAL color video signal, and means for separating a horizontal sync signal (sync TH) and a vertical sync signal (cycle TV) from the color video signal. Means for obtaining a color framing signal (cycle 8TV) serving as a reference for detecting the SCH phase, and having a time difference of a predetermined time TA with the horizontal synchronizing signal, and for 2 or 4 minutes while synchronizing with the color framing signal. A means for detecting the polarity of the signal phase-synchronized with the subcarrier at the detection point set by the first pulse of the cycle 2TH or 4TH, and having a time difference of a certain period TB with the same cycle as the vertical synchronization signal. The second pulse of the synchronous 2TV which has a time difference of 2 pulses or the vertical synchronizing signal with the above-mentioned vertical synchronizing signal, and is divided by 2 while synchronizing with the color framing signal. The range of the SCH phase is determined from the means for forming a third pulse by delaying the second pulse by a certain time TC and the polarity of the detection point at the timing determined by the second and third pulses. SCH phase detecting apparatus for PAL signal, comprising: