JPH0792902A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide the programmable controller capable of making high-speed processing by a pipeline system of simple circuitry without providing additive circuits. CONSTITUTION:A control section 15 of this programmable controller 10 has a control section 20 to control the operations of respective sections so as to store the instruction read out of an instruction memory section 11 into an instruction register 13, to output the result obtd. by processing in an arithmetic section 14 to an execution result storage section 12, to read out the next instruction after determination of output data and to store the instruction into the instruction register 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly to a high-speed processing technique in a pipeline system, that is, a control system in which reading and execution of program instructions are processed in an overlapping manner.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional programmable controller. That is, 1 is a storage unit that stores a program, 2 is an input unit that receives an input signal, 3 is a CPU that executes the program according to the input signal, 4 is an output unit that outputs the calculation result of the CPU 3 to an external device, 5 Is a system storage unit that stores the execution processing procedure of the program.

FIG. 6 is a diagram showing the timing of the sequential processing of the conventional programmable controller, that is, the method of performing the execution processing after the reading of the program instruction, and subsequently performing the reading and the execution alternately and continuously. However, in this processing method, the instruction cannot be executed during the instruction reading time, and the total processing time is about twice as long as the time required to access the stored instruction. Therefore, in order to realize high-speed processing of programs,
In the pipeline method, that is, in the instruction processing time by the so-called pipeline method, in which the next instruction is read in parallel with the reading and execution processing of the first instruction, and the reading and execution processing are performed in parallel in the following. Have been devised to shorten.

[0004]

The pipeline method can theoretically speed up the processing time to about one time the memory access time. Generally, a detailed analysis of the instruction processing steps by the pipeline is as follows: F (Fetch): Read instruction from storage unit to instruction register D (Decode): Decode instruction in operation unit EA (Execution address): Instruction execution address generation E (execution): Execution of an instruction by the control unit can be divided into four stages, but usually after decoding the instruction and generating the execution address, the amount of information as data increases. , The number of bits in a register for storing data increases. The scale of the sequence circuit greatly differs depending on the position of the above steps (1) to (3) where the break in the processing step, that is, the point where the calculation is temporarily stopped in the middle of the program is provided. For example, if an instruction with an opcode of 16 bits and an operand of 16 bits is read from the storage unit, the entire instruction of the instruction register is 32 bits.
Is a bit. In the decoding step in the arithmetic unit, the operand is left unchanged, and a part of the opcode is used for 80 arithmetic control signals, 16 register control signals, and 16 I / O addresses.
A total of 120 signals are generated, including a book, 16 memory addresses, and 16 I / O addresses and 16 memory addresses in the execution address generation step.
In the last instruction execution step of the book, I / O address 1
6 lines, memory address 16 lines, operation data 16 lines, I /
A total of 56 O control signals and 4 memory control signals output the calculation result. In this way, various signals are generated from the 32-bit instruction. Therefore, when each step is divided, a large difference occurs in the number of bits for temporarily storing the state. In other words, the number of bits in the register for storing the result increases depending on where the processing break is placed.

In order to transfer data from the instruction register to the arithmetic unit in the middle of processing, if an instruction reading and an instruction execution are attempted at the same time, the execution result is not stored in the storage unit. Since the next instruction is read and the content of the arithmetic unit changes, the processing of the instruction cannot be performed if the respective processes are perfectly synchronized for speeding up. In view of this, Japanese Patent Laid-Open No. 59-135506 provides an external register for temporarily storing instructions between the CPU and the memory, and an external additional circuit so that the contents of the arithmetic unit do not change during the process. Have been disclosed.

The present invention has been made for the purpose of providing a programmable controller of a pipeline system capable of executing high-speed processing at a low cost without providing the above-mentioned additional circuit.

[0007]

[Means for Solving the Problems] Means for solving the above problems are described in the claims. That is, an object of the present invention is to provide a storage unit that stores a program,
An input unit that receives an input signal, a CPU that executes the program according to the input signal, an output unit that outputs a calculation result of the CPU to an external device, and a system storage unit that stores an execution processing procedure of the program In a programmable controller, an instruction storage unit that stores a program instruction, a storage unit that includes an execution result storage unit that records the execution result of the instruction, an instruction register that stores the instruction read from the instruction storage unit, and the instruction is decoded It has a CPU composed of an arithmetic unit and a control unit for instructing the execution of the above-mentioned instruction, and the reading of the instruction and the subsequent decoding, execution address generation, and execution of each processing are performed after the reading of the above-mentioned instruction. The following steps are started in parallel and continuous processing is performed by timing control. It is accomplished by rollers.

[0008]

With the above construction, it is possible to perform high-speed processing without providing a special additional circuit to the programmable controller that performs processing by the pipeline method, and the conventional serial processing method by changing the operation timing. Is also possible, and reading of the instruction and execution of the instruction can be performed in parallel.

[0009]

1 is a block diagram showing the configuration of a programmable controller 10 according to an embodiment of the present invention. The input unit 2, the output unit 4, and the system storage unit 5 have a configuration according to the related art. The CPU 20 includes an instruction register 13,
The storage unit includes a calculation unit 14 and a control unit 15, and the storage unit is the instruction storage unit 1.
1 and the execution result storage unit 12. The feature of this embodiment is that
The storage unit has an instruction storage unit 11 and an execution result storage unit 12,
The instruction storage unit 11 stores an instruction converted into a specific code and outputs an instruction read address to the instruction register 13. The instruction register 13 is a register for temporarily storing the instruction read from the instruction storage unit 11. The execution result storage unit 12 outputs the execution address to the CPU 20 and also stores the execution result by the calculation unit 14.

Next, the operation of this embodiment will be described with reference to FIGS. Basic operation clock 21 as shown in FIG.
Accordingly, the control unit 15 outputs the instruction read address 22a and reads the instruction 23a into the instruction register 13. Next, the processing of this instruction 23a is performed by the arithmetic unit 14 to output the execution address 24a, and the arithmetic result 25a is output to the execution result storage unit 12. Immediately after the output data is fixed, the next instruction 23b is stored in the instruction register 13. In this way, the instructions 23a, 23b, ... Can be read and executed at the same time, and the pipeline is delimited immediately after the instruction is read. Therefore, only by providing the instruction register 13 for reading the instruction, the instruction 23a can be provided. , 23b ... Can be continuously read out and simultaneously executed simultaneously. Therefore, high-speed processing can be continuously performed, and therefore the circuit configuration can be simplified. This makes it possible to set the processing time for one instruction to a time approximately equal to the memory access time.

FIG. 3 shows an instruction register 13, an arithmetic unit 14,
3 is a block diagram showing a configuration of a CPU 30 of the programmable controller 50 when the control unit 15 is one LSI. FIG. The instruction register 13, the arithmetic unit 14, and the control unit 15 are incorporated into one LSI 32, and the instruction processing is performed by the LSI 3
2 is configured to execute. The instruction register 13, the arithmetic unit 14, and the control unit 15 are incorporated in the LSI 32 so that the processing of instructions can be performed by hardware, and the processing of the pipeline system is performed by the configuration of this CPU. This is an embodiment showing that the execution speed can be increased. In the above processing, the processing time is limited only by the memory access time. Therefore, in FIG. 1, if a memory having a high-speed processing capability is used for the instruction storage unit 11 and the execution result storage unit 12, the same circuit configuration is used. By this, it is possible to execute a further advanced high-speed processing.

FIG. 4 is a diagram showing the configuration of another embodiment. In the embodiment of FIG. 1, the instruction register stores only one instruction, but the instruction register 43 of this embodiment can store a plurality of instructions. It was done like this. If you do this, J
Even if there is an MP instruction etc., the branch address after the JMP instruction can be read in advance, and when the JMP instruction is read, the processing can be immediately transferred to the target branch destination and high-speed processing can be executed. Becomes Figure 5
4 is a diagram showing a relationship between an instruction register 43 and an instruction storage unit 41. FIG. The instruction is read from the instruction storage unit 41 and transferred to the instruction register 43, and at the same time, the instruction already stored in the instruction register 43 is pushed, that is, transferred.
By doing so, it becomes possible to read the instruction after several steps.

The specific configuration and effect of an embodiment in which the processing system and configuration of the present invention are applied to a CPU of a programmable controller will be described below. By applying this embodiment, the steps of the pipeline system, that is, instruction reading 200 ns decoding 3 ns execution address generation 3
In the ns execution of 200 ns, the processing time of 200 ns was shortened by setting the delimiter position immediately after the instruction reading. Further, as a result, the cost can be reduced by about 10%, and the size of the main body of the apparatus can be reduced by about 20%.

[0014]

According to the programmable controller of the present invention, the execution address register, which is required in the normal pipeline processing circuit configuration, is unnecessary, and high-speed processing is possible without providing a special additional circuit. Since the circuit configuration is simple, it is extremely effective in reducing the cost of the entire device. Further, the present invention has a remarkable effect that it can be adapted to a conventional method of repeatedly executing instruction reading and execution by slightly changing the timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a programmable controller of the present invention.

FIG. 2 is a diagram showing an operation timing of outputting an instruction read address and reading it to an instruction storage register according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a CPU of another embodiment of the programmable controller of the present invention.

FIG. 4 is a block diagram showing an instruction register capable of storing a plurality of instructions in another embodiment of the present invention.

5 is a detailed view showing the relationship between the instruction register and the instruction storage unit of FIG.

FIG. 6 is a diagram showing a timing of a processing method of a conventional programmable controller.

FIG. 7 is a block diagram showing a configuration of a conventional programmable controller.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Storage unit 2 ... Input unit 3, 20, 30 ... CPU 4 ... Output unit 5 ... System storage unit 10, 50 ... Programmable controller 11, 41 ... Instruction storage unit 12 ...
Execution result storage unit 13, 43 ... Instruction register 14 ...
Arithmetic unit 15, 45 ... Control unit 16 ... Instruction read bus 17 ...
Execution bus 18 ... Instruction data bus 19 ...
Control symbol 21 ... Operation clock 22 ...
Instruction read address 23 ... Instruction 24 ...
Execution address 25 ... Execution result 32 ... LSI 33 ...
Microcomputer 34 ... Microcomputer data bus 35 ...
Peripheral interface 36 ... External I / O bus

Claims (1)

[Claims] 1. A storage unit for storing a program, an input unit for receiving an input signal, a CPU for executing the program according to the input signal, an output unit for outputting a calculation result of the CPU to an external device, and In a programmable controller having a system storage unit that stores a program execution processing procedure, an instruction storage unit that stores a program instruction, a storage unit that is an execution result storage unit that records an execution result of the instruction, and read from the instruction storage unit An instruction register for storing the instruction, an arithmetic unit for decoding the instruction, and a CPU including a control unit for instructing the execution of the instruction, and reading the instruction and subsequent decoding, execution address generation, and execution processing. After reading the above-mentioned instruction, the following processing for reading the next instruction is started in parallel, and the timing control continues. A programmable controller characterized by performing processing.