JPH0792501A - Substrate for image display and its production and tft display element - Google Patents

Abstract

PURPOSE:To simultaneously process polycrystalline layer forming stages for both driving circuits for rows and columns at a high speed by arranging the TFTs of peripheral circuits in a straight form. CONSTITUTION:Pixel regions 5 where pixel electrodes 5a and pixel driving TFTs 10A arranged in a grid form, the column driving circuit 7 and the row driving circuit 6 are disposed. The respective circuits are provided with row driving TFTs 10B1, 10B2..., 10Cx... and column driving TFTs 10Dx..., 10Ex..., 10Fx.... The respective TFTs are arranged in nearly the straight form in a direction parallel with row electrode lines. Since TFTs are arranged and constituted in the straight form in such a manner, extremely high productivity and yield are obtd. in the polycrystallization stage for alpha-Si (amorphous silicon). The variation in the characteristics of the TFTs which are main circuit elements arises less with the substrate for image display obtd. in such a manner and the substrate is capable of exhibiting stable performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as a thin film transistor) having a polycrystalline semiconductor channel in an image display substrate (also referred to as an active matrix display device, a thin film active device substrate, or a TFT substrate) provided with an active device. (TFT), and the T using it
The present invention relates to an FT display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for flat panel displays as display devices to replace CRTs, and the most promising of these is the liquid crystal display element (LC).
D). Recently, an active matrix type LCD using a TFT or the like has been put into practical use in response to the demand for colorization and high speed.

Amorphous silicon (α-Si) is generally used as a semiconductor layer in a TFT, but α-S
When polycrystalline Si is used in place of i, the mobility is high, so that the TFT can be downsized and operated at high speed, and a large-screen / high-density liquid crystal display device can be realized. Further, it becomes possible to simultaneously form the driving circuit together with the pixel display TFT on the same substrate.

Polycrystalline Si has a temperature of about 1000 ° C. on a quartz substrate.
The method of forming at a high temperature and the method of forming on a glass substrate at a low temperature of 600 ° C. or lower are both known. There is also known a method of irradiating α-Si with a laser beam spot and performing beam annealing in a room temperature atmosphere to obtain polycrystalline Si.

In order to increase the screen size of an LCD and to obtain a product with higher productivity and higher performance, polycrystalline Si is used as an ordinary glass substrate for LCD (Corning 7059).
Etc.) is desired. Moreover, a low temperature process of 600 ° C. or lower is required. To achieve this,
The beam annealing method described above is promising.

As a method of forming polycrystalline Si by beam annealing, there is a first method of beam annealing the entire surface of the substrate or the entire necessary region of polycrystalline Si without any gap. Further, there is a second method of skipping a portion that does not require beam annealing. The former is like an excimer laser,
A large number of lasers that have a large laser irradiation area by pulse oscillation are used. Beam annealing of a continuous wave laser such as an argon ion laser is used for the latter. The latter is used to improve throughput by requiring high-speed processing.

In addition, polycrystalline silicon is described on pages 103 to 109 of Nikkei Electronics No. 602 (2/28/94).
There is a description of the TFT liquid crystal panel, which will be described.

At present, it is difficult for the beam annealing (laser beam annealing) method to uniformly control the mobility of polycrystalline Si in the plane. Moreover, a large-diameter laser device capable of collectively irradiating a large substrate has not been obtained at present. Therefore, a large-sized substrate is annealed by scanning with a pulse laser having a diameter of about 5 to 10 mm. The problem in this case is
Since overlapping portions are formed by laser processing, in-plane variations in mobility of about ± 50% may occur, and TFT characteristics may vary.

As a countermeasure for this, it is possible to reduce the processing speed to reduce the overlapping portion of polycrystalline Si as much as possible. Alternatively, it has become possible to suppress the variation, which can be prototyped at the laboratory level, to about ± 10% by performing the laser processing a plurality of times. Another issue for mass production is how to increase the processing speed while suppressing nonuniformity.

The above is the outline described on pages 106 to 107. Next, the high-speed beam annealing method (high-speed beam annealing method, hereinafter also referred to as HSBA) will be described. This is one of the beam annealing methods, and its major feature is that the beam spot is first scanned at high speed. For example, the laser output is about 7 to 25 W and the scanning linear velocity is 10 to 20 m / s, preferably 10 to 15 m / s.
s, more preferably 11 to 13 m / s (when the beam spot diameter is approximately 100 μm). Further, JP-A-4-226039 and JP-A-4-2260 relating to a method for forming a polycrystalline Si TFT using this HSBA.
Japanese Patent Laid-Open Publication No. 40 is given as Conventional Example 1. According to this HSBA, it becomes possible to polycrystallize α-Si at a process temperature of 450 ° C. or lower.

In this HSBA, beam annealing is performed only on a portion forming a silicon island (Si island) which becomes a polycrystalline semiconductor active layer of a TFT. Other than that, beam annealing is not performed on the portions having only wirings and pixel electrodes. For example, when a pixel display TFT provided with polycrystalline Si is formed on a substrate by using a scanning type beam annealing device, the laser beam is scanned by the same number of times as the number of rows of a matrix forming a screen. And then irradiate.

Next, as a second conventional example, Japanese Patent Publication No. 5-9794
I will give you a bulletin. The present invention is characterized in that only the non-single crystal SiTFT of the peripheral drive circuit other than the pixel region of the LCD is laser-annealed. For example, only the peripheral drive circuit portion is laser-annealed while scanning the beam in the left and right directions with a beam diameter of 200 μm using a CW-excited YAG laser as a light source and a linear velocity of 50 cm / s.

Further, in the prior art example 2, it is described that if the laser annealing is applied to the entire surface of the substrate, the throughput of the manufacturing process is extremely deteriorated due to the low linear velocity, which is not practical. Therefore, only the peripheral drive circuit is polycrystallized to form a polycrystal semiconductor transistor. On the other hand, α-Si is used in the pixel area. Further, it is described that when annealing the row-side peripheral circuits and the column-side peripheral circuits, the substrate can be rotated to perform laser annealing processing. And, as the performance of LCD, the signal line (data line)
And 200 scanning lines (gate buses) each, and the operation speed required for the polycrystalline semiconductor layer having sufficient mobility and the circuit was obtained.

Next, the positional relationship of Si islands in the beam annealing method will be described. FIG. 2 is a plan view showing the relationship between the arrangement of the Si islands 1 and the polycrystallized stripes 2 in the column driving circuit when the Si islands are arranged without being sufficiently aligned. In order to anneal all the Si islands 1, the beam annealing scan must be performed with almost no gap, and the number of scans increases. As a result, it takes a long time to beam anneal the TFTs for the column side drive circuit, which leads to a decrease in throughput.

[0015]

When manufacturing the above-mentioned substrate for image display by using the beam annealing method, the TFT of the row driving circuit or the column driving circuit provided in the peripheral circuit different from the pixel region is the pixel driving TFT. At the same time, it was difficult to perform beam annealing.

If the arrangement of the TFTs in this peripheral circuit is not devised, the beam annealing of this portion will take time and the throughput will decrease. The present invention is intended to eliminate such drawbacks.

[0017]

According to the present invention, in an image display substrate in which a pixel driving TFT and a peripheral circuit TFT are formed on the same substrate, the peripheral circuit TFT has a linear shape in the row direction (or (Linear in the column direction if it can be replaced)
The major feature is that they are arranged in.

In the present invention, a drive circuit using a TFT using a polycrystalline semiconductor is further formed on a substrate provided with a pixel drive TFT using a polycrystalline semiconductor. First, the TFT in the row drive circuit or the TFT in the column drive circuit is used for pixel display.
By using the method of arranging the TFTs for the pixel display TFT and the TFT for the pixel display and the TFT for the drive circuit in either the row or the column, the beam annealing can be simultaneously performed.

Next, the TFTs in the remaining column driving circuits are positioned in the row direction, or the TFTs in the row driving circuit are positioned so as to be arranged in parallel in the column direction. As a result, the polycrystalline layer forming process for both the row and column drive circuits can be collectively processed at high speed.

First, a plurality of row electrode lines and a plurality of column electrode lines are arranged in a grid on a substrate, pixel electrodes corresponding to respective intersections and pixel driving TFTs having a polycrystalline semiconductor channel are provided. A substrate for an image display element in which the pixel driving TFTs are linearly arranged at least in the row direction, row signals are supplied from the row electrode lines to the pixel driving TFTs, and column signals are supplied from the column electrode lines to the pixel driving TFTs. In, the plurality of row driving circuits corresponding to the respective row electrode lines and supplying row signals are further provided on the same substrate, and each row driving circuit is provided with at least one row driving TFT, and the row driving TFT is polycrystalline. Provided is a substrate for image display, which has a semiconductor channel, and the row driving TFT is arranged linearly in the row direction with the pixel driving TFT of one row. This is called the first aspect of the present invention.

In addition, a plurality of row electrode lines and a plurality of column electrode lines are arranged in a grid on the substrate, and pixel driving TFTs having pixel electrodes and polycrystalline semiconductor channels are provided corresponding to the respective intersections. A substrate for an image display element in which the pixel driving TFTs are linearly arranged at least in the row direction, row signals are supplied from the row electrode lines to the pixel driving TFTs, and column signals are supplied from the column electrode lines to the pixel driving TFTs. A plurality of column driving circuits, which correspond to the column electrode lines and supply a column signal, are further provided on the same substrate, and each column driving circuit is provided with at least one column driving TFT.
Provided is a substrate for image display, wherein T has a polycrystalline semiconductor channel, and a plurality of column driving TFTs selected from one or more different columns are arranged substantially parallel and linearly in the row direction. To do. This is called the second aspect of the present invention.

In addition, a plurality of row electrode lines and a plurality of column electrode lines are arranged in a grid on the substrate, and pixel driving TFTs having a pixel electrode and a polycrystalline semiconductor channel are provided corresponding to each intersection. A substrate for an image display element in which the pixel driving TFTs are linearly arranged at least in the row direction, row signals are supplied from the row electrode lines to the pixel driving TFTs, and column signals are supplied from the column electrode lines to the pixel driving TFTs. In, the plurality of row driving circuits corresponding to the respective row electrode lines and supplying row signals are further provided on the same substrate, and each row driving circuit is provided with at least one row driving TFT, and the row driving TFT is polycrystalline. A plurality of column driving circuits each having a semiconductor channel, the row driving TFTs being arranged linearly in the row direction and the pixel driving TFTs in one row and corresponding to the column electrode lines, and having the same column driving circuit for supplying a column signal are the same. A plurality of column driving TFTs are further provided on the plate, each column driving circuit is provided with at least one column driving TFT, and each column driving TFT has a polycrystalline semiconductor channel and is selected from different columns. Provides a substrate for image display, which is arranged substantially parallel and linearly in the row direction. This is the third aspect of the present invention.
Is called a mode.

Further, an amorphous semiconductor layer is formed on a substrate, the amorphous semiconductor layer is irradiated with a beam spot, the beam spot is linearly scanned at 10 m / s or more, and a polycrystalline is formed by beam annealing. To form a stripe-shaped polycrystalline semiconductor layer, further form a semiconductor island from the polycrystalline semiconductor layer, and use the semiconductor island to form a pixel driving TFT, a row driving TFT, and a column driving TFT. Provided is a method for manufacturing a substrate for image display, which comprises forming a crystalline semiconductor channel. This is called the fourth aspect of the present invention.

In the substrate for image display according to any one of the first, third, and fourth aspects, a row driving TFT is used as an output buffer for directly driving the row electrode line, and a channel width nCH of n channel is used. _d is 50 to 500 μm, and
The channel width pCH _{d of the} p channel is 1 to 10 of nCH _d .
Provided is a substrate for image display, which is provided with a first CMOS inverter having a double size. This is called the fifth aspect of the present invention.

Specifically, a TFT can be used as a final output buffer that directly drives the row electrode lines and supplies a high current. Channel length is 6 to 7 μm, depending on pixel density and number of pixels
(NCH _d = 50 μm, pCH _d = 50 μm) can supply a current of about 0.5 mA. In this case, 320 × 240 pixels of 3 sizes (inch) can be driven at a refresh rate of 60 Hz.

In addition, (nCH _d = 500 μm, pCH _d
= 5000 μm), a current of approximately 10 mA can be supplied. In this case, 12 sizes and 1280 × 1024 pixels can be driven at a refresh rate of 70 Hz.

In the image display substrate of the fifth mode, nCH _d is 5 to 250 μm and pCH _d is nC before the first CMOS inverter is driven.
A second CMOS inverter having a dimension of 1 to 10 times H _d is preferably provided. A desirable high driving performance can be obtained by a combination of both.

In the second, third, and fourth embodiments of the image display substrate, a column driving TFT is used as an output buffer for directly driving the column electrode line, and nCH is used.
_{1 in} which _d is 20 to 100 μm and pCH _d is nCH _d
A substrate for image display is provided, which is provided with a first CMOS inverter having a size of ˜3 times or with an output buffer having an nCH _d of 20 to 100 μm. This is called the sixth aspect of the present invention.

Further, in the case where a TFT having a long channel width is provided in the image display substrate of the sixth aspect,
The output transistors are divided and arranged to be driven in parallel. 2 to 6, preferably 2 to 6 per column electrode wire
Three column driving TFTs are provided to drive the column electrode lines in parallel. In this way, the TFTs can be arranged in the pitch gap in the column direction (dimension in the column direction of the pixel electrodes).

In the present invention, the pixel driving TFTs and the row driving TFTs are linearly arranged, and further, at least a part of the semiconductor active layer of the column driving TFTs is arranged linearly in the row direction. Preferably, the column side drive circuits are arranged and designed so that all the semiconductor active layers are arranged in a plurality of straight lines.

FIG. 1 is a diagram showing the relationship between Si islands 30 of TFTs in a linearly arranged drive circuit and a strip-shaped polycrystalline layer (called stripe 2) obtained by beam annealing scanning. . The H-shaped portion is the Si island 3. The width of the stripe 2 is about 30 to 100 μm, preferably about 40 to 60 μm. It depends on the power of the laser light source used and the shape stability of the beam spot. There is a tradeoff with the circuit size as the minimum width, but 2
It can be used even at 0 μm. On the other hand, when the polycrystalline semiconductor channel is used perpendicularly to the stripe 2, it is 4 to 10 μm (for example, 4 μm length, 7 μm length) depending on the margin of the contact hole, the SD region, the accuracy of photolithography and the like.

FIG. 7 shows an example of the present invention (image display substrate) having such a plane arrangement of row and column drive circuits.
The pixel region 5 in which the pixel electrodes 5a and the pixel driving TFTs 10A are arranged in a grid pattern, the column driving circuit 7 (column driving output buffer 7a, column driving sample hold circuit 7b, column shift register 7c), row driving circuit 6 (row driving). Output buffer 6a,
A row shift register 6b) is provided. In addition, the row driving TFTs 10B ₁ , 10B _2, ...
0C _X ..., and column drive TFTs 10D _X ..., 10E
_X ..., 10F _X ... are provided. Each of these TFTs
Are arranged substantially linearly in a direction parallel to the row electrode lines.

A beam annealing scanning line for obtaining a layer of polycrystalline Si by laser annealing is shown by reference numeral 4. In this case, the process is repeated in a fixed direction of the substrate at a predetermined pitch P _t . The size of the pitch depends on the size of the pixel, but is preferably at least 50 μm or more.
Beam annealing is effective when P _t > stripe width from the viewpoint of deterioration of characteristics at the joint portion due to overlapping of stripes.

Further, from the viewpoint of throughput, P _t
> Stripe width × 2 is preferable. It is also possible to change the pitch P _t in relation to each circuit. Further, the beam annealing can be performed not only in one direction but also in reciprocal scanning. Further, when the pixel size in the row direction is L _row , P _t × M = L _row (M is an integer).

In the present invention, the row driving TFT means a TFT which is arranged in the row driving circuit and constitutes a circuit. Similarly, the column driving TFT indicates a TFT which is arranged in the column driving circuit and constitutes a circuit. In particular, the size is not limited, and any TFT that functions to drive a column signal and a row signal may be used.

[0036]

In the present invention, since the TFTs are arranged linearly, extremely high productivity and yield can be obtained in the polycrystallization process of α-Si. Further, the image display substrate thus obtained can exhibit stable performance with little variation in the characteristics of the TFT, which is a main circuit element. In addition, since it can be manufactured by a low temperature process, the reliability of the entire substrate for image display thus completed is improved.

[0037]

【Example】

(Embodiment 1) FIG. 3 is a plan view of a TFT substrate 100 for a liquid crystal display in which a pixel region (matrix circuit for pixel display) 5, a row driving circuit 6 and a column driving circuit 7 are formed on a glass substrate. Is. The pixel region 5 is configured by arranging switching transistors such as TFTs having a polycrystalline semiconductor channel, pixel electrodes, row electrode lines (gate bus lines), column electrode lines (source bus lines) in a matrix. In this embodiment, Si is used as the semiconductor.

Further, in FIG. 3, both the row drive circuit 6 and the column drive circuit 7 are divided and arranged on both sides so as to sandwich the pixel region 5. Usually divided by odd and even numbers,
In many cases, they are arranged vertically and horizontally with the pixel region in between.

The TFT is periodically turned on by a row signal (scanning signal) supplied from the row driving circuit 6 through the row electrode line, and a column signal (data signal) supplied from the column driving circuit 7 through the column electrode line is generated. Written to the pixel electrode. The liquid crystal layer sandwiched between the glass substrate and a counter substrate (not shown) is driven by the signal voltage written in the pixel electrode.

Since the row driving circuit 6 handles row signals,
Mainly, a shift register and a row output buffer are provided.
In order to supply a column signal to the column driving circuit 7, a shift register, a data register, a latch, a level shifter, and an output buffer (in the case of a digital circuit), or
Shift register, level shifter, sample and hold,
Various circuits such as an output buffer (the above is the case of an analog circuit) are provided.

As the semiconductor layers (channel, source and drain) of these TFT circuits, polycrystalline Si formed by beam annealing of α-Si formed on a glass substrate using a scanning type beam annealing apparatus. To use. FIG. 4 is a plan view showing a scanning state when beam annealing is performed on the glass substrate shown in FIG. The beam annealing scanning line 4 represented by a solid line is not performed on one solid surface but is performed intermittently.

The beam annealing scanning is performed in the row direction (the direction of arrow L in FIG. 4). Note that beam annealing is a hydrogenation α that is an irradiation target such as a continuous wave argon ion laser.
Any beam may be used as long as it has an energy capable of rapidly polycrystallizing a non-single crystal film such as -Si.
In this embodiment, an argon ion laser is used, the laser output is 10 W, the beam spot diameter is 100 μm (energy is about 1 / e ² of the peak intensity), and the scanning linear velocity is 13 m / s.

When beam annealing is performed over the range of width a shown in FIG. 4, the row drive circuit 6 is configured such that the transistors in the row drive circuit 6 are on the same straight line as the pixel display transistors, as described above. Devise like. As a result, the material (specifically, hydrogenated α-Si, etc.) of the area to be formed as the TFT of the pixel area 5 and that of the TFT of the row drive circuit 6 can be annealed collectively. . The beam anneal is scanned at a pitch that is approximately equal to the pixel row pitch.

Alternatively, the annealing may be performed at a pitch of 1 / M (M is an integer) of the pixel row pitch. Further, although the pitch can be changed on the way, it is advantageous to use a constant pitch in order to maintain the positional accuracy.

More than the number of row electrodes of the pixel, the row drive circuit 6
When beam annealing is performed on the area of, the TFT is added to the extra annealing line (stripe 2) that is increased from the number of rows.
It becomes possible to arrange a circuit using.

The material (actually, hydrogenated .alpha.-Si, etc.) in a region to be formed as the TFT of the column driving circuit 7 over the range of the width b shown in FIG. 4 is beam-annealed together with the pixel display TFT. However, it is not possible to do so, but the regions to be the semiconductor channels of the TFT are arranged in advance so as to form a group of straight lines having a predetermined pitch interval in the column direction and a predetermined width extending in the row direction. .

Therefore, the number of beam annealing scans is the number of the straight lines. The beam anneal scanning pitch is the pitch of the straight line group. Of course, not only the fixed pitch, but the intervals between the two adjacent specific straight lines may be different from the intervals at other places. The arrangement with a constant pitch further contributes to the improvement of overall throughput and stability.

The pitch of the straight line group formed by the predetermined area of the TFT of the column driving circuit does not necessarily have to be constant, and T
It may be appropriately changed according to the size of the FT, the circuit configuration, and the like. In other words, TFTs arranged in a straight line
A group may be formed. Normally, the circuit configuration is performed substantially symmetrically in the row direction or the column direction. Therefore, in the column driving circuit, the circuit configuration is also performed symmetrically on the row direction side.

However, if the pitch in the column driving circuit 7 and the pitch in the row driving circuit 6 (and the pixel region 5) are made substantially the same, the throughput and the obtained stripes 2 in processing the entire substrate are obtained. Is more preferable in terms of the overall positional accuracy of.

Specifically, since the beam annealing scanning is performed by the laser beam, each circuit component is exactly on the straight line (the beam annealing scanning line which forms the stripe) having the width of the beam spot. Must be placed so that it is located. It may be determined in consideration of the relationship between the fluctuation of the scanning locus and the allowable error when the beam spot used is scanned.

In the present embodiment, the scanning pitch of the beam annealing scanning line is set to 120 μm for both the column driving circuit and the pixel region (including the row driving circuit). The obtained polycrystalline semiconductor layer (polysilicon) has a mobility of about 40 to 50 cm ^2.
/ V · s. In addition, the in-plane variation of the substrate in the region to be the column driving circuit, the pixel region, and the region to be the row driving circuit is within about 5%, which is significantly improved as compared with the conventional example.

(Embodiment 2) A row driving circuit is used as a pixel driving TFT.
A TFT substrate having a coplanar polycrystalline SiTFT integrated on the same substrate provided with was formed. The number of pixels is 384 (H) x 288 (V), and the pixel pitch is 192
An RGB stripe array of μm was used. It can be used for a full-color liquid crystal display device.

First, α-Si having a thickness of 100 nm was formed on a glass substrate by using plasma CVD. This α-
Si was beam-annealed by HSBA and polycrystallized as described above. The beam annealing scan was performed in a direction substantially parallel to the row electrode lines. The scanning pitch was 192 μm, which was equal to the pitch of the row electrode lines, that is, the row pitch of the TFTs in the pixel region. The width of α-Si is about 50 by beam annealing.
It became a stripe of μm.

Subsequently, this stripe is patterned by photolithography and etching, and Si which becomes the semiconductor channel (and source and drain) of the TFT is formed.
Formed an island. FIG. 5 shows the positional relationship between the pixel driving TFTs, which are the switching elements of the pixels, and the Si island groups that are the semiconductor channels of the row driving TFTs at this time.

The first Si islands 3 serving as the semiconductor channels of the pixel driving TFTs and the second Si islands 20A ₁ and 20A _{2 serving as} the semiconductor channels of the row driving TFTs (not shown but further provided). Were arranged linearly and included in the stripe 2 polycrystallized by beam annealing.

The number of beam annealing scans for annealing the pixel region and the row driving circuit is the number of rows of the TFT matrix, that is, 288. Further, the Si island for the high-power TFT of the row driving TFT is long in the channel width direction.
Therefore, the channel length direction is perpendicular to the row electrode line (or
Arrange so that the channel width is almost parallel to the row direction,
The stripe 2 was used effectively.

The Si islands of the pixel drive TFT are arranged so that the channel length direction is parallel to the row electrodes. After that, film formation and patterning of the insulating film and the electrode were repeated to fabricate a TFT substrate for image display. S in FIG.
FIG. 6 shows a part of a pixel and row driving circuit manufactured using the i island.
(The scale is almost the same as in FIG. 5).

In FIG. 6, the pixel drive TFT 10A, the pixel electrode 5a, the column electrode line 8, the row electrode line 9, the row drive TFT 1
0B ₁ and 10B ₂ are shown. Row drive TFT 10B ₁ , 10
B ₂ constitutes a CMOS inverter and forms a final output stage buffer (row output buffer) for applying a row signal to the row electrode line 9. The channel width is made large in order to obtain the necessary drive current.

In this embodiment, the n channel width is 50 μm, and the p
A second CMOS inverter having a channel width of 400 μm (adjacent to the row driving TFT 10B ₂ in the figure but not shown), and an n channel width of 250 μm, p
A first CMOS inverter (row driving TFT 10B ₂ and row driving TFT 10B ₁ ) having a channel width of 2000 μm was formed. As a result, a row signal of about 5 mA could be supplied to the row electrode line 9. And vertical frequency 60H
z, a horizontal frequency of 31.5 KHz was sufficient to drive the pixel region 5. The channel length was about 7 μm.

(Embodiment 3) In addition to the row output buffer in the embodiment, the TFT in the row shift register in the row drive circuit
Also, the TFTs were formed by using the polycrystalline Si of the stripe 2 so as to be parallel to the direction of the row electrodes. In this case, a channel length of 5 to 6 μm and a channel width of 7 to 80 μm are formed.

Table 1 shows the main steps of manufacturing the image display substrate and the TFT display element according to the present invention. In addition, the cutting and separating of the substrate in step 11 will be described later in the TFT.
It is used when making multiple jumps of substrates.

[0062]

[Table 1]

Next, according to the conventional technique, as in the embodiment, T
A comparative example in which an FT substrate is manufactured is shown below.

(Comparative Example 1) The same as Example 1 except the TFT arrangement and the annealing process. FIG. 10 shows the arrangement of Si islands that will be the semiconductor channels of the pixel driving TFT and the row driving TFT.
Shown in. Although the Si islands 3 of the pixel driving TFTs are linearly arranged, the Si islands 20a, 2a to be the row driving TFTs
0b is not arranged only on the extension of the straight line. It spans multiple stripes.

Therefore, in order for all the Si islands of the row driving TFT to be polycrystallized, the beam annealing should be scanned with a pitch of 48 μm without any gap. The number of beam annealing scans for annealing the image display region and the row drive circuit is four times the number of rows of the TFT matrix, which is 115
Will be two.

(Embodiment 4) Pixel driving TF in this embodiment
The positional relationship between T and the Si island group serving as the semiconductor channel portion of the row driving TFT is the same as that in FIG. 5 described above. In this embodiment,
By using the Si island, the connection between the row drive circuit side and the pixel region is deviated by one row from the positional relationship at the time of beam annealing, and the row signal from the row drive circuit in the (n) th row is (n ±
1) Wired to the row electrode line of the row.

Example 2 is a pixel drive TFT of a certain row,
While the row driving TFTs of the stage corresponding to the row are arranged on the same straight line, in the present embodiment, the pixel driving TFT of the (n) th row and the row driving TFT of the (n ± 1) th row are arranged. They are arranged on the same straight line. In this case, the number of beam annealing scans required to form a 288-row TFT substrate is 289.

This embodiment is preferable when the layers other than the semiconductor layer are to be arranged line by line due to patterning and layout restrictions.

Example 5 Polycrystalline SiTF on the same substrate
T in which the row drive circuit and the column drive circuit are integrated together in T
An FT substrate was produced.

Similar to the second embodiment, α-Si is polycrystallized by the high speed beam annealing method and patterned to form Si islands. FIG. 8 shows an example of the arrangement of Si islands which will be the semiconductor channel portion of the column driving TFT. The scanning pitch P _t of the beam annealing is 96 μm, and the Si island 30A ₁ of the column driving TFT,
30A ₂ , 30A ₃ , 30A ₄ , 30A ₅ and 30A ₆ were linearly arranged so as to be included in the polycrystallized stripe 2 so as to be placed on a plurality of straight lines parallel to the row electrode lines.

The number of beam annealing scans required to polycrystallize the Si islands of the column driving TFT is 120.
Further, since the Si islands of the column driving TFTs are also long in the channel width direction similarly to those of the row driving TFTs, they are arranged so that the channel length direction is perpendicular to the row electrode lines, and α is formed by beam annealing.
The stripe 2 in which -Si is polycrystallized is used effectively. FIG. 9 shows a part of the column drive circuit manufactured using the Si islands of FIG. A part of the column shift register 7c _(m) of the column drive circuit is shown. In FIG.
Two adjacent columns (i + 1) and (i) are shown.

Column driving TFTs 10F ₁ , 10F ₂ , 10F
₃ , 10F ₄ , 10F ₅ and 10F ₆ were formed. Similar to the row drive circuit, two of them are combined to form a CMOS inverter. Further, the respective CMOS inverters are located on the same stripe 2.
In addition, power supply lines V ₁ and V ₂ of each TFT are shown. The details of the wiring (steps and interlayer connections) are shown in a simplified manner. Next, a comparative example in which a TFT substrate is manufactured using the conventional technique will be shown below.

(Comparative Example 2) Si island groups (30a, 30b, 30C, 30d, 30) which will be the channel portions of the column driving TFTs.
The arrangement of e, 30f) is shown in FIG. The Si islands are not arranged linearly, but are arranged mainly for the ease of wiring. In order to polycrystallize these Si islands, beam annealing is performed with a pitch of 48 μm without any gap. Column drive TF
The number of beam annealing scans required to polycrystallize T Si islands is 200.

In the column driving circuit manufactured using the Si islands of FIG. 11, a characteristic difference is likely to occur between the column driving TFTs, and display characteristics may be uneven between columns.

(Embodiment 6) As in Embodiment 5, a TFT substrate in which a row drive circuit and a column drive circuit are both integrated with a polycrystalline Si TFT on the same substrate was produced.

FIG. 12 shows an example of the column output buffer of the column driving circuit in this embodiment. Si islands 30D _{1 (i + 1)} , 30D _{2 (i + 1)} , 30D which are semiconductor channels of the column driving TFT
The layout of _{3 (i + 1)} is also shown. Its size is about 4
It is 0 μm × 28 μm. The scanning pitch P _{t for} beam annealing is 192 μm for the row and pixel regions, as in the fifth embodiment.
The row area was 96 μm. Further, the Si islands of the column driving TFTs were arranged in a plurality of straight lines parallel to the row electrode lines so as to be included in the stripe 2.

The number of beam annealing scans required for the column drive circuit is 120. Further, in the present embodiment, the column drive TF
In order to obtain a drive current of T, the channel length direction is arranged to be perpendicular to the row electrode line, and one column electrode line (i
Three TFTs 10D _{1 (i)} , 10D _{2 (i)} , 1 for one column)
0D _{3 (i)} is provided in parallel to drive. In this case, the channel width is 120 μm in total.
In this case, even if one fails, it can be divided and driven by the remaining normal TFTs. In addition, it can be preferably applied even when the pixel density becomes higher definition.

Example 7 A plurality of image display substrates were obtained from the same large substrate. That is, a plurality of sets of row driving circuits and column driving circuits were provided on the substrate by using polycrystalline TFTs for integration.

An example of this embodiment is shown in FIG. A plurality of TFT substrates 101 and the like can be simultaneously obtained from one large substrate 50 (this is called multi-annealing). The production efficiency is much higher than that in the case of beam annealing only one TFT substrate. In this embodiment, the size of the large substrate 50 is 400 mm in length (L ₀ ) and 400 mm in width (W).
₀ ) It was set to 300 mm.

The size of one image display substrate 101 is L
₁ = W ₁ = 100 mm. The diagonal dimension is 3.1 size (inch), the pixel area is 640 × 480 pixel configuration, and the vertical and horizontal dimensions are approximately 64 mm × 48 mm. Further, the scanning pitch P _{t for} beam annealing is 100 μm.
m. The size of each image display substrate is the same, and eight substrates are obtained from one large substrate.

The time required for the beam annealing at this time includes the overhead time in the middle (the portion between the substrates is skipped without beam annealing) when the linear velocity is about 13 m / s. It took about 2 minutes.

When the panels of a plurality of display devices are arranged in the beam annealing direction, the superiority of the multi-annealing method is further demonstrated. Either the row direction or the column direction is selected so that the total number of beam anneals is reduced. Usually, it is arranged so that beam annealing is performed in the row direction. Since the scanning speed is high (10 m / s or more), the time required for the annealing process does not change much even if the length of the annealing line becomes long. Table 2 shows the glass substrate (4
An example of combination in the case of performing multi-annealing with 50 mm × 370 mm) is shown. However, the glass substrate can be made larger. For example, 1280 (× 3) × 10
It is also possible to perform multi-annealing of a high definition / large diameter substrate such as 24.

Further, Table 3 collectively shows the constitutions of Examples 1 to 7 of the present invention. In all the examples, coplanar TFTs are used.

[0084]

[Table 2]

[0085]

[Table 3]

Example 8 A TFT display element 200 was obtained by further providing an opposing substrate on each of the above-mentioned image display substrates. FIG. 14 schematically shows the cross section. Glass substrate 1
1, counter glass substrate 12, peripheral seal 13, liquid crystal layer 1
4, the row drive circuit 7, the pixel region 5, and the counter electrode 5b.

In this TFT display element, the peripheral drive circuit is also formed on the same substrate 11, and is composed of a TFT having a polycrystalline semiconductor channel. Can be produced at low cost,
A stable image display with little variation was obtained. Also,
Since the peripheral circuits have already been formed as one unit, there is no need for assembling work as in the past. Therefore, defective connection between the peripheral driver circuit and the pixel region can be reduced.

[0088]

According to the present invention, a TFT for a row drive circuit
Are arranged in a linear group, and TFTs for the column side drive circuit
Are arranged in a straight line group, the number of scanning times for beam annealing of the column side drive circuit portion is only the number of those straight lines. Compared with the case where TFTs are arranged by the conventional method, the number of beam annealing scans is significantly reduced.

As a result, a TFT incorporating a drive circuit
Throughput in substrate manufacturing is dramatically improved.
Comparing the conventional example with the present invention, for example, the number of scans required to beam anneal the same number of Si islands is 7 to 3
Can be reduced to books. The smaller the number of straight lines in this straight line group, the smaller the number of scans and the higher the throughput.

Further, since the Si islands are designed to be included in the beam annealing scanning line from the beginning, the seams of the beam annealing scanning line do not reach the Si islands as shown in FIG. Variation is suppressed.

Therefore, when the TFTs of the same size are used for comparison, the driving circuit operates stably at a high speed, the writing to the pixel becomes faster, and the leakage is reduced, so that the TF is reduced.
The characteristics of T are improved. That is, the signal writing speed to the liquid crystal layer becomes stable. Then, a better image quality than the conventional one can be obtained.

Furthermore, when a plurality of substrates for image display are formed on a large-sized substrate, the effect of the present invention is more exhibited.

For example, 8 to 16 TFs can be obtained with one large substrate.
When forming a T substrate, the process required for its polycrystallization is only within a few minutes. The position of the polycrystalline Si layer (stripe) formed by this method is determined in advance, and the process alignment property is good. Therefore, the yield is further improved.

Further, since the high speed beam annealing method can be performed in a room temperature atmosphere, it is more advantageous when manufacturing a large substrate. Since a large temperature history is not received, yield and product characteristic variations can be reduced.

Further, since an inexpensive glass substrate having a low softening point can be used, low cost production can be performed.

Further, since the pattern layout has regularity, it is easy to carry out a test and a repair in the middle of manufacturing.

Further, the present invention can be applied in various ways within a range that does not impair the effect.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention (column-side Si arranged linearly).
FIG.

FIG. 2 is a plan view showing a conventional example provided with non-linearly arranged column-side Si islands.

FIG. 3 is a plan view of a (TFT array) substrate for a liquid crystal display device according to the present invention.

FIG. 4 is a plan view showing a state where the beam annealing is performed linearly over the entire surface of the glass substrate in the manufacturing method of the present invention.

FIG. 5 shows an embodiment of the present invention (linearly arranged row-side Si
FIG.

FIG. 6 is a plan view showing an embodiment of the present invention (a part of a row driving circuit arranged linearly and a pixel region).

FIG. 7 is a plan view of a TFT substrate of the present invention including a row driving circuit, a column driving circuit and a pixel area.

FIG. 8 is a plan view showing an example of column-side Si islands linearly arranged.

FIG. 9 is a plan view showing an embodiment of (a part of) a column driving circuit linearly arranged.

FIG. 10 is a plan view showing a conventional example including row-side Si islands arranged non-linearly.

FIG. 11 is a plan view showing a conventional example including column-side Si islands that are non-linearly arranged.

FIG. 12 is a plan view showing an example of a column driving circuit (output buffer) linearly arranged.

FIG. 13 is a plan view showing a large-sized substrate of the present invention in which a plurality of TFT substrates are arranged.

FIG. 14 is a schematic cross-sectional view of a TFT display element.

[Explanation of symbols]

 1, 3, 20, 30: Si Island 2: Stripe 4: Beam Annealing Scan Line 5: Pixel Area 6: Row Drive Circuit 7: Column Drive Circuit 8: Column Electrode Line 9: Row Electrode Line 10A, 10B, 10C, 10D : TFT

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (6)

[Claims] 1. A substrate is provided with a plurality of row electrode lines and a plurality of column electrode lines arranged in a grid pattern, pixel electrodes corresponding to respective intersections, and pixel driving TFTs having polycrystalline semiconductor channels, A substrate for an image display element in which the pixel driving TFTs are linearly arranged at least in the row direction, row signals are supplied from the row electrode lines to the pixel driving TFTs, and column signals are supplied from the column electrode lines to the pixel driving TFTs. A plurality of row driving circuits corresponding to the respective row electrode lines and supplying row signals are further provided on the same substrate, and each row driving circuit is provided with at least one row driving TFT, and the row driving TFTs are polycrystalline. A plurality of column driving circuits having a semiconductor channel, the row driving TFTs being arranged linearly in the row direction and the pixel driving TFTs in one row and corresponding to the column electrode lines, and having a plurality of column driving circuits for supplying column signals are the same. A plurality of column driving TFTs further provided on the plate, each column driving circuit having at least one column driving TFT, each column driving TFT having a polycrystalline semiconductor channel, and one column driving TFT selected from different columns. Is a substrate for image display, which is arranged substantially parallel and linearly in the row direction. 2. The image display substrate according to claim 1, wherein at least one row driving TF of row driving circuits of each row.
T is arranged linearly with the pixel driving TFT of any row, and is selected from one or more of all the columns or from each of the divided columns formed by dividing all the columns. A substrate for image display, wherein a plurality of column driving TFTs are arranged substantially parallel and linearly in the row direction. 3. The substrate for image display according to claim 1, wherein a polycrystalline semiconductor channel of the pixel driving TFT, a polycrystalline semiconductor channel of the row driving TFT, and a polycrystalline semiconductor channel of the column driving TFT. The substrate for image display, wherein the amorphous semiconductor layer is formed by using a polycrystalline semiconductor layer polycrystallized by beam annealing. 4. A liquid crystal layer is sandwiched between an image display substrate according to any one of claims 1 to 3 and a counter substrate further provided with a counter electrode. T
FT display element. 5. An amorphous semiconductor layer is formed on a substrate, the amorphous semiconductor layer is irradiated with a beam spot, the beam spot is linearly scanned at 10 m / s or more, and the polycrystalline is formed by beam annealing. To form a stripe-shaped polycrystalline semiconductor layer, form a semiconductor island from the polycrystalline semiconductor layer, and use the semiconductor island to form a polycrystalline semiconductor of each of a pixel driving TFT, a row driving TFT, and a column driving TFT. A method of manufacturing a substrate for image display, which comprises forming a channel. 6. The method for manufacturing an image display substrate according to claim 5, wherein the stripes obtained by one beam annealing are respectively pixel drive TFTs, row drive TFTs and column drive TFTs.
A method for manufacturing a substrate for image display, which is used to form a polycrystalline semiconductor channel of a plurality of substrates for image display, which comprises: