JPH0789280A - Ic module - Google Patents

Ic module

Info

Publication number
JPH0789280A
JPH0789280A JP5264128A JP26412893A JPH0789280A JP H0789280 A JPH0789280 A JP H0789280A JP 5264128 A JP5264128 A JP 5264128A JP 26412893 A JP26412893 A JP 26412893A JP H0789280 A JPH0789280 A JP H0789280A
Authority
JP
Japan
Prior art keywords
chip
module
bumps
bump
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5264128A
Other languages
Japanese (ja)
Inventor
Shuichi Matsumura
秀一 松村
Masashi Takahashi
正志 高橋
Fumihiro Takayama
文博 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP5264128A priority Critical patent/JPH0789280A/en
Publication of JPH0789280A publication Critical patent/JPH0789280A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item

Abstract

PURPOSE:To provide a bump connection type IC module having high bonding strength of an IC chip. CONSTITUTION:When an IC chip 13 is placed and adhered to a printed board 12, a dummy bump 19 isolated from a normal bump 18 is arranged. The bump 19 remarkably enhances a bonding strength of the chip 13 to the board 12 at the time of resin sealing. In order to enhance the bonding strength of the bump 19 to the board 12, a dummy wiring pattern 20 is also arranged.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＩＣカードに搭載される
ＩＣモジュール、特にワイヤレスボンディング方式の一
種であるバンプ接続方式を採用したＩＣモジュールの改
良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an IC module mounted on an IC card, and more particularly to an IC module adopting a bump connection method which is one of wireless bonding methods.

【０００２】[0002]

【従来の技術】従来のバンプ接続方式のＩＣモジュール
は図５〜図７に示すように構成されていた。このもの
は、プリント基板（モジュール基材）５１上にＩＣチッ
プ５２をバンプ５３により接続、搭載している。ＩＣチ
ップ５２は樹脂５４により被覆、封止（モールド）され
ている。バンプ５３はプリント基板５１表面の配線パタ
ーン５５と、ＩＣチップ５２の電極端子とを接続すると
ともに、ＩＣチップ５２をプリント基板５１に固着して
いる。５６はプリント基板５１の裏面に配設された配線
パターンであって、スルーホール５７を介して表面の配
線パターン５５に接続されている。なお、この裏面の配
線パターン５６は外部出力端子を有しており、ＩＣカー
ドへの装着時はこの外部出力端子を介してＩＣチップ５
２の内蔵ＬＳＩは動作する。2. Description of the Related Art A conventional bump connection type IC module is constructed as shown in FIGS. In this device, an IC chip 52 is connected and mounted by bumps 53 on a printed circuit board (module base material) 51. The IC chip 52 is covered and sealed (molded) with a resin 54. The bump 53 connects the wiring pattern 55 on the surface of the printed board 51 and the electrode terminal of the IC chip 52, and also fixes the IC chip 52 to the printed board 51. A wiring pattern 56 is provided on the back surface of the printed circuit board 51, and is connected to the wiring pattern 55 on the front surface through the through holes 57. The wiring pattern 56 on the back surface has an external output terminal, and when mounted on an IC card, the IC chip 5 is connected via the external output terminal.
2 built-in LSI operates.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のＩＣモジュールにあっては、ＩＣチップを樹
脂で封止する場合、プリント基板にＩＣチップをバンプ
により接続した後、それらの隙間にノズルより一定圧力
で樹脂溶湯を注入する。この場合、従来のＩＣモジュー
ルではバンプは電気的に必要な部分にのみ設けられてい
たため、バンプによる接着強度が低く、ＩＣチップが剥
がれてしまうという課題があった。However, in such a conventional IC module, when the IC chip is sealed with resin, the IC chip is connected to the printed board by bumps, and then the nozzles are provided in the gaps between them. The molten resin is injected at a more constant pressure. In this case, in the conventional IC module, since the bumps are provided only in the electrically necessary portions, there is a problem that the adhesive strength of the bumps is low and the IC chip is peeled off.

【０００４】[0004]

【発明の目的】そこで、本発明は、樹脂封入時にチップ
剥がれの生じることがないＩＣモジュールを提供するこ
とを、その目的としている。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an IC module in which chip separation does not occur during resin encapsulation.

【０００５】[0005]

【課題を解決するための手段】請求項１に記載の発明
は、平板状でその表面に配線パターンが配設されたモジ
ュール基材と、このモジュール基材上に配置されたＩＣ
チップと、このＩＣチップを被覆する樹脂部とを備え、
上記配線パターンとＩＣチップの端子とをバンプにより
接続したＩＣモジュールにおいて、上記ＩＣチップの使
用端子以外の部分と、上記モジュール基材にあって配線
パターン以外の部分とを接続するダミーバンプを設けた
ＩＣモジュールである。According to a first aspect of the present invention, there is provided a module base material having a flat plate shape on which a wiring pattern is arranged, and an IC arranged on the module base material.
A chip and a resin portion covering the IC chip,
In an IC module in which the wiring pattern and terminals of an IC chip are connected by bumps, an IC is provided with dummy bumps that connect parts other than the used terminals of the IC chip and parts of the module base material other than the wiring pattern. It is a module.

【０００６】[0006]

【作用】請求項１に記載のＩＣモジュールにあっては、
ダミーバンプによりＩＣチップとモジュール基材との間
の接着強度が増している。このため、樹脂封入時にＩＣ
チップの剥がれ、バンプによる接続不良が生じることは
ない。According to the IC module of claim 1,
The dummy bumps increase the adhesive strength between the IC chip and the module base material. Therefore, when resin is filled, IC
There is no peeling of the chip or defective connection due to bumps.

【０００７】[0007]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図１は本発明に係るＩＣカード用のＩＣモジュー
ルの一実施例を示すその断面図である。図２は同じくＩ
Ｃモジュールのモジュール基材の表面図である。図３は
そのＩＣチップの底面図（裏面図）である。図４はその
ＩＣモジュールのモジュール基材の裏面図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of an IC module for an IC card according to the present invention. Figure 2 is also I
It is a surface view of the module base material of C module. FIG. 3 is a bottom view (back side view) of the IC chip. FIG. 4 is a back view of the module base material of the IC module.

【０００８】これらの図に示すように、ＩＣモジュール
１１は、平板状のプリント基板（モジュール基材）１２
と、ＬＳＩ等内蔵のＩＣチップ１３と、ＩＣチップ１３
を封止する樹脂モールド部１４と、を有している。As shown in these figures, the IC module 11 includes a flat printed board (module base material) 12
And an IC chip 13 with a built-in LSI, etc., and an IC chip 13
And a resin mold portion 14 that seals the.

【０００９】プリント基板１２のＩＣチップ１３装着側
表面には配線パターン１５が、その裏面、すなわちＩＣ
カードへの実装時はＩＣカード表面となる側には配線パ
ターンおよび外部出力端子１６が、それぞれ印刷等によ
り配設されている。そして、これらの表裏面の配線パタ
ーン１５，１６同士は、プリント基板１２に穿設された
スルーホール１７を介して電気的に接続されている。こ
の外部出力端子を介して、外部機器（ＩＣカードリーダ
ライタ等）との間でデータの授受が行われることとな
る。A wiring pattern 15 is provided on the front surface of the printed circuit board 12 on which the IC chip 13 is mounted, that is, the back surface thereof,
The wiring pattern and the external output terminal 16 are arranged by printing or the like on the side which becomes the surface of the IC card when mounted on the card. The wiring patterns 15 and 16 on the front and back surfaces are electrically connected to each other through through holes 17 formed in the printed board 12. Data is exchanged with an external device (such as an IC card reader / writer) via the external output terminal.

【００１０】プリント基板１２は矩形板状のプラスチッ
ク製であって、その表面の略中央部には、ＩＣチップ１
３が固着、搭載されている。ＩＣチップ１３は複数のバ
ンプ１８およびダミーバンプ１９によってプリント基板
１２に接着されている。バンプ１８はＩＣチップ１３の
裏面（プリント基板１２と対向する面）の電極端子（Ｇ
ＮＤ，Ｖｃｃ，Ｉ／Ｏ，ＣＬＫ，ＲＳＴ）をプリント基
板１２の配線パターン１５に接続するものでもある。一
方、ダミーバンプ１９は、図３に示すように、ＩＣチッ
プ１３にあって上記端子として使用しない端子（Ｖｐ
ｐ，ＲＦＵ等）部分に配設されて、該未使用端子（より
具体的にはそのパッド）とダミーの配線パターン２０と
を接着している。すなわち、これらのダミーバンプ１９
は単にＩＣチップ１３をプリント基板１２に強固に接着
するための目的により設けられたものである。なお、こ
の未使用端子部分とは別の電気的に影響を与えない部分
にダミーバンプ専用のパッドを設けてもよい。さらに、
ダミーの配線パターン２０がダミーバンプ１９に対応し
て設けられ、ダミーバンプ１９との間の接着強度を高め
ている。ダミーの配線パターン２０は上記配線パターン
１５と同時に印刷等によって配設されるが、電気的には
これらの正規の配線パターン１５に対して完全に絶縁、
隔離された状態にあるものである。The printed board 12 is made of plastic in the shape of a rectangular plate, and the IC chip 1 is provided at the substantially central portion of the surface thereof.
3 is fixed and mounted. The IC chip 13 is bonded to the printed board 12 by a plurality of bumps 18 and dummy bumps 19. The bumps 18 are electrode terminals (G) on the back surface of the IC chip 13 (the surface facing the printed circuit board 12).
ND, Vcc, I / O, CLK, RST) is also connected to the wiring pattern 15 of the printed board 12. On the other hand, the dummy bump 19 is, as shown in FIG. 3, a terminal (Vp
p, RFU, etc.), and the unused terminals (more specifically, the pads) and the dummy wiring patterns 20 are bonded to each other. That is, these dummy bumps 19
Is provided merely for the purpose of firmly adhering the IC chip 13 to the printed board 12. It should be noted that a pad dedicated to the dummy bump may be provided in a portion other than the unused terminal portion, which has no electrical influence. further,
A dummy wiring pattern 20 is provided corresponding to the dummy bump 19 to increase the adhesive strength between the dummy wiring pattern 20 and the dummy bump 19. The dummy wiring pattern 20 is arranged at the same time as the wiring pattern 15 by printing or the like, but is electrically completely insulated from these regular wiring patterns 15.
It is in an isolated state.

【００１１】そして、このプリント基板１２上でＩＣチ
ップ１３およびバンプ１８，１９はモールド用樹脂１
４、例えばＢＴレジン等にて封止されている。なお、上
記ダミーバンプ１９とバンプ１８とは面内で点対象の位
置（８個の端子位置）に配設されている（図３）。ＩＣ
チップ１３を平面に安定保持して接着するとともに、如
何なる方位からの外力によっても均等に作用するもので
ある。これらのバンプ１８，１９はいずれも導体金属、
例えば金、銀等で所定の方法により同時に配設されるも
のとする。例えばＩＣチップ１３の各パッド面に金（Ａ
ｕ）バンプ（ワイヤボールバンプ）を配置する。一方、
プリント基板１２の所定位置には銀ペーストを塗布し、
この銀ペーストに上記金バンプを融着する。したがっ
て、ダミーの配線パターン２０およびダミーバンプ１９
の配設に際して特別な工程が増加することはない。The IC chip 13 and the bumps 18 and 19 on the printed circuit board 12 are molded resin 1.
4, sealed with, for example, BT resin. The dummy bumps 19 and 18 are arranged at point-symmetrical positions (8 terminal positions) in the plane (FIG. 3). IC
The chip 13 is stably held and adhered to a flat surface, and acts evenly by an external force from any direction. These bumps 18 and 19 are both conductive metal,
For example, it is assumed that gold, silver, etc. are simultaneously arranged by a predetermined method. For example, gold (A
u) Arrange bumps (wire ball bumps). on the other hand,
Apply silver paste to the specified position on the printed circuit board 12,
The gold bumps are fused to this silver paste. Therefore, the dummy wiring pattern 20 and the dummy bump 19
There is no increase in the number of special steps in disposing the.

【００１２】以上のように３つのダミーバンプ１９を、
ＩＣチップ１３のデバイス等とは電気的に絶縁された部
分であってこれに電気的な影響を与えない部分に配設し
たため、ＩＣチップ１３のプリント基板１２への接着強
度が高められる。よって、樹脂をノズル等によりこれら
の間に所定圧力で流し込む際にも、ＩＣチップ１３が剥
がれたりすることはない。As described above, the three dummy bumps 19 are
Since the device of the IC chip 13 and the like are electrically insulated from each other and disposed in a portion that does not electrically affect the device, the bonding strength of the IC chip 13 to the printed circuit board 12 is increased. Therefore, the IC chip 13 is not peeled off even when the resin is poured between them by a predetermined pressure with a predetermined pressure.

【００１３】[0013]

【発明の効果】本発明によれば、モジュール基材からＩ
Ｃチップが剥離することがない。バンプによる接続不良
の発生は完全に防止される。よって、製造歩留まりが高
められ、製造コストの低減が可能となる。According to the present invention, I
The C chip does not peel off. Occurrence of connection failure due to bumps is completely prevented. Therefore, the manufacturing yield is increased and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係るＩＣモジュールを示す
断面図である。FIG. 1 is a sectional view showing an IC module according to an embodiment of the present invention.

【図２】本発明の一実施例に係るＩＣモジュールを示す
表面図である。FIG. 2 is a front view showing an IC module according to an embodiment of the present invention.

【図３】本発明の一実施例に係るＩＣモジュールのバン
プ位置を示すＩＣチップの底面図である。FIG. 3 is a bottom view of an IC chip showing bump positions of an IC module according to an embodiment of the present invention.

【図４】本発明の一実施例に係るＩＣモジュールを示す
裏面図である。FIG. 4 is a back view showing an IC module according to an embodiment of the present invention.

【図５】従来のＩＣモジュールを示す断面図である。FIG. 5 is a cross-sectional view showing a conventional IC module.

【図６】従来のＩＣモジュールを示す表面図である。FIG. 6 is a front view showing a conventional IC module.

【図７】従来のＩＣモジュールのバンプ位置を示すＩＣ
チップの底面図である。FIG. 7 is an IC showing bump positions of a conventional IC module.
It is a bottom view of a chip.

【符号の説明】[Explanation of symbols]

１１ ＩＣモジュール、 １２ プリント基板（モジュール基材）、 １３ ＩＣチップ、 １４ 樹脂モールド部（封止樹脂部）、 １５ 配線パターン、 １８ バンプ、 １９ ダミーバンプ 11 IC modules, 12 printed circuit boards (module base materials), 13 IC chips, 14 resin mold parts (sealing resin parts), 15 wiring patterns, 18 bumps, 19 dummy bumps

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 平板状でその表面に配線パターンが配設
されたモジュール基材と、このモジュール基材上に配置
されたＩＣチップと、このＩＣチップを被覆する樹脂部
とを備え、上記配線パターンとＩＣチップの端子とをバ
ンプにより接続したＩＣモジュールにおいて、 上記ＩＣチップの使用端子以外の部分と、上記モジュー
ル基材にあって配線パターン以外の部分とを接続するダ
ミーバンプを設けたことを特徴とするＩＣモジュール。1. A wiring board, comprising: a module base material having a flat plate-shaped surface on which a wiring pattern is arranged; an IC chip arranged on the module base material; and a resin portion covering the IC chip. In an IC module in which a pattern and terminals of an IC chip are connected by bumps, dummy bumps are provided to connect parts other than the used terminals of the IC chip and parts other than the wiring pattern on the module base material. IC module.
JP5264128A 1993-09-28 1993-09-28 Ic module Pending JPH0789280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5264128A JPH0789280A (en) 1993-09-28 1993-09-28 Ic module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5264128A JPH0789280A (en) 1993-09-28 1993-09-28 Ic module

Publications (1)

Publication Number Publication Date
JPH0789280A true JPH0789280A (en) 1995-04-04

Family

ID=17398862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5264128A Pending JPH0789280A (en) 1993-09-28 1993-09-28 Ic module

Country Status (1)

Country Link
JP (1) JPH0789280A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10193848A (en) * 1996-12-27 1998-07-28 Rohm Co Ltd Circuit chip-mounted card and circuit chip module
JP2001175829A (en) * 1999-10-08 2001-06-29 Dainippon Printing Co Ltd Noncontact data carrier and ic chip
JP2006101550A (en) * 2005-12-05 2006-04-13 Fujitsu Media Device Kk Surface acoustic wave device, communication apparatus using the same, and antenna duplexer
JP2006252050A (en) * 2005-03-09 2006-09-21 Matsushita Electric Ind Co Ltd Ic card module
JP2007213463A (en) * 2006-02-13 2007-08-23 Dainippon Printing Co Ltd Noncontact data carrier and wiring board for noncontact data carrier
JP2008140400A (en) * 2007-12-14 2008-06-19 Renesas Technology Corp Electronic tag and its manufacturing method
US8174093B2 (en) 1996-12-02 2012-05-08 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174093B2 (en) 1996-12-02 2012-05-08 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US8283755B2 (en) 1996-12-02 2012-10-09 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JPH10193848A (en) * 1996-12-27 1998-07-28 Rohm Co Ltd Circuit chip-mounted card and circuit chip module
JP2001175829A (en) * 1999-10-08 2001-06-29 Dainippon Printing Co Ltd Noncontact data carrier and ic chip
JP2006252050A (en) * 2005-03-09 2006-09-21 Matsushita Electric Ind Co Ltd Ic card module
JP2006101550A (en) * 2005-12-05 2006-04-13 Fujitsu Media Device Kk Surface acoustic wave device, communication apparatus using the same, and antenna duplexer
JP2007213463A (en) * 2006-02-13 2007-08-23 Dainippon Printing Co Ltd Noncontact data carrier and wiring board for noncontact data carrier
JP2008140400A (en) * 2007-12-14 2008-06-19 Renesas Technology Corp Electronic tag and its manufacturing method

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