JPH0787436B2 - Time slot switching control method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplex data communication system such as ISDN, in which a time slot of each circuit is provided when a communication control device has a dual circuit in order to improve system reliability. Regarding usage, the present invention relates to a time slot switching control method for performing exclusive control at high speed.

[0002]

2. Description of the Related Art With the recent increase in computer networks, high-speed and large-volume data transfer and high reliability of data transfer are required. Therefore, ISDN
It is conceivable to realize high-speed and large-volume data transfer by using a time-division multiplex data communication system, etc., and to provide high reliability of the system by multiplexing communication control devices.

When multiplexing communication control devices, it is important to maintain consistency of data and communication control because a plurality of communication control units must handle the same data. FIG. 15 shows the configuration of a conventional duplex communication control device. In FIG. 15, the communication control device is connected to a computer via a redundant bus.

The duplex bus consists of two buses # 0B and # 1B. The communication control device has a dual circuit and includes a # 0 system circuit connected to the bus # 0B and a bus # 1B.
# 1 system circuit connected to. Each of the circuits of the # 0 system and the # 1 system has a microprocessor 1, a time slot control unit 2, and N line control units 3.

In the circuit of each system, the microprocessor 1 executes a communication control program, sends N line (channel) data to a set of N line control units 3 and sends a time slot control unit 2 a line. A time-slot control is performed by sending a line allocation command instructing the allocation of the time slot to the time slot. The line control unit 3 controls the procedure of the ISDN line and outputs the data of each line to the time slot control unit 2.

The time slot control unit 2 inputs the channel data from each line control unit 3 and associates the time slot with the line address in accordance with the line allocation instruction from the microprocessor 1.

FIG. 16 shows the structure of channel data. The minimum unit of data transmission / reception is a time slot (TS). Each time slot contains 8 bits of data. One frame is formed by n time slots. With this data structure, it is possible to physically transmit data for up to n lines (channels) through one transmission path.

To send and receive data, for example, TS1
Are assigned to time slots and channel 2 is assigned to TS2, and channels are assigned to time slots. When the channel data is transmitted, it is placed on the transmission line at the corresponding time slot, and when it is received, it is extracted from the transmission line at the corresponding time slot.

If necessary, one channel can be assigned to a plurality of time slots for transmission / reception to increase the transmission rate. For example, if two time slots are used for one channel, transmission / reception can be performed at twice the transmission rate as in one case.

Returning to FIG. 15, the time slot control units 2 of the # 0 system and the # 1 system are both connected to the frame control unit 4. The frame control unit 4 adds a frame synchronization signal to the frame signal from the time slot control unit 2 and outputs it to the ISDN network.

In the previous communication control device, only one microprocessor 1 was provided. Therefore, the switching of the time slot is performed by this one microprocessor 1.
Since the communication control program above has performed, if the microprocessor 1 fails, or if the communication control program on the microprocessor 1 fails, the reliability of this communication control device is impaired. It was a thing.

Therefore, the system reliability is improved by providing two microprocessors 1 so as to continue operating even if a failure occurs in the microprocessor 1 or the communication control program on the microprocessor 1. Is.

[0013]

In the duplicated communication control device for improving the reliability of the system, it is conceivable that each microprocessor 1 performs exclusive control of time slots by a communication control program.

That is, two microprocessors 1
Always monitors which time slot is currently being used and controls the allocation and switching of time slots based on this monitoring information so that the same time slot is not used by two microprocessors 1 at the same time. There must be.

In the time slot control method using such a communication control program, a failure occurs due to an error of software (communication control program), for example, a bug,
Malfunction of hardware, in this case, timeslots may be doubly assigned, causing a problem of impairing reliability.

It is an object of the present invention to provide a communication control device for high-speed and highly reliable digital communication, in which the communication control program on the microprocessor 1 does not exclusively control the time slots.

[0017]

A time slot switching control system according to the present invention, in a communication control device of a time division multiplex communication system, comprises two processors for executing a communication control program, and two processors for executing the communication control program. Inputs data from each of the two sets of line control units and two sets of line control units that input line data and control the line, respectively, and associate the time slot with the line address. Two time slot control units that store the state of association, means for sending a line assignment command from each of the two processors to the corresponding time slot control unit, instructing to assign a line to a time slot, From each of the two time slot control units, the corresponding processor is allocated to the time slot of the line. Means for sending a notification signal notifying that the time slot has been canceled, and means for sending an exclusive control signal for prohibiting the allocation of the time slot of the line from one of the two time slot control units to the other. Composed.

Further, the time slot switching control system includes means for giving priority to the two time slot control units, and the line allocation command instructs the two time slot control units to connect to the same time slot at the same time. When an address is specified, the higher priority time slot control unit assigns a line to a time slot, and the other time slot control unit controls the processor to notify each line address that could not be assigned. To be configured.

[0019]

With the above configuration, each time slot control section
If the timeslot indicated by the line allocation instruction from the corresponding processor is not currently in use,
The use of the time slot is prohibited by assigning a line to the time slot and sending an exclusive control signal to the other time slot control unit.

The time slot control unit which has received the exclusive control signal cancels the correspondence between the time slot and the line address if the time slot is used and notifies the processor of the canceled line address. .

When the time slot designated by the line allocation instruction from the corresponding processor is currently in use, each time slot control unit switches the use of the time slot to the newly designated line and allocates the time slot. The address of the released line is notified to the corresponding processor. Also, the two time slot control units are
Can be prioritized.

When the line allocation command instructs the two time slot control units to simultaneously specify the line address in the same time slot, the time slot control unit with the higher priority allocates the line to the time slot and the other time slot is controlled. The slot controller controls the processors so as to notify the line addresses that could not be assigned.

As described above, the exclusive control of the time slot is also checked by the hardware. Therefore, even if a failure occurs in the software and the timeslot is duplicated, this failure can be detected. it can. At this time, the hardware will operate normally even if an illegal allocation is received.

[0024]

EXAMPLES Examples of the present invention will be described in detail below. FIG. 1 shows the configuration of a time slot switching control system according to the present invention. In FIG. 1, the same reference numerals as those in FIG. 8 indicate the same functions.

In FIG. 1, the communication control device has # 0 system and # 1 system circuits connected to the redundant buses # 0B and # 1B, respectively. Each circuit of the # 0 system and the # 1 system includes a microprocessor 10 that executes a communication control program, a time slot control unit 12 that associates a time slot with a line address, and a set of line control that controls the ISDN line procedure. It has a part 13.

The microprocessor 10 has a data line 11
Is connected to the N line control units 13 by the control line 1
5 and 17 connect to the time slot controller 2. A line allocation command is sent from the microprocessor 10 to the time slot control unit 12 through the control line 15.

A line address notification interrupt signal is sent from the time slot controller 12 to the microprocessor 10 through the control line 17.

As for the line address notification interrupt signal, the time slot control unit 12 allocates a line to a time slot according to a line allocation command of the microprocessor 10 and an exclusive control signal from the time slot control unit 12 of another system, which will be described later. It is a signal for notifying the microprocessor 10 of the line address when the line is released or the line is changed during use.

The time slot control units 12 of both # 0 and # 1 are connected to each other by control lines 16A and 16B. From the # 0 system time slot control circuit 12 through the control line 16A, and through the control line 16B,
An exclusive control signal is sent from the 1-system time slot control circuit 12 to the other-system time slot control circuits 12, respectively.

The exclusive control signal is sent to the time slot control circuit 12 of another system when the time slot control circuit 12 receives from the microprocessor 10 a line allocation command for instructing the allocation of a line to a certain time slot. This is a control signal for requesting not to use the time slot. The time slot control circuit 12 of each system is connected to the network via the frame control circuit 14.

FIG. 2 shows the configuration of an embodiment of the time slot controller 12. In FIG. 2, the time slot allocation circuit 18 includes a microprocessor 10 and a control line 15.
And 17 and the control lines 16A and 16B to the time slot allocation circuit 18 of the other system. Time slot allocation circuit 18
Is also connected to the time slot management table 19.

The time slot management table 19 is composed of a time slot number, an E flag indicating whether or not the time slot is being used, and a line address assigned to the time slot in association with each other. .

The LNC (line control unit) selection circuit 20 is connected to the line control unit 13 and the time slot management table 19, and selects the line control circuit 13 currently used based on the contents of the time slot management table 19. To do.

The operation of the time slot switching control system shown in FIGS. 1 and 2 will be described below with reference to FIGS. (1) FIG. 3 shows the contents of the time slot management table 19 of the # 0 and # 1 time slot control units 12 in the initial state.

(2) If the communication control program of the # 0 system issues a line allocation command for allocating the line address 5 to the time slot 1 in the initial state of FIG. 3, the time slot allocation circuit of the # 0 system. 18 is
The E flag of the time slot 1 of the time slot management table 19 is checked.

In this case, since the E flag is not "1", the instructed line address is set in the time slot 1 and the # 1 system time slot control unit 12 stops using this time slot 1. Issue the exclusive control signal to request.

In the # 1 system time slot controller 12,
Whether or not this time slot is used is checked by checking the E flag of the time slot management table 19, and since it is "0" in this case, nothing is executed for this exclusive control signal.

In the initial state, when the communication control program of the # 1 system issues a line allocation command for allocating the line address 7 to the time slot 3, # 0
As with the system, there is no collision with other systems, so line 7 is assigned to time slot 3. FIG. 4 shows the contents of the time slot management table 9 at this time.

If the microprocessor of the # 1 system issues a line assignment instruction to assign the line address 2 to the time slot 1 in the state of FIG. 4, # 1
In the system time slot control unit 12, the time slot allocation circuit 18 uses the time slot management table 19
Check the E flag of time slot 1 of.

In this case, since it is not "1", the designated line address is set in time slot 1 and
An exclusive control signal is issued to the # 0 system time slot control unit 12 requesting to cancel the use of the time slot 1.

The # 0 system time slot control unit 12 checks the E flag of the time slot management table 19 to see if this time slot is being used. Since it is "1" in this case, this E flag is reset to "0". At the same time, it issues a line address notification interrupt signal for notifying the microprocessor 10 of the line address used (5 in this case). FIG. 5 shows the state of the time slot management table 19 at this point.

(4) Next, in the state of FIG. 5, it is assumed that the # 1 system microprocessor 10 issues a line allocation instruction for allocating the line address 6 to the time slot 3. The # 1 system time slot allocation circuit 18 uses the E of the time slot 3 of the time slot management table 19.
Check the flag.

In this case, since it is "1", the designated line address is set, and the line address before being newly set (7 in this case) is set in the microprocessor 10.
A line address notification interrupt signal for notifying the same is issued, and an exclusive control signal for requesting the # 0 system time slot control unit 12 to stop using this time slot 3 is issued.

The # 0 system time slot controller 12 checks the E flag of the time slot management table 19 to see if this time slot is being used. In this case, since it is "0", nothing is executed for this exclusive control signal. do not do. FIG. 6 shows the time slot management table 1 at this point.
9 shows the state 9.

(5) In the state shown in FIG. 6, it is assumed that the microprocessors # 0 and # 1 simultaneously issue line assignment instructions for assigning the line address 8 and the line address 9 to the time slot 2.

Time slot allocation circuit 18 for each system
Sets the E flag to "1" because the E flag of the time slot 2 is "0", allocates each designated line address, and uses the time slot 2 to the time slot control units 12 of other systems. Issue an exclusive control signal requesting to cancel.

At this time, if it is preliminarily set that the priority of the # 0 system is higher, the exclusion control signal is ignored by the # 0 system by this setting, but the exclusive control of the # 1 system having a lower priority is performed. The signal resets the E flag of the time slot 2 to "0" and the microprocessor 1
A line address notification interrupt signal for notifying the line address that could not be assigned to 0 (9 in this case) is issued. FIG. 7 shows the state of the time slot management table 19 at this point.

FIG. 8 specifically shows the communication control device of FIG. In FIG. 8, two time slot control units 100 having the same configuration are connected to the # 0 system and # 1 system processors 101, respectively.

The time slot control section 100 receives the MST / SLV instruction signal (priority signal) from the time slot allocation circuit 102 for allocating and deallocating time slot to channel number, and the processor 101, and gives priority to which system. MST / SL to determine if you have the right
A V circuit 103, a TS-TABLE 104 that holds a correspondence table of time slots and channel numbers in a memory, and an LNC selection circuit 105 that selects an LNC for each channel.

FIG. 9 is a detailed circuit diagram of the MST / SLV circuit 103. In FIG. 9, each MST / SLV circuit has an MST / SLV signal from its own processor and an MS of another system.
The presence / absence of the priority is determined based on the MST / SLV from the T / SLV circuit, and the MST signal indicating the priority is output to the time slot allocation circuit 102.

The MST / SLV circuit 103 includes an MST signal from the processor of its own system and the MST / SLV circuit 1 of the other system.
OR of MST signal from 03, SLV signal from own system processor and SLV from other system MST / SLV circuit
AND with the signal NOR, and output this AND with D-
It is the D input of FF106.

The D-FF 106 outputs the MST signal to its own time slot allocation circuit 102. Further, each MST / SLV circuit sends the MST signal and SLV signal from the processor 101 of its own system to the MST / SLV circuit 103 of the other system.

In the initial state, the D-FF 106 is SL
V, that is, set to "0". In this state, when the MST signal from at least one of the processors 101 is active and both SLV signals are inactive, the D-FF 106 is set to "1", that is, MST, and otherwise. Is set to SLV.

The MST / SLV circuit 103 is an MS of another system.
It is necessary to control so as not to output the MST signal at the same time as the T / SLV circuit 103. Therefore, if one is set to SLV, send the MST signal to the other,
When set to, the SLV signal is sent to the other.

If both MST / SLV circuits 103 are S
When the LV is instructed, the MST signal is sent from each MST / SLV circuit to another MST / SLV circuit.
When the MST signal and the SLV signal are mixed, priority is given to the instruction of the SLV signal, so that both MST / SLV signals are given.
The D-FF 106 of the circuit 103 is prevented from being set to MST at the same time.

FIG. 10 shows a time slot allocation circuit 10
2 is a circuit diagram of FIG. Each time slot allocation circuit 10
2 has a counter 107, a time slot allocation / deallocation unit 108, and a TS-TABLE management unit 109.

The counter 107 counts the bits of one time slot, sends the bit 1 as a FRM RD signal to the TS-TABLE 104, and the bit 2 of the TS-TA.
It is sent to the BLE management unit 109, and bit 8 is sent to the time slot allocation / deallocation unit 108 and TS-TABLE management unit 109.

Time slot allocation / deallocation unit 108
Executes a time slot allocation / deallocation instruction from the processor 101 of its own system, and performs exclusive control so as not to compete with the time slot allocation circuit 108 of another system for the same time slot. If the channel number is lost to another system or the channel number is changed by itself, the lost channel number or the changed channel number is notified to the processor 101 of the own system.

When the time slot allocation / deallocation unit 108 receives the channel allocation command, TS-TABLE
A channel number is written in a corresponding time slot of 104 and channel allocation is performed.

At this time, if the time slot has already been used, the correspondence between the time slot and the channel is canceled, the newly designated channel number is assigned, and the processor 101 is notified of the channel number before the change. Send an interrupt signal.

When channel numbers are assigned to the time slots, the time slot assignment circuit 1 of the other system is used.
02, sends a SLT DSBL signal that prohibits allocating a channel to that time slot.

Upon receiving the SLT DSBL signal, the time slot allocating / deallocating unit 108 of the time slot allocating circuit 102 of the other system cancels the correspondence between the time slot and the channel when the corresponding time slot is used and cancels it. A channel number notification interrupt signal for notifying the selected channel
Send to.

The TS-TABLE management unit 109 is the T of its own system.
Manage S-TABLE.

FIG. 11 shows the input / output of the TS-TABLE 104. TS-TABLE104 is dual port RA
It is composed of M, and is capable of two inputs and outputs at the same time.

Port 0 of TS-TABLE 104 is used for reading and writing by a command with time slot allocation / deallocation unit 108, and port 1 is currently used with TS-TABLE management unit 109 for a time slot. Used for reading and writing.

FIG. 12 shows the contents of TS-TABLE.
In the TS-TABLE 104, time slots and channels are associated with each other by flags E and E0.
When both E and E0 are "0", it means that the time slot is not used, and the channel number of the time slot is invalid.

When E is "0" and E0 is "1", it indicates that the time slot allocation command has been received but the time slot is not yet used, and the channel number of the time slot is newly associated. This is the assigned channel number.

If both E and E0 are "1", this indicates that this time slot is currently used. When E is "1" and E0 is "0", this time slot is currently in use, but a time slot release command has been received.

FIG. 13 is a detailed circuit diagram of the time slot allocation / deallocation unit 108. In FIG. 13, an instruction register 110 temporarily holds a time slot allocation / deallocation instruction from the processor 101.

The time slot allocation / deallocation instruction includes a bit S, a bit R, a channel number, and a time slot number. S is set to "1" when this instruction is an allocation instruction, and R is set to "1" when this instruction is a release instruction.

When an instruction is set in the instruction register 110, the channel number of the corresponding time slot and the flag E are read from the TS-TABLE 104, and at the same time, the currently executed time slot number is received from the frame control unit and the instruction The comparison circuit 111 compares the time slot number given in step 1).

If the comparison result of the comparison circuit 111 is a match, the channel number currently in use cannot be changed, and therefore the execution of the instruction is made to wait. When S is set in the instruction register 110, the comparison circuit 112 compares the current channel number with the channel number given by the instruction.

Based on the results of the comparison circuits 111 and 112 and the value of the flag E, the gate circuit group determines whether the allocation by the instruction is a new allocation or an allocation change. When the allocation is changed as a result of the above determination, the channel number of TS-TABLE 104 is written to the notification channel number register 13 and sent to the processor 101.

In the case of new allocation and allocation change, the SLT DSBL signal is sent to another time slot allocation / deallocation unit 108. The allocation is released when R is set in the register 110 and the comparison result of the comparison circuit 111 does not match, or when the SLT DS from another system.
It is performed when the BL signal is received.

NAND gate 14 and AND gate 1
5 indicates that when a time slot allocation command is given to the time slot allocation / deallocation units 108 of both systems at the same time,
That is, when the SLT DSBL signals are output from both systems at the same time, this is a circuit for causing the system on the master side determined by the MST / SLV circuit 103 to ignore this signal.

When the SLT DSBL signal is received and the corresponding time slot is used, TS-TABL is set in the notification channel number register 13.
The channel number of E104 is written, and the processor 10
Notify 1.

When new allocation, allocation change, or deallocation is confirmed, the corresponding data is TS-TA.
At the same time as being written to the BLE 104, the register 110
Is reset. Reference numeral 16 is an adjusting circuit for matching the timings of the two inputs of the gate 17.

FIG. 14 is a detailed circuit diagram of the TS-TABLE management unit 109. At bit 1 of the time slot, the BIT1 signal of the counter 107 causes the time slots E and E0 currently in progress to be read from the TS-TABLE 104.

The read E and E0 are set in the flip-flops 118 and 119, respectively, at the timing of bit 2. If both the set E and E0 are "0" or "1", no operation is performed.

When E is "0" and E0 is "1", TS
-“1” is set to the corresponding E in the TABLE 104, bit 8
Write at the timing of. When E is “1” and E0 is “0”, the corresponding E of TS-TABLE 104 is
"0" is written to the bit 8 at the timing of bit 8.

As described above, in the communication control device using the time slot control method according to the present invention, no matter what line allocation command is issued from the processors of the two systems, only one of the systems is surely issued. No line address is assigned and therefore the same time slot can be guaranteed not to be used by both systems.

Further, the processor can know which line cannot be used by the line address notification interrupt signal only when the line address allocation fails or the line address used up to now becomes invalid. Therefore, the load on the processor and the communication control program can be reduced.

In each of the above-mentioned embodiments, the case where the number of time slot control units is two is shown, but two or more time slot control units may be used. In that case, it is necessary to connect all the time slot control units one-to-one with an exclusive control signal.

[0084]

As described above, according to the present invention,
In the multiplexed communication control device, it is possible to remedy a failure of the communication control program that could not be remedied in the past. Therefore, the fault recovery rate of the entire system is improved, which largely contributes to the improvement of the reliability of the multiplex communication control device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a time slot control unit in FIG.

FIG. 3 is a diagram (No. 1) for explaining the operation of the circuit of FIG. 1;

FIG. 4 is a diagram (No. 2) for explaining the operation of the circuit of FIG. 1;

5 is a diagram (No. 3) for explaining the operation of the circuit of FIG. 1. FIG.

FIG. 6 is a diagram (No. 4) for explaining the operation of the circuit of FIG. 1;

FIG. 7 is a diagram (No. 5) for explaining the operation of the circuit of FIG. 1;

FIG. 8 is a diagram specifically showing the communication control device of FIG. 1.

FIG. 9 is a circuit diagram of an MST / SLV circuit.

FIG. 10 is a circuit diagram of a time slot allocation circuit.

FIG. 11 is a diagram showing input / output of TS-TABLE.

FIG. 12 is a diagram showing the contents of TS-TABLE.

FIG. 13 is a circuit diagram of a time slot allocation / deallocation unit.

FIG. 14 is a circuit diagram of a TS-TABLE management unit.

FIG. 15 is a diagram for explaining a conventional technique.

FIG. 16 is a diagram showing a structure of a frame.

[Explanation of symbols]

1 Microprocessor 2 Time slot control unit 3 Line control unit 4 Frame control unit 10 Microprocessor 11 Data line 12 Time slot control unit 13 Line control unit 14 Frame control unit 15, 16A, 16B, 17 Control line 18 Time slot allocation circuit 19 Time slot management table 20 LNC selection circuit 100 Time slot control unit 101 Processor 102 Time slot allocation circuit 103 MST / SLV circuit 104 TS-TABLE 105 LNC selection circuit 106 D-FF 107 Counter 108 Time slot allocation / deallocation unit 109 TS-TABLE Management unit 110 Registers 111, 112 Comparison circuit 113 Notification channel number register 114, 115, 117 Gate 116 Delay circuit 118, 119 Flops MST / SLV master - slave indication signal MST master signal SLV slave signal SLT DSBL exclusive control signal I / O WR, I / O RD, I / O DATA, FR
M WR, FRM RD, FRM DATA signal E, E0 flag

Claims (2)

[Claims] 1. A communication control device for a time division multiplex communication system, comprising two processors each for executing a communication control program, and two sets for respectively performing line control by inputting line data from each of the two processors. Line control unit and two sets of line control units, each of which inputs data to associate a time slot with a line address and stores the current association state. Unit, means for sending a line assignment command from each of the two processors to the corresponding time slot control unit, and an instruction to assign a line to a time slot, and from each of the two time slot control units Notification to notify the corresponding processor that the allocation to the time slot of the line has been canceled And a means for transmitting an exclusive control signal for prohibiting the allocation of the time slot of the line from one of the two time slot control units to the other, and each of the time slot control units, If the time slot indicated by the line allocation instruction from the corresponding processor is not currently in use, the line is allocated to the time slot and an exclusive control signal is sent to the other time slot control unit to Prohibits the use of time slots, and when the time slot indicated by the line allocation instruction is currently in use,
When the use of the time slot is switched to the newly designated line, the address of the line that has been deallocated is notified to the corresponding processor, and when an exclusive control signal is received from the other time slot control unit, If the time slot is being used, the time slot switching control method is characterized in that the time slot is not associated with the line address and the processor is notified of the canceled line address. . 2. A means for assigning a priority to the two time slot control units, wherein the line allocation command instructs the two time slot control units to simultaneously specify line addresses in the same time slot, The time slot control unit having a high priority assigns a line to a time slot, and the other time slot control unit controls the microprocessor to notify each of the line addresses that cannot be assigned. The time slot switching control method according to claim 1, wherein