JPH0786868B2 - Communication method between processors - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication method, and more particularly, to a computer system in which a main processor, a plurality of coprocessors, and a main memory are connected to a common address bus and data bus. In the above, each coprocessor relates to an interprocessor communication method for performing communication under the control of the main processor.

2. Description of the Related Art A conventional interprocessor communication method is, for example, Motorola.
Inc. (Motorola Incorporated) MC68881 F
Some are shown in the Loating-Point Coprocessor User's Manual (First Edition).

Figure 3 shows the conventional inter-processor communication method, Motorola Incoporation 32-bit microprocessor MC68020 (hereinafter referred to as MC68020) and Motorola Incorporation Floating Point Coprocessor MC68881 (hereinafter referred to as MC68881). FIG. 4 is an explanatory diagram showing a communication method performed between the above. 21 is
It is the main processor MC68020. 22 is a coprocessor MC68881. 23 is a Coprocessor Decode Logic that decodes a part of the address of the MC680202 (FCO-FC2 and A19-A13) and outputs the result to CS. 24 is a function code signal FCO-FC2 that distinguishes the processor state and the address space of the current bus cycle. 25 is the address bus A19-A13. 26 is a chip select signal CS. 27 is an address strobe signal AS indicating that valid information is present on the address bus. 28
Is a data strobe signal DS which indicates that valid information is present on the data bus. Reference numeral 29 is a read / write signal R / W indicating a data transfer method. 30 is an acknowledge signal DSACK1 indicating the completion and size of data transfer
It is −0. 31 is the address bus A4-A1. 32
Is the data bus D31-DO. 33 is a coprocessor interface register (hereinafter referred to as CIR) provided for the MC68881 22 to communicate with the main processor.
Is.

Figure 4 shows the coprocessor in the MC68881 22 in Figure 3.
It is a figure for explaining in detail an interface register. In FIG. 4, 34 is MC68881 and 22 is MC68.
020 21 32-bit x 3 and 16-bit x 10 coprocessor interfaces provided to communicate with
It is a register.

In the conventional inter-processor communication method configured as described above, the MC68020 21 will transfer the 32-bit data in the main memory to the MC68881 22 as floating point data.
The communication procedure performed when executing the instruction stored in the register will be described.

(1) The MC68020 21 decodes the instruction and determines that the instruction is for MC68881 22.

(2) MC68020 21 is the command CIR for MC68881 22.
Perform the following subsequence to transfer the command to 34.

[I] Data that CS 26 becomes active is output to FCO-FC224 and A19-A1325. At the same time, it is decoded by the coprocessor decode logic 23 and CS26 becomes active.

[Ii] R / W 29 indicates the direction of data write.

[Iii] When AS 27 becomes active, A4-A1 31 outputs the address of command CIR 34.

[Iv] Command output by MC68020 21 when DS 28 becomes active (this time, command to store 32-bit data in main memory transferred by MC68020 21 to floating point data register on MC6881 22) )But
Written to command CIR 34 through D31-D0 32.

[V] The MC68881 22 informs the MC68020 21 of the completion and size of the data transfer by using DSACK1-0 30 when the command is written in the command CIR 34.

(3) The MC68881 22 decodes the command written in the command CIR 34 and starts executing the command.

(4) The MC68881 22 executes the following steps (5) to (8) while it needs the service of the MC68020 21.

(5) The MC68881 22 writes the requested service (this time, 32-bit data is transferred as an operand) to the response CIR 34.

(6) The MC68020 21 reads the service requested by the response CIR 34 using the following subsequence. Note that this service is read by the MC68020 21 at appropriate intervals, so if the previous command is still executing, the service requested by the response CIR 34 is not yet written. Repeats the following sequence many times until written.

[I] Data that CS 26 becomes active is output to FCO-FC224 and A19-A1325. At the same time it is decoded by the coprocessor decode logic 23 and CS 26 becomes active.

[Ii] R / W 29 indicates the data read direction.

[Iii] When AS 27 becomes active, A4-A1 31 outputs the address of response CIR 34.

[Iv] MC68020 21 is D when DS 28 becomes active
Read the contents of the response CIR 34 through 31-D0 32.

[V] MC68881 22 is a CIR 34 for MC68020 21 for response.
Use DSACK1-0 30 to read the size of data transfer to MC68020 21.

(7) The MC68020 21 starts executing the read service request.

(8) The MC68020 21 reads the 32-bit data specified by the instruction from the main memory and uses it as the CIR for the MC68881 22 operand.
Write to 34 using the following subsequence:

[I] Data that CS 26 becomes active is output to FCO-FC224 and A19-A1325. At the same time it is decoded by the coprocessor decode logic 23 and CS 26 becomes active.

[Ii] R / W 29 indicates the direction of data write.

[Iii] When AS 27 becomes active, A4-A131 outputs the address of operand CIR 34.

[Iv] Operand output by MC68020 21 when DS 28 becomes active is used as an operand through D31-DO 32
Written and written to CIR 34.

[V] The MC68881 22 informs the MC68020 21 of the completion and size of data transfer by using DSACK1-0 30 when a command is written in the CIR 34 for operand.

(9) MC68881 22 was written in CIR 34 for operand
Receive services by reading 32-bit data.

(10) MC68881 22 returns to CIR 34 for response when the service of MC68020 21 is no longer needed (requires no service).

(11) MC68881 22 written to CIR 34 for operand
32-bit data is floating point data
Store in register.

(12) When the MC68881 22 finishes executing the command, it notifies the response CIR 34 of the end of processing.

(13) The MC68020 21 proceeds to execute the next instruction.

Problems to be Solved by the Invention However, in the above configuration, when the MC68020 21 tries to write the operand in the main memory required for executing the coprocessor instruction to the CIR 34 for the operand of the MC68881 22, the MC68020 Since 21 fetches the data in the main memory to itself and then transfers it to the MC68881 22 as an operand, it takes a very long time from when the MC68881 22 receives the command until it receives the operand. And when the previous instruction has already finished executing, the MC68881 22 will be in the idling state during the time. Therefore, there is a problem that it takes time to communicate between the MC68020 21 and the MC68881 22 and the overall execution of the MC68881 22 is slow. Further, since the operand is transferred from the main memory to the MC6802021 via the data bus and again transferred to the MC6888122 via the data bus, there is a problem that the bandwidth of the bus is narrowed.

In view of the above point, the present invention has an object of providing an interprocessor communication method capable of performing high-speed interprocessor communication, enabling a coprocessor to execute from the viewpoint of a main processor, and increasing a bus bandwidth.

According to the present invention, when executing a coprocessor instruction, when the coprocessor requires an operand, the coprocessor does not go through the main processor under the control of the main processor and the main memory is not used. This is an inter-processor communication method in which a coprocessor directly writes in the main memory under the control of the main processor when the operand is directly fetched and the operation result is written in the main memory.

The present invention has the above-described configuration, and thus the coprocessor can fetch the operand from the main memory without passing through the main processor and write the operation result in the main memory without passing through the main processor, thereby enabling high-speed interprocessor communication. , The coprocessor sees from the main processor to run faster and the bus bandwidth increases.

Embodiment FIG. 1 is a block diagram of an embodiment of a system for carrying out the interprocessor communication method of the present invention. In FIG. 1, reference numeral 1 is a main memory that stores instructions and data. Reference numeral 2 reads the instruction in the main memory 1, decodes it, and normally executes it by itself. If it is a coprocessor instruction, it manages communication between coprocessors to execute it in the target coprocessor, and executes commands. It is the main processor that issues and reads operands. A coprocessor 3 receives commands and operands and executes coprocessor instructions. Reference numeral 4 denotes an instruction execution device that decodes and executes the read instruction in the main processor 2. 5
Is a communication control device for controlling, in the main processor 2, instructions for reading instructions from the main memory 1, writing and reading data to and from the main memory 1 and communication procedures between the coprocessor 3. An instruction execution unit 6 executes a coprocessor instruction using the received command and operand in the coprocessor. 7 is a coprocessor 3
In the above, the communication control device controls the communication procedure between the main processors 2. Reference numeral 8 denotes a communication command register in which a fixed address is allocated in the communication control device 7 of the coprocessor 3, data can be written and read using the address, and a command transferred by the main processor 2 is written. is there. Reference numeral 9 is an operand that allows the communication control device 7 of the coprocessor 3 to write and read data using a fixed address assigned to it, which the main processor 2 transfers or reads from the main memory 1. Is a communication operand register to which is written. The coprocessor 3 confirms whether or not the coprocessor 3 has all the necessary commands and the operation bar h for executing the coprocessor instruction, and when the end of the previous instruction is confirmed, the command and the next instruction It is a signal line CPRDY that informs the main processor 2 that the operand can be written. Reference numeral 11 is a signal RDY for the main memory 1 and the coprocessor 3 to notify the end of the data transfer cycle. Reference numeral 12 is a read / write signal R / W indicating the direction of data transfer on the bus. Reference numeral 13 is an address strobe signal AS indicating that a valid address is present on the address bus. 14 is an address bus. Reference numeral 15 is a data strobe signal DS indicating that valid data is present on the data bus. 16 is a data bus.

FIG. 2 is a timing chart diagram for explaining in detail the procedure of the communication method in the block diagram of the inter-processor communication method of FIG.

Regarding the interprocessor communication method of this embodiment configured as described above, the main processor 2 will be described below on the main memory 1.
A communication procedure performed when executing an instruction to store 32-bit data in the floating data register on the coprocessor 3 will be described.

(1) In the main processor 2, the communication control device 5
An instruction is read from the main memory 1, and the instruction execution device 4 decodes the instruction.

(2) As a result of decoding, when the instruction is found to be a coprocessor instruction, the main processor 2 starts preparing a command to be written in the coprocessor 3 and an address of an operand existing in the main memory 1.

(3) In the main processor 2, the instruction execution device 6
A command to be transferred to the coprocessor 3 is generated, and the communication control device 5 writes the command in the communication command register 8 of the coprocessor 3 using the following subsequence.

[I] In the main processor 2, the communication control device 5
R / W12 is made inactive and data write is notified.

[Ii] In the main processor 2, the communication control device 5
An address that specifies the communication command register 8 is output to the address bus 14, and at the same time, AS 13 is activated to notify the validity of the address.

[Iii] Communication controller 5 in main processor 2
Outputs a command to be transferred to the data bus 16 and at the same time activates DS15 to notify the validity of data.

[Iv] In the coprocessor 3, the communication control device 7 uses the AS1
3. When the DS15 becomes active, the command on the data bus 16 is written in the communication command register 8 designated by the address bus 14.

[V] In the coprocessor 3, the communication control device 7 inactivates the RDY 11 when the correct command is written in the communication command register 8, and the main processor 2
To notify the communication control device 5 at the end of the command transfer cycle.

[Vi] In the main processor 2, the communication control device 5
End the command transfer cycle.

(5) In the coprocessor 3, the instruction execution device 6 predecodes the written command, recognizes that the necessary operand is in the main memory 1, and the communication control device 7
Then, preparations are made for fetching valid data on the data bus 16.

(6) In the main processor 2, the communication control device 5
The data on the main memory 1 is read using the address on the main memory 1 of the operand to be transferred to the coprocessor 3. The coprocessor 3 fetches the required operand in the communication operand register 9 using the following sub-sequence.

[I] In the main processor 2, the communication control device 5
R / W 12 is activated and data read to main memory 1 is notified.

[Ii] In the main processor 2, the communication control device 5
The address designating the operand on the main memory 1 is output to the address bus 14, and at the same time, the AS 13 is activated to notify the validity of the address.

[Iii] Communication controller 5 in main processor 2
Activates DS15.

[Vi] The main memory 1 outputs the data of the specified address to the data bus 16 and, at the same time, makes the RDY11 inactive at the end.

[V] In the coprocessor 3, the communication control device 7
3. When the DS15 is active and RDY 11 is inactive, the data bus 14 is added to the communication operand register 9
Take the above data as an operand.

[Vi] In the main processor 2, the communication control device 5
Ends the operand transfer cycle.

[Vii] In the coprocessor 3, the communication control device 7 compares whether or not all the necessary commands and operands for executing the coprocessor instruction are prepared with the result of predecoding. When it is confirmed that they are aligned and it is possible to end the previous instruction and write the command and operand of the next instruction, the CPRDY 10 is made inactive to notify the main processor 2 that the next instruction can be executed.

[Viii] Communication control device 5 in main processor 2
Ends the entire data transfer cycle.

(7) In the coprocessor 3, the instruction execution unit 6 decodes the command written in the communication command register 8 and starts storing the data written in the communication operand register 9 in the floating data register.

(8) In the main processor 2, the instruction execution device 4 is
Proceed with execution of the next instruction.

As described above, according to this embodiment, the coprocessor receives the command transferred from the main processor, and also receives the data output to the data bus when the main processor reads to the main memory as the direct operand. , High-speed inter-processor communication can be performed, the co-processor can be executed faster as seen from the main processor,
Moreover, it becomes possible to widen the band width of the bus.

In the present embodiment, the CPRDY 10 is a single signal line, but the CPRDY 10 is a plurality of signal lines for notifying an error occurrence in the coprocessor, an exception processing request, a request for necessary data such as a program counter, etc. May be

Although the 32-bit data transfer instruction has been described in the present embodiment, the instruction, the size of the data, the read / write location of the operand, etc. are not particularly limited.

Further, in the present embodiment, when the coprocessor instruction stores the operation result in the main memory, the main processor performs the address output to the address bus and the control of other signal lines, as in the case of reading the operand. The coprocessor only needs to output the calculation result to the data bus.

Further, in the present embodiment, the command issuance to the coprocessor does not disturb the instruction execution order in the main processor, so that it is possible even if the main processor is performing pipeline processing.

EFFECTS OF THE INVENTION As described above, according to the present invention, high-speed inter-processor communication can be performed, execution of the coprocessor viewed from the main processor can be accelerated, and the bandwidth of the bus can be widened. The practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a system for carrying out the interprocessor communication method of the present invention, FIG. 2 is a timing chart for communication of the embodiment, and FIG. 3 is a conventional interprocessor communication method. FIG. 4 is a block diagram of the system shown in FIG. 3, and FIG. 4 is a block diagram of the coprocessor interface register of the conventional example shown in FIG. 1 ... Main memory, 2 ... Main processor, 3 ... Coprocessor, 4 ... Instruction execution device in main processor, 5 ...
Communication control device in main processor, 6 ... Instruction execution device in coprocessor, 7 ... Communication control device in coprocessor, 8 ... Communication command register, 9 ... Communication operand register, 10 ... Signal line CPRDY, 11 ... Signal line R
DY, 12 ... Signal line R / W, 13 ... Address strobe AS, 14 ...
Address bus, 15 ... Data strobe DS, 16 ... Data bus, 21 ... MC68020, 22 ... MC68881, 23 ... Coprocessor decode logic, 24 ... Function code signal FC
O-FC2, 25 ... Address bus A19-A13, 26 ... Chip select signal CS, 27 ... Address strobe signal AS, 28 ...
Data strobe signal DS, 29 ... Read / write signal R /
W, 30 ... Acknowledge signal DSACK1-0, 31 ... Address
Bus A4-A1, 32 ... Data bus D31-DO, 33 ... Coprocessor interface register, 34 ... Coprocessor
Interface register.

Claims (1)

[Claims] 1. A main processor and a plurality of coprocessors are mutually connected to a signal line, the main processor and the plurality of coprocessors and a main memory are connected to a common address bus and a data bus, and the main processor is a coprocessor. In a system for executing an instruction using the coprocessor, the main processor writes a command required by the coprocessor to execute the coprocessor instruction from the main processor to the coprocessor, When the operand required for execution exists in the main memory, the coprocessor directly reads the operand from the main memory under the control of the main processor, and the coprocessor instruction stores the operation result in the main memory. When writing, the coprocessor There interprocessor communication method and writes directly to the main memory in the managed the main processor.