JPH077936B2 - n-bit demultiplexing conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an n-bit demultiplexing conversion circuit for performing n-bit multiplexing and n-bit demultiplexing in an n-bit multiplexing terminal device.

In the present specification, n-bit demultiplexing is an inverse conversion process of n-bit multiplexing, and the device configuration is also the same, and since it can be easily analogized from the description of the n-bit multiplexing process (n-bit multiplex conversion circuit), Detailed description of the n-bit separation processing (n-bit separation conversion circuit) is omitted.

[Conventional technology]

The multiplexing unit in the digital signal multiplexing system is
Bit-based multiplexing that sequentially multiplexes the input signal sequence of each channel bit by bit, and word-wise multiplexing that multiplexes the input signal sequence of each channel by a fixed code length (word consisting of n bits) (this specification) In the book, it is referred to as "n-bit multiplexing"), and there is frame-based multiplexing for multiplexing for each frame.

The conventional input N (N is an integer multiple of n) channel n-bit multiplex conversion circuit has a configuration realized by one-stage parallel / serial conversion process and a configuration realized by a plurality of stages of parallel / serial conversion process. .

FIG. 10 is a diagram for explaining an input N-channel n-bit multiplex conversion circuit when it is realized by one-stage parallel / serial conversion processing.

In the figure, the input signal of the input channel ch1~chN, for each channel: the input [1 n] S / P conversion circuit (n-bit memory) to 101 ₁ to 101 _N, respectively n bits n
Number of parallel signals {1-1 to 1-n}, {2-1 to 2-n}, ..., {N-1
~ Nn} is once converted. Each parallel signal is input to the [nN: 1] parallel / serial conversion circuit 103 and sequentially bit-multiplexed to be converted into an n-bit multiplexed signal.

FIG. 11 is a diagram for explaining an input N-channel n-bit multiplex conversion circuit when it is realized by a plurality of stages of parallel / serial conversion processing. FIG. 11 (a) shows the overall configuration, and FIG. 11 (b) shows the configuration of the final stage and time series data to be input / output.

In the figure, the input signals of the input channels ch1 to chN are sequentially n-bit multiplexed by a predetermined number of channels in the n-bit multiplex conversion units 111 and 112 in each stage, and the n-bit multiplex conversion unit 113 in the final stage. Is input to N / m channels together.

Channel c input to the final stage n-bit multiplex conversion unit 113
The time series data of h1 ′ to ch (N / m) ′ are input channels ch1 to chm, ch (m + 1) to ch2m, ..., ch (N-m +
1) to chN are multiplexed n bits, [1: mn]
The signals are input to the serial / parallel conversion circuits 115 _{1 to} 115 _{N / m} , respectively.

Each [1: mn] serial / parallel conversion circuit 115 _{1 to} 115 _{N / m} has m × n parallel signals {1-1 to mn}, {(m + 1) -1 to (2m)-.
, n, ..., {(N-m + 1) -1 to Nn}. Each parallel signal is a [nN: 1] parallel / serial conversion circuit
It is input to 117 and sequentially bit-multiplexed to be converted into an n-bit multiplexed signal.

[Problems to be Solved by the Invention]

By the way, in any of the configurations of the input N-channel n-bit multiplex conversion circuits shown in FIGS. 10 and 11, in any case, the [nN: 1] parallel / serial conversion circuits 103 and 117 are finally obtained.
Was needed.

Therefore, when the number of multiplexed bits n or the number of input channels N becomes large, the circuit scale of the parallel / serial conversion circuit becomes large and high-speed operation may become difficult.

Further, before performing the parallel / serial conversion processing, it is necessary to decompose the time-series data by using the serial / parallel conversion circuit or the memory, which complicates the control circuit for performing the speed conversion.

Furthermore, when the number N of input channels is changed, a new circuit design is required, and there is a lack of flexibility.

The above is the same for the n-bit decomposition conversion circuit.

The present invention solves such a conventional problem, and is capable of high-speed operation and flexible n-bit multiplex decomposition conversion even when the number of multiplexed bits n or the number of input channels N becomes large. The purpose is to provide a circuit.

[Means for Solving the Problems]

 FIG. 1 is a block diagram showing the principle configuration of the present invention.

An n-bit multiplex conversion circuit that multiplexes each input signal of n (n is a positive integer) every n bits (FIG. 1 (a))
, The i-th (i ≦ n) of each input signal of n channels
A time slot conversion circuit that performs time slot replacement with each bit as the output signal of the i-th channel in units of n bits, and converts into a new n-channel signal sequence,
This new n-channel signal is input and a multiplexing unit that performs n-to-1 multiplexing is configured.

An n-bit multiplex conversion circuit that multiplexes input signals of N (N is an integer multiple of n) channels every n bits (FIG. 1 (b))
In the above, there are N / n number of time slot conversion circuits, each time slot conversion circuit has a predetermined channel correspondence, and each time slot exchange is performed in units of n bits to obtain a new N channel signal sequence. A time slot conversion unit for conversion and a multiplexing unit for inputting this new N-channel signal and performing N-to-1 multiplexing are configured.

In an n-bit separation conversion circuit that separates N (N is an integer multiple of n) channel input signal for every n bits, 1 to N
And a time slot conversion unit that has N / n of the time slot conversion circuits, performs inverse conversion by switching inputs and outputs, and converts the original N channel signal sequence. It is configured with.

[Work]

The present invention is a time slot conversion circuit that performs bit multiplexing by performing, in n-bit units, time slot replacement having the i-th bit of each input signal of n channels as the output signal of the i-th channel. In the department,
Since it is not necessary to disassemble the input signal by parallel conversion,
It can be configured only with a parallel / serial conversion circuit of N: 1 or less.

Therefore, the number of multiplexed bits n or the number of input channels N
However, the conversion processing speed depends on only the speed of the multiplexing unit even when the value becomes large, so that it is easy to increase the speed and the configuration of the control circuit can be simplified.

Further, when the number of input channels N increases, an n-bit multiplex conversion circuit can be easily configured by adding a time slot conversion circuit corresponding to a predetermined channel. Furthermore, even if the configuration of the multiplexing unit is changed,
Correspondence can be taken only by changing the channel correspondence.

Further, the n-bit separation conversion circuit uses a time slot conversion circuit having the same configuration as that used in the n-bit multiplex conversion circuit, and in the separation conversion unit that performs bit separation by interchanging the inputs and outputs and performing inverse conversion. , It can be configured only with a serial / parallel conversion circuit of 1: N or less.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the present embodiment, first, the basic configuration and function of the present invention will be described using a 4-bit multiple conversion circuit (input 4 channels, 8 channels, 16 channels), and then an 8-bit multiple conversion circuit (input 8 channels, 64 channels). A specific configuration example will be described using.

FIG. 2 is a diagram for explaining a 4-bit multiple conversion circuit with four input channels. FIG. 2 (a) shows the overall structure,
2 (b) shows time series data input / output to / from the time slot conversion circuit, and FIG. 2 (c) shows time series data of a 4-bit multiplexed signal.

In the figure, the input terminal in of the time slot conversion circuit 21
1, in2, in3, in4, output terminals out1, out2, out3,
out4. Connect input channel ch1 (time series data 1-1, 1-2, 1-3, 1-4) to input terminal in1 and so on.
2 for ch2 (2-1, 2-2, 2-3, 2-4), in3 for ch3 (3-1, 3
-2, 3-3, 3-4), ch4 (4-1, 4-2, 4-3, 4-4) is connected to in4.

The time slot conversion circuit 21 performs 4-bit time slot conversion (rows and columns are exchanged), and outputs the first bit of time series data 1-1, 2-1 of each input channel from the output terminal out1.
Output 3-1 and 4-1. Similarly, from the output terminal out2, the second-bit time series data 1-2, 2-2, 3-2, 4-2, and from the output terminal out3 the third-bit time series data, 1-3, 2 -3, 3-
3, 4-3, time series data of each bit from output terminal out4 1-
Outputs 4, 2-4, 3-4, 4-4, and channel ch1 ', c respectively
Corresponds to h2 ', ch3', ch4 '.

In this embodiment, the multiplexing unit is realized by a single stage [4: 1] parallel / serial conversion circuit.

[4: 1] The parallel / serial conversion circuit 23 uses the channels ch1 ', ch
Input time series data of 2 ', ch3', ch4 ', 4: 1 normal /
By performing the serial conversion processing, it is possible to convert to the time series data (4-bit multiplexed signal) shown in FIG. 2 (c).

As described above, by using the time slot conversion circuit 21, the [1: 4] serial / parallel conversion circuit and [16: 1] parallel / serial conversion circuit for each channel described in the prior art are
[4: 1] The parallel / serial conversion circuit 23 can be replaced.

Further, since the time slot conversion circuit 21 can perform inverse conversion by exchanging its input and output,
It can be used as a time slot conversion circuit of a 4-bit separation conversion circuit.

FIG. 3 is a diagram for explaining a 4-bit multiple conversion circuit with 8 input channels. FIG. 3 (a) shows the overall structure,
FIG. 3 (b) shows the configuration of the time slot converter and time series data to be input / output, and FIG. 3 (c) shows time series data of a 4-bit multiplexed signal.

In the figure, the time slot conversion unit 31 of the present embodiment has a configuration in which the time slot conversion circuit 21 shown in FIG. 2B is used as a basic module and two of them (module # 1, module # 2) are used. Yes, the correspondence between the input terminals in1 to in4 of each module and the input channels ch1 to ch8 shown in Table 1, and the correspondence between the output terminals out1 to out4 of each module and the channels ch1 'to ch8' after time slot conversion Connected based on relationships.

By configuring the time slot converter 31 in this way, the time series data shown in FIG. 3B can be output to each of the channels ch1 'to ch8'.

In the present embodiment, the multiplexing unit is realized by a single stage [8: 1] parallel / serial conversion circuit.

[8: 1] The parallel / serial conversion circuit 33 uses the channels ch1 ′ to ch
By inputting 8'time-series data and performing the 8: 1 parallel / serial conversion process, the time-series data (4
A bit multiplexed signal) can be output.

FIG. 4 is a diagram for explaining a 4-bit multiple conversion circuit having 16 channels of input. FIG. 4 (a) shows the overall structure,
FIG. 4 (b) shows the configuration of the time slot converter and time series data to be input / output, and FIG. 4 (c) shows time series data of a 4-bit multiplexed signal.

In the figure, the time slot conversion unit 41 of the present embodiment has a configuration in which the time slot conversion circuit 21 shown in FIG. 2B is used as a basic module and four modules (modules # 1 to # 4) are used. , Input terminals of each module shown in Table 2
Connection is established based on the correspondence between in1 to in4 and input channels ch1 to ch16, and the correspondence between output terminals out1 to out4 of each module and channels ch1 ′ to ch16 ′ after time slot conversion.

By configuring the time slot converter 41 in this way, the time series data shown in FIG. 4 (b) can be output to each of the channels ch1 'to ch16'.

In the present embodiment, the multiplexing unit is realized by a single stage [16: 1] parallel / serial conversion circuit.

The [16: 1] parallel / serial conversion circuit 43 uses the channels ch1 ′ to c
By inputting time-series data of h16 'and performing a 16: 1 parallel / serial conversion process, the time-series data (4-bit multiplexed signal) shown in FIG. 4 (c) can be output.

As shown in FIGS. 3 and 4, when the number of multiplexed channels is increased, a time slot conversion circuit (basic module) 21 is added and the input / output terminals are optimized to easily cope with it. Therefore, a new circuit design is unnecessary.

The same applies to the 4-bit separation conversion circuit.

In addition, the multiplexing unit configured by each parallel / serial conversion circuit (23, 33, 43) has a multi-stage configuration (for example, [16: 1] parallel / serial conversion circuit is changed to [4: 1] parallel / serial conversion circuit. It is easy to deal with the case where it is realized by two stages of five.

FIG. 5 is a diagram illustrating another configuration example of a 4-bit multiplex conversion circuit with 8 input channels. Here, [8: 1] average /
An example is shown in which the multiplexing unit constituted by the serial conversion circuit (33 in FIG. 3) is implemented by seven [2: 1] parallel / serial conversion circuits in a three-stage configuration.

FIG. 5 (a) shows the overall configuration, and FIG. 5 (b) shows the configuration of the time slot conversion unit and the time series data to be input / output.

In the figure, the time slot conversion unit 51 of this embodiment has the same configuration as the time slot conversion unit 31 shown in FIG. 3B, but the input terminal in1 of each module shown in Table 3 is used.
To in4 and input channels ch1 to ch8, and the output terminals out1 to out4 of each module and the channels ch1 'to ch8' after time slot conversion are connected.

By configuring the time slot converter 51 in this way, the time series data shown in FIG. 5B can be output to each of the channels ch1 'to ch8'.

Each stage [2: 1] parallel / serial conversion circuit 53 ₁ to 53 _7, and inputs the time-series data of the channel Ch1'～ch8 ', the 2: by performing first the parallel / serial conversion, The time series data (4-bit multiplexed signal) shown in FIG. 3 (c) can be output.

As described above, even when the configuration of the multiplexing unit is changed, it is possible to deal with it by optimizing the connection between the output terminal of each basic module of the time slot conversion unit 51 and each channel ch1 'to ch8'. The same applies to the 4-bit separation conversion circuit.

In general, the time slot conversion unit of the n-bit multiplex conversion circuit outputs n in accordance with the number of input channels N (N is an integer multiple of n).
This can be easily realized by providing N / n time slot conversion circuits (basic modules) compatible with bit multiplexing and optimizing the connection of the input / output terminals.

Further, in the conventional configuration, the multiplexing unit required the serial / parallel conversion circuit and the [nN: 1] parallel / serial conversion circuit, but in the configuration of the present invention, at most the [N: 1] parallel / serial conversion circuit. That is enough.

Furthermore, as shown in FIG. 5, high-speed operation is possible [2:
1] By stacking a predetermined number of parallel / serial conversion circuits,
It is also possible to have a similar function.

Hereinafter, the time slot conversion circuit (basic module) in the 8-bit (1 byte) multiplex conversion circuit will be described in detail.

FIG. 6 is a diagram for explaining an 8-bit 8-bit multiplex conversion circuit of input. FIG. 6 (a) shows the overall structure,
FIG. 6 (b) shows time series data input / output to / from the time slot conversion circuit, and FIG. 6 (c) shows time series data of an 8-bit multiplexed signal.

The time slot conversion circuit 61 shown here is a basic module of an 8-bit multiplex conversion circuit, and its function is the same as that of the time slot conversion circuit 21 of the 4-bit input 4-channel multiplex conversion circuit shown in FIG. To be done.

Time series data of each channel ch1 'to ch8' (Fig. 6 (b)) output from each output terminal of the time slot conversion circuit 61 is 8: 1 in the [8: 1] parallel / serial conversion circuit 63. By performing the parallel / serial conversion process, the time series data (8-bit multiplexed signal) shown in FIG. 6C can be converted.

FIG. 7 is a block diagram showing the configuration of an embodiment of the time slot conversion circuit 61 corresponding to 8-bit multiplexing.

In the figure, the time series data of the input channel ch1 is input is 8 branches to D flip-flop 71 _{11-71 18} respectively. The time series data of the input channels ch2 to ch8 are delay circuits 73 _{2 to} 7 7 each of which delays 1 bit to 7 bits.
D flip-flops, each of which is branched into 8 via 3 ₈
71 _{21 to} 71 ₂₈ , ... 71 _{81 to} 71 ₈₈ are input.

The outputs of the first D flip-flops 71 ₁₁ , 71 ₂₁ , ..., 71 ₈₁ of the D flip-flop group corresponding to each channel are
Input to the OR circuit 75 ₁ . The outputs of the second D flip-flops 71 ₁₂ , 71 ₂₂ , ... 71 ₈₂ are OR circuits 75 ₂
To the eighth D flip-flop 71 and so on.
The outputs of ₁₈ , 71 ₂₈ , ... 71 ₈₈ are input to the OR circuit 75 ₈ .

Output data of the OR circuit 75 ₁ to 75 _7, via a delay circuit 77 ₁ to 77 ₇ to give each 7-bit to 1-bit delay, are respectively outputted to the channel ch1'~ch7 '. The output data of the logical sum circuit 75 ₈ is output to the channel ch8 '.

The control signal generation circuit 79 outputs control signals (clocks) that are sequentially shifted according to the input of the reference clock clk.

The control signals are D flip-flops 71 ₁₁ , 71 ₂₈ , ... 71 ₈₂
, And the reset terminal R of the D flip-flops 71 ₁₈ , 71 ₂₇ , ... 71 ₈₁ which latches the data at the immediately preceding clock.

The control signals are D flip-flops 71 ₁₂ , 71 ₂₁ , ... 71 ₈₃
, And the reset terminal R of the D flip-flops 71 ₁₁ , 71 ₂₈ , ... 71 ₈₂ for latching data with the control signal.

Similarly, the control signal is the D flip-flop 71 ₁₈ ,
71 ₂₇ , ... 71 ₈₁ D flip-flop for latching data with the clock terminal C and control signal 71 ₁₇ , 71 ₂₆ , ... 71 ₈₈
Connected to the reset terminal R of.

Here, the operation of the time slot conversion circuit 61 used in the 8-bit multiplex conversion circuit will be described with reference to FIGS. 7 and 8.

Time-series data (Figure 8 (a)) of each input channel ch1~ch8 through delay circuit 73 _{2-73 8,} respectively 0-7
A bit delay is given (Fig. 8 (b)).

The control signals are D flip-flops 71 ₁₁ , 71 ₂₈ , ... 71 ₈₂
The time series data 1-1 of the input channel ch1 is output to the OR circuit 75 ₁ by latching each time series data in the. Similarly, the control signal is the D flip-flop.
71 _18, 71 _27, ... 71 by latches each time series data _81, series data 8-1 is output when the OR circuit 75 _1, time-series data 7-2 to the OR circuit 75 ₂ There is output and output time series data 1-8 to the OR circuit 75 ₈ in the same manner.

That is, 1 of the time series data of each input channel ch1 to ch8
Bits (1-1, 2-1, ..., 8-1) are sequentially output from the OR circuit 75 ₁ . Similarly, for each input channel ch1 to ch8
Bit of the time series data of (1-k, 2-k, ..., 8-k)
Are sequentially output from the OR circuit 75k with a delay of K-1 bits (FIG. 8 (c)).

Time series data output from the OR circuit 75 ₁ to 75 ₈ (Figure 8 (c), the phase by through each delay circuit 77 ₁ to 77 _7, given each 7-0 bit delay Time series data (ch
1'-ch8 ') can be completed (Fig. 8 (d)).

The time slot conversion circuit (basic module) required for the n-bit demultiplexing / conversion circuit of the present invention can be realized by the above-described structure. However, the circuit structure shown in FIG. 7 and that shown in FIG. The conversion procedure is not limited to the above.

Finally, a schematic block diagram of an 8-bit multiplex conversion circuit and an 8-bit separation conversion circuit with 64 input channels is shown in
Shown in the figure.

In FIG. 9, the time slot conversion unit 91 of the 8-bit multiplex conversion circuit uses the time slot conversion circuit 61 shown in FIG. 6 (b) and FIG. 7 as a basic module.
This is a configuration using individual pieces (modules # 1 to # 8). Also,
The multiplexer 93 includes nine [8: 1] parallel / serial conversion circuits 93 ₁
93 ₉ to configure a two-stage.

Therefore, the time slot conversion unit 91 uses the input terminals in1 to in8 and the input channels ch1 to c of each module shown in Table 4.
Correspondence with h64 and output terminal out1 of each module
~ Out8 and channel ch1 '~ ch6 after time slot conversion
Input 6 by connecting based on the correspondence with 4 '
It is possible to perform 4-bit 8-bit multiplex conversion.

Also, 8-bit separation conversion circuit of the separation unit 95, nine [1: 8] S / P conversion circuit 95 ₁ to 95 ₉ constitute two stages, similar to time slot conversion unit 91 time-slot converter unit By configuring 97, an 8-bit separation conversion circuit can be similarly realized.

〔The invention's effect〕

As described above, according to the present invention, by providing the time slot conversion circuit, even if the number of multiplexed bits or the number of input channels is significantly changed, the high speed operation can be performed according to the speed of the multiplexing unit. You can

In addition, the configuration of the control circuit that controls each unit can be simplified.

Furthermore, the number of input channels or the multiplexing unit (separation unit)
When the number of stages of is changed, a time slot conversion circuit (basic module) corresponding to the number of multiplexed bits is added,
Further, by optimizing the input / output terminal and the channel, it is possible to easily and flexibly correspond.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention. FIG. 2 is a diagram for explaining a 4-bit multiple conversion circuit with four input channels. FIG. 3 is a diagram for explaining a 4-bit multiple conversion circuit with 8 input channels. FIG. 4 is a diagram for explaining a 4-bit multiple conversion circuit with 16 input channels. FIG. 5 is a diagram for explaining another configuration example of a 4-bit multiple conversion circuit with 8 input channels. FIG. 6 is a diagram for explaining an 8-bit input 8-channel multiplex conversion circuit. FIG. 7: A block diagram showing the configuration of an embodiment of a time slot conversion circuit compatible with 8-bit multiplexing. FIG. 8 is a diagram for explaining the operation of the time slot conversion circuit. FIG. 9 is a block diagram showing an example of the configuration of an input 64-channel 8-bit multiplex conversion circuit. FIG. 10 is a diagram for explaining an input N-channel n-bit multiplex conversion circuit when it is realized by a single-stage parallel / serial conversion circuit. FIG. 11 is a diagram for explaining an input N-channel n-bit multiplex conversion circuit when it is realized by a plurality of stages of parallel / serial conversion circuits. 21 …… Time slot conversion circuit 31, 41, 51, 61 …… Time slot conversion unit 23 …… [4: 1] Parallel / serial conversion circuit (multiplexing unit) 33, 43, 53, 63, …… [8 : 1] Parallel / serial conversion circuit (multiplexing unit) 71 …… D flip-flop 73 …… Delay circuit 75 …… OR circuit 77 …… Delay circuit 91, 97 …… Time slot conversion circuit 93 …… Multiplexing unit 95 …… Separation unit 101 …… [1: n] Serial / parallel conversion circuit 103 …… [nN: 1] Parallel / serial conversion circuit 111, 112, 113 …… n-bit multiple conversion unit 115 …… [1: mn] serial / parallel conversion circuit 117 …… [nN: 1] parallel / series conversion circuit

Claims (3)

[Claims] 1. An n-bit multiplex conversion circuit for multiplexing input signals of n channels (n is a positive integer) every n bits, wherein each i-th (i ≦ n) bit of each input signal of n channels Is performed as an output signal of the i-th channel in n-bit units, and a time-slot conversion circuit for converting into a new n-channel signal sequence and this new n-channel signal are input, and n: 1 An n-bit multiplex conversion circuit, comprising: 2. An n-bit multiplex conversion circuit for multiplexing an input signal of N (N is an integer multiple of n) channels every n bits, wherein the time slot conversion circuit according to claim (1) is used. A time slot conversion unit which has N / n number of times, each time slot conversion circuit corresponds to a predetermined channel, each time slot is exchanged in units of n bits, and is converted into a new N channel signal sequence, An n-bit multiplex conversion circuit comprising: a multiplexer for inputting a new N-channel signal and performing N-to-1 multiplexing. 3. An n-bit separation conversion circuit for separating an input signal of N (N is an integer multiple of n) channels for every n bits, and a separation unit for performing a 1-to-N separation. A time slot conversion unit that has N / n time slot conversion circuits described in the item (1), performs reverse conversion by switching inputs and outputs, and converts the original N channel signal sequence. An n-bit separation conversion circuit characterized by the above.