JPH0778724B2 - Divider - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subtraction shift type divider based on a cell array method for performing division of two's complement representation numbers or unsigned numbers.

2. Description of the Related Art Conventional dividers include, for example, Takagi, Yasuura, and Yajima:
"High-speed divider for VLSI using redundant binary representation", IEICE Transactions (D), J67-D, No4, pp450-457 (SHO 59-0)
4), JP-A-63-49836.

In the following description, redundant binary is [] _SD2 , unsigned 2
Enclose the notation in [] ₂ and the two's complement number in [] _2C . Each digit of a numerical value represented by an uppercase letter is represented by a lowercase letter and a subscript number such as X = [x _0. x ₁ x ₂ ... x _n ] _SD2 . The explanation of the symbols used in the following description is given in Table 1.

FIG. 5 shows a block diagram of a conventional divider. Therefore, in the example of the figure, n = 6 is set in particular. In the figure, 1 is a divisor converter for converting a positive or negative divisor of a normalized 2's complement representation into a redundant binary number, and 2 is a divisor converter for converting a positive or negative 2's complement dividend into a redundant binary number. The dividend converter 3, 3 is a redundant binary adder / subtractor that performs addition or subtraction between redundant binary numbers, and 4 is a function that determines whether addition or subtraction should be performed in the redundant binary adder / subtractor of the corresponding stage. A quotient determination circuit for determining the digit of the quotient corresponding to the stage, 5 is a quotient converter for converting the quotient of the redundant binary representation into a two's complement representation number, and 6 is the operation result of the redundant binary adder / subtractor at the final stage 2 is a remainder converter for converting a redundant binary number that is a number into a two's complement number. In the drawings below, common numbers are used for the same items.

The principle and operation of the conventional divider configured as above will be described below. An unsigned binary representation of the dividend X and the divisor Y is provided to the conventional divider. Since the conventional divider is configured for processing the mantissa part of a floating point number, it is assumed that X and Y have been normalized in advance. First, the dividend X and the divisor Y are converted into redundant binary numbers R ⁽⁰⁾ and D by the dividend converter 2 and the divisor converter 1, respectively.

Here, the conversion rule from the unsigned binary representation to the redundant binary representation is shown below.

When _{[X] 2 = [0.x 1} x 2 ... x n] 2 [X] SD2 ← [X] 2 < conversion rule to the redundant binary representation from the unsigned binary representation>, [X] _SD2 = [0.x ₁ x ₂ ... x _n ] _SD2 Here, <-represents the conversion of the number expression. That is, the unsigned binary representation number is a redundant binary representation number as a value.

Next, R ⁽⁰⁾ is input as the augend for the redundant binary adder / subtractor 3 in the first stage, and D is the redundant 2 of each stage as the operation number (addend or subtraction) for the redundant binary adder / subtractor as shown in FIG. It is supplied all at once to the adder / subtractor 3. Subtraction is performed in the redundant binary adder / subtractor 3 in the first stage. Redundancy after the first stage 2
In the addition / subtraction adder / subtractor 3, either addition or subtraction is performed according to the judgment of the quotient determination circuit 4 corresponding to that stage. The quotient determining circuit 4 looks at the upper 3 digits of the operation result of the redundant binary adder / subtractor 3 in the preceding stage and determines the value of the operation and quotient digit of that stage. The quotient corresponding to all n stages and the redundancy of the (n + 1) th stage 2
When the operation result of the adder-subtractor 3 is obtained, the quotient and the remainder of the redundant binary representation are obtained as the calculation result. The quotient of the redundant binary representation is converted by the quotient converter 5 and the remainder is converted by the remainder converter 6 into a two's complement representation number.

Here, the conversion rule from the redundant binary representation to the two's complement representation is shown below.

<Conversion Rule from Redundant Binary Representation to 2's Complement Representation> [X] _SD2 = [0.x ₁ x ₂ ... x _n ] _SD2 [X] _2C ← [X] If _SD2 , the redundant binary representation becomes 2 2 is the conversion of to
This can be done by subtracting two unsigned binary numbers. Looking at each digit of the redundant binary number, only the ones are collected and the other digits are set to 0. From the binary number, only the ones are selected and the other digits are set to 0.
It can be converted into a two's complement number by reducing the base number. This conversion can be implemented using a two's complement adder with an input selector at each digit.

The contents of the processing described above and the calculation and quotient decision algorithm in the quotient decision circuit are summarized as follows.

<Conventional division algorithm> Step 1 [R ⁽⁰⁾ ] _SD2 ← [X] ₂ [D] _SD2 ← [Y] ₂ Step 2 [q ₀ ] _SD2 : = 1 [R ⁽¹⁾ ] _SD2 : = [ R ⁽⁰⁾ ] _SD2- [D] _SD2 Step 3 Step 4 Q: = [q _0. q ₁ q ₂ ... q _n ] _SD2 [Z] ₂ ← [Q] _SD2 [R] ₂ ← [R ^{(n + 1)} ] _{SD2 As} shown in Table 2, The range of input values for the divider is limited. Therefore, the range of the value of quotient Z is also 1/2 ≦ Z <2. If the given X and Y are arbitrary integers, then X and Y must be absolute and normalized.

Addition and subtraction of redundant binary numbers are defined as shown in Tables 3 and 4, respectively. The conventional divider has the following advantages because the value that can be taken by the number of operations (addition or subtraction) is limited to non-negative.

(1) The calculation rule becomes simple.

(2) The transmission digit propagates only at most one digit.

Here, the transmission digit ti is defined as follows.

In addition or subtraction of redundant binary numbers U and V, U and V
Let ui and vi be the i-th digits of u _i ± v _i = 2t _i-1 + w _i s _i = w _i + t _i u _i , v _i , s _i , t _i , w _i { 1,0,1} s _i : Sum (difference) digit t _i : Transfer digit w _i : Intermediate sum (difference) That is, the transfer digit has the same meaning as carry or borrow in addition and subtraction of two's complement representation .

In addition and subtraction of redundant general binary numbers, a transmission digit propagates up to two digits, but if the operation number (addend or subtraction) is limited to non-negative as described in (2), the transmission digit propagates at most one digit. . Therefore, the above-mentioned addition and subtraction does not have carry propagation, and can be performed in a fixed time regardless of the number of digits of the operation number.

As described above, the conventional divider can divide only normalized unsigned binary. That is, the dividend X,
The range of values that the divisor Y can take is limited as shown in Table 2.

The range of this value matches the condition of the mantissa part of the floating-point display number, and in practice, division under such restrictions is Arithmetic was designed specifically for the division of the mantissa parts of floating-point display numbers.

However, in the above configuration, for example, when two complemented integer dividends X and integer divisors Y are given, X ÷ Y = Z, remainder R where quotient Z, The remainder R is an integer. The fractional part of the quotient Z is truncated. The sign of the remainder R does not matter.

Cannot be applied to integer division. When the conventional divider is expanded to perform integer division, absolute value and normalization of dividend X and divisor Y before division, sign of quotient Z after division, complement of decimal point position and remainder R It is necessary to correct the decimal point position of. As a result, the hardware amount and the calculation time of the entire divider increase.

In view of the above point, the present invention has an object to provide a divider that can also perform division of integers including division of normalized numbers by a divider using a cell array method.

Means for Solving the Problems In order to solve the above problems, the inventions according to claims 1 and 3 include a dividend converter for converting a dividend of a positive or negative two's complement representation into a redundant binary number, and a normalized dividend converter. And a divisor converter that converts a positive or negative divisor in 2's complement notation to a redundant binary number, and takes three values {−1,0,1} for the MSB of the addend or subtraction represented in redundant binary. The value that can be taken by each digit other than the MSB of the addend or the subtraction is limited to binary {0,1} and the redundant binary number output from the dividend converter and the output from the divisor converter A redundant binary adder / subtractor at the first stage that performs addition / subtraction with a redundant binary number, and allows addition of three values {−1,0,1} to the MSB of the addend or subtraction expressed in redundant binary. The possible values of each digit other than the MSB of a number or a divisor are limited to binary {0,1} and the divisor conversion is performed. The redundant binary adder / subtractor for performing addition / subtraction between the redundant binary number output from the above and the redundant binary number obtained by shifting the output from the preceding redundant binary adder / subtractor by 1 bit to the left is the redundant binary adder / subtractor of the first stage. Based on the redundant binary adder / subtractor array stacked n stages later and the operation result of the preceding redundant binary adder / subtractor and the sign of the divisor, whether the addition or subtraction operation should be performed in the redundant binary adder / subtractor of the next stage is performed. A quotient determining circuit for determining and determining the quotient digit corresponding to the stage, and a quotient in a redundant binary representation in which each digit of the quotient determined by the quotient determining circuit in each stage is combined into a two's complement representation. A quotient converter for converting into a quotient converter, and a residue converter for converting a redundant binary number, which is the operation result of the redundant binary adder / subtractor at the final stage, into a two's complement representation number. -1 if positive and negative instep , 0 if 0, positive if 1 is the value of the corresponding quotient digit, if the divisor is negative, if the instep A is 0, 0 if positive, -1 if positive, the corresponding quotient digit value It is a divider characterized by performing.

Further, the inventions according to claims 2 and 4 include a one's complement calculator which takes the one's complement of the divisor when the normalized divisor of the two's complement expression is negative and allows the divisor value to pass through when the divisor is not negative; , A dividend converter for converting a positive or negative dividend of a complement expression of the above into a redundant binary number, a divisor converter for converting an output from the one's complement unit into a redundant binary number, and a redundant binary-added sum or The possible values of all digits of the divisor are limited to binary {0,1}, and the redundant binary number output from the dividend converter and 1 output from the divisor converter are added when the divisor is negative. The redundant binary adder / subtractor at the first stage that performs addition and subtraction with the redundant binary number that has been created, and the possible values of all digits of the redundant binary-added addend or subtraction are limited to binary {0,1} only. With the redundant binary, the output from the preceding redundant binary adder / subtractor is shifted to the left by 1 bit. And a redundant binary adder / subtractor for performing addition / subtraction between the redundant binary number output from the divisor converter and added with 1 when the divisor is negative, are stacked n stages after the first stage redundant binary adder / subtractor. Based on the redundant binary adder / subtractor array and the operation result of the preceding redundant binary adder / subtractor, it is determined whether addition or subtraction should be performed in the redundant binary adder / subtractor of the next stage, and the quotient corresponding to that stage is determined. Of the quotient determined by the quotient determining circuit in each stage is combined into a redundant binary representation quotient and the sign of the quotient is inverted when the divisor is negative. And a quotient converter for converting the quotient of the redundant binary representation into a two's complement representation number, and a residue conversion for converting the redundant binary number which is the operation result of the redundant binary adder / subtractor at the final stage into the two's complement representation number. In the quotient decision circuit, If the negative -
The divider is characterized by making a determination that the value of the digit of the quotient is 0 if 1 or 0 and 1 if positive.

With the above-mentioned means, the invention according to claim 1 is configured such that the redundant binary adder / subtractor is used as a redundant binary representation of an addend or a subtraction MS.
Allowed to take three values {−1,0,1} for B, and improved so that the possible values of each digit other than MSB of addend or subtraction are limited to binary {0,1} And in the quotient decision circuit, when the divisor is positive, if the instep is negative, it is -1, if 0, 0,
If it is positive, 1 is taken as the value of the corresponding quotient digit, and when the divisor is negative, it is determined that if the instep A is negative, 0 is 0, if positive, -1 is the corresponding quotient digit value. It is possible to allow any two's complement represented integer for the dividend and negative numbers for the divisor.

According to the invention described in claim 3, by further providing a normalizer, a quotient barrel shifter and a remainder barrel shifter, in addition to the invention described in claim 1, an integer represented by any two's complement is allowed for the divisor. Is possible.

According to the second aspect of the present invention, the value that can be taken by the one's complementer and all the digits of the addend or the subtraction represented by the redundant binary is represented by the binary value {0,
Redundant 2 which is limited to only 1} and which performs addition and subtraction between the redundant binary number output from the dividend converter and the redundant binary number output from the divisor converter and added with 1 when the divisor is negative. By providing an adder-subtractor and a quotient converter that inverts the sign of the quotient represented in the redundant binary form when the divisor is negative, any two's complement represented integer is allowed for the dividend, and the divisor is On the other hand, it is possible to allow negative numbers.

The invention according to claim 4 further includes a normalizer, a quotient barrel shifter, and a remainder barrel shifter, thereby allowing an integer represented by any two's complement to the divisor in addition to the invention according to claim 2. Is possible.

Examples Hereinafter, dividers according to four examples of the present invention will be described with reference to the drawings.

The first embodiment is a configuration example of the divider according to the first aspect of the present invention. FIG. 1 is a block diagram of the divider when n = 6 in the embodiment. In the figure, 1 is a divisor converter for converting a positive or negative divisor of a normalized 2's complement representation into a redundant binary number, and 2 is a dividend for converting a dividend of a positive or negative 2's complement representation into a redundant binary number. A converter 3 is a redundant binary adder / subtractor for performing addition or subtraction between redundant binary codes, and a reference numeral 4 is for determining whether addition or subtraction should be performed in the redundant binary adder / subtractor 3 of the corresponding stage. A quotient determination circuit for determining the quotient digit corresponding to the stage,
5 is a quotient converter for converting the quotient of the redundant binary representation into 2's complement representation, and 6 is a remainder for converting the redundant binary number which is the operation result of the redundant binary adder / subtractor 3 in the final stage into the 2's complement representation number. It is a converter.

The principle and operation of the divider of this embodiment configured as above will be described below.

It is assumed that the dividend X and the divisor Y in the two's complement representation are given to the divider of this embodiment, and the divisor Y is normalized in advance. First, dividend X and divisor Y are redundant binary numbers R ⁽⁰⁾ and D by dividend converter 2 and divisor converter 1, respectively.
Is converted to.

Here, the conversion rule from 2's complement representation to redundant binary representation is shown below.

<Conversion rule from 2's complement representation to redundant binary representation> [X] _2C = [x _S. x ₁ x ₂ ... x _n ] _2C [X] _SD2 ← [X] _2C , then [X] _SD2 = [ _S. x ₁ x ₂ ... x _n ] _SD2 Here, ← represents a conversion of a numerical expression, and _S = 1 if x _S = 0 = 0 if x _S = 1. That is, the conversion from the two's complement representation to the redundant binary representation only needs to invert the sign of the sign bit (MSB).

Next, R ⁽⁰⁾ is input as an operand to the redundant binary adder / subtractor at the first stage (augend or subtraction), and D is an operand to the redundant binary adder / subtractor (addend or addend) as shown in FIG. It is simultaneously supplied to the redundant binary adder / subtractor 3 of each stage as a subtraction). In the redundant binary adder / subtractor 3 of each stage, either addition or subtraction is performed according to the judgment of the quotient determination circuit 4 corresponding to that stage.

In the redundant binary adder / subtractor 3 in this embodiment, the calculation rule is extended only to the redundant binary adder / subtractor cell of the MSB in order to deal with the negative divisor. The calculation rules for the redundant binary adder / subtractor cells of the MSB are listed in Tables 5 and 6. In this calculation rule, the regularity of the transmission digit is disturbed, but since this redundant binary adder / subtractor cell is in the MSB, its carry cannot be propagated higher.

The quotient determining circuit 4 determines the value of the digit of the operation and quotient at that stage by looking at the upper 3 digits of the operation result of the redundant binary adder / subtractor 3 at the preceding stage and the sign of the divisor Y. The quotient corresponding to all n stages and the (n
When the operation result of the +1) stage redundant binary adder / subtractor 3 is obtained, the quotient and the remainder of the redundant binary representation are obtained as the calculation result. The quotient of the redundant binary representation is converted by the quotient converter 5 and the remainder is converted by the remainder converter 6 into a two's complement representation number.

The contents of the processing described above and the calculation and quotient decision algorithm in the quotient decision circuit are summarized as follows.

<Division algorithm of the first embodiment> Step 1 [R ⁽⁰⁾ ] _SD2 ← [X] _2C [D] _SD2 ← [Y] _2C Step 2 Step 3 Step 4 Q: = [q _0. q ₁ q ₂ … q _n ] _SD2 [Z] _2C ← [Q] _SD2 [R] _2C ← [R ^{(n + 1)} ] _SD2 The second embodiment is a configuration example of the divider according to the second aspect of the present invention. FIG. 2 is a block diagram of the divider when n = 6 in the embodiment. In the figure, 1 is a divisor converter for converting a positive or negative divisor of a normalized 2's complement representation into a redundant binary number, and 2 is a dividend for converting a dividend of a positive or negative 2's complement representation into a redundant binary number. A converter 3, a redundant binary adder / subtractor for performing addition or subtraction between redundant binary numbers, and 4 determines whether addition or subtraction should be performed in the redundant binary adder / subtractor of the corresponding stage, and the stage Quotient decision circuit for deciding the digit of the quotient corresponding to
Is a quotient converter for correcting the sign of the quotient obtained by the quotient determination circuit 4 and for converting the quotient of the redundant binary representation into a two's complement representation number; 6 is the operation of the redundant binary adder / subtractor at the final stage It is a remainder converter for converting the resulting redundant binary number into a two's complement representation number.

The principle and operation of the divider of this embodiment configured as above will be described below.

It is assumed that the dividend X and the divisor Y in the two's complement representation are given to the divider of this embodiment, and the divisor Y is normalized in advance. First, the divisor Y is converted to a one's complement of Y if Y is negative by a one's complement calculator. Dividend X and 1
The outputs of the complement units of the above are converted into redundant binary numbers R ⁽⁰⁾ and D by the dividend converter 2 and the divisor converter 1, respectively. Next, R ⁽⁰⁾ is input as an operand to the redundant binary adder / subtractor at the first stage (augend or subtraction), and D is an operand to the redundant binary adder / subtractor (addend or addend) as shown in FIG. Reduction)
Are simultaneously supplied to the redundant binary adder / subtractor 3 of each stage.
In the redundant binary adder / subtractor 3 of each stage, either addition or subtraction is performed according to the judgment of the quotient determination circuit 4 corresponding to that stage.

Here, if the divisor Y is negative, the divisor Y is already 1
Since it has been converted into the complement of, the correction of adding 1 to D is performed in order to convert this into the complement of 2 of the divisor Y. This correction is simultaneously performed when the redundant binary adder / subtractor 3 in each stage performs addition / subtraction. As shown in Tables 9 and 10, this correction is realized by modifying the calculation rule in the LSB of the redundant binary adder / subtractor 3 in each stage. Like this LSB
Even if the calculation rule of is modified, carry does not occur from the lower part of the LSB (transmission digit), so carry propagation from the LSB to the upper part does not occur.

The quotient determining circuit 4 looks at the upper 3 digits of the operation result of the redundant binary adder / subtractor 3 in the preceding stage and determines the value of the operation and quotient digit of that stage. The quotient corresponding to all n stages and the redundancy of the (n + 1) th stage 2
When the operation result of the adder-subtractor 3 is obtained, the quotient and the remainder of the redundant binary representation are obtained as the calculation result. The quotient of the redundant binary representation is converted by the quotient converter 5 and the remainder is converted by the remainder converter 6 into a two's complement representation number. In this embodiment, the quotient converter 5 also corrects the quotient code.

This is because the absolute value of the divisor is taken first, so that the sign of the quotient is inverted when the divisor is negative. Therefore, if the divisor is negative, the sign of the quotient may be inverted. This is a subtraction performed when the quotient of the redundant binary representation is converted into the number of 2's complement representation in the quotient converter 5, and can be realized by exchanging the subtracted numbers. Table 12 shows the quotient conversion algorithm in the quotient converter 5.

The contents of the processing described above and the calculation and quotient decision algorithm in the quotient decision circuit are summarized as follows.

<Division algorithm of the second embodiment> Step 1 [R ⁽⁰⁾ ] _SD2 ← [X] _2C if Y> 0then [D] _SD2 ← [Y] _2C else [D] _SD2 ← [] _2C Step 2 Step 3 Step 4 Q: = [q _0. q ₁ q ₂ … q _n ] _SD2 if Y> 0then [Z] _2C ← [Q] _SD2 else [Z] _2C ← [−Q] _SD2 [R] _2C ← [R ^{( n + 1)} ] _SD2 Here, represents the one's complement of Y, that is, the numerical value obtained by inverting the bit of each digit. Table 11 shows the modified Step 2
Table 12 shows an operation table of the quotient converter of the embodiment.

The sign of the remainder of the operation result does not matter in the first and second embodiments because it is often influenced by the standard of the entire operation processing device including the divider.

As described above, according to the first and second embodiments, the dividend is 2
It is possible to directly calculate the complement expression number of. Further, since it is possible to calculate a negative number for the divisor, the effect of only normalizing the divisor before it is input to the divider of the present embodiment is provided as preprocessing for performing the division of the present embodiment. Have. In the divider of this embodiment, since the bit length of the dividend is 2n, a double precision division such as (2n bits) ÷ (n bits) = (n bits) remainder (n bits) is performed in integer division. Will be there.

Single-precision division (n bits) / (n bits) = (n bits) When performing the remainder (n bits), the n-bit dividend is simply sign-extended to 2n bits.

The third embodiment is a configuration example of the divider according to the third aspect of the present invention.

FIG. 3 is a block diagram of the divider in the embodiment. In the figure, 8 is a divisor normalizer, 9 is the divider of the first embodiment, 10 is a quotient barrel shifter, and 11 is a remainder barrel shifter. The normalizer 8 is, for example, a priority encoder that searches rightward from the right adjacent bit of the MSB of the divisor to find the position of a bit different from the MSB first, and a barrel shifter that shifts the divisor to the left by the number of bits counted by the priority encoder. It is composed of

The principle of the divider of the third embodiment is the same as that of the first embodiment. The operation of the third embodiment will be described below.

(1) Normalize the divisor Y.

(2) The division according to the first embodiment is executed to obtain the temporary quotient Z and the temporary remainder R.

(3) Move to the position where the decimal point of the obtained quotient Z is correct.
The shift amount of the quotient of the quotient, that is, the shift number is obtained from the shift number when the divisor Y is normalized.

(4) Move the decimal point of the obtained remainder R to the correct position. The number of shifts at this time is the same as that of (3).

As described above, the divisor is normalized as the pre-processing of the division by the divider of the first embodiment, and the quotient and the remainder are corrected as the post-processing to allow the arbitrary two's complement display number as the divisor. FIG. 6 is a flow chart for explaining the operation flow of the division step in this embodiment.

The fourth embodiment is a configuration example of the divider according to the fourth aspect of the present invention. FIG. 4 is a block diagram of the divider in the same embodiment. In the figure, 7 is a one's complementer, 8
Is a normalizer, 10 is a quotient barrel shifter, 11 is a remainder barrel shifter, and 12 is a divider obtained by removing the 1's complement unit from the divider of the second embodiment. The normalizer 8 is, for example, a priority encoder that searches rightward from the right adjacent bit of the MSB of the divisor to find the position of a bit different from the MSB first, and a barrel shifter that shifts the divisor to the left by the number of bits counted by the priority encoder. It is composed of

The principle of the divider of the fourth embodiment is the same as that of the second embodiment. The operation of the fourth embodiment will be described below.

(1) If the divisor Y is negative, take the 1's complement of Y.

(2) Normalize the divisor Y.

(3) Perform division according to the second embodiment (provided that 1 of Y
, Except that the temporary quotient Z and the temporary remainder R are obtained.

(4) Move the decimal point of the obtained quotient Z to the correct position. The shift amount of the quotient of the quotient, that is, the shift number is obtained from the shift number when the divisor Y is normalized. At the same time, when the divisor Y is negative, the sign of the quotient Z is inverted.

(5) Move the decimal point of the obtained remainder R to the correct position. The number of shifts at this time is the same as that of (4).

By correcting the divisor before and after the division by the divider of the second embodiment as described above, any two's complement display number is allowed as the divisor. FIG. 7 is a flow chart for explaining the operation flow of the division step in this embodiment.

As described above, by the divider of the third and fourth embodiments, the unsigned binary number, the two's complement number, the normalized number and the denormalized number, the double-precision integer and the single-precision integer are represented. Division is also possible. When the divider of the third and fourth embodiments is incorporated, for example, as a part of the arithmetic processing unit, it can function as both an integer divider and a mantissa divider of a floating point arithmetic unit. Therefore, it is possible to speed up both integer division and floating-point division without increasing the amount of hardware. In the case of this implementation method, the divisor input to the divider of the first and second embodiments can be selected from either the normalizer or the already-normalized mantissa so that the mantissa does not pass through the normalizer. By doing The execution time of floating point division can be further speeded up.

The effects of expanding the range of the number of operations that can be handled by the four examples in Table 13 are summarized.

EFFECTS OF THE INVENTION As described above, according to the present invention, by limiting the possible values of some or all digits of the redundant binary number supplied to the redundant binary adder / subtractor to binary {0,1}, It is possible to directly divide two's complement representation numbers. Therefore, integers (fixed point numbers) can be directly divided. In the past, since only normalized positive numbers could be divided, the mis-divider could only be applied to floating point division, but the divider of the present invention divides both integer (fixed point number) and floating point numbers. Applicable to

[Brief description of drawings]

FIG. 1 is a block diagram of a divider according to the first embodiment of the present invention, FIG. 2 is a block diagram of a divider according to the second embodiment of the present invention, and FIG. 3 is a third embodiment of the present invention. 4 is a block diagram of a divider in FIG. 4, FIG. 4 is a block diagram of a divider in a fourth embodiment of the present invention, FIG. 5 is a block diagram of a conventional divider, and FIG. 6 is a third embodiment of the present invention. 7 is a flowchart showing the operation flow of the division step in FIG. 7, and FIG. 7 is a flowchart showing the operation flow of the division step in the fourth embodiment of the present invention. 1 ... Divisor converter, 2 ... Dividend converter, 3 ... Redundancy 2
Addition / subtraction device, 4 ... Quotation determination circuit, 5 ... Quotation converter, 6
... Residue converter, 7 ... 1's complementer, 8 ... normalizer,
9 ... Divider of the first embodiment, 10 ... Quartz barrel shifter,
11 ... remainder barrel shifter, 12 ... divider obtained by removing the 1's complement unit from the divider of the second embodiment

Claims (4)

[Claims] 1. A dividend of a positive or negative two's complement representation, where n is a bit length of the divisor, has a radix of 2 and each digit is {−1,0,1}.
A dividend convertor for converting into a signed digit number with redundancy (hereinafter referred to as redundant binary number) represented by any of the elements, and the absolute value is stored between 1/2 and 1 (hereinafter For a divisor converter that converts a positive or negative divisor in 2's complement notation into a redundant binary number, and the most significant bit (abbreviated as MSB below) of the addend or subtraction in redundant binary representation. Allowed to take three values {−1,0,1} and the binary value of the possible value of each digit other than the MSB of the addend or subtraction is {0,1}.
And a redundant binary adder / subtractor at the first stage for performing addition / subtraction between the redundant binary number output from the dividend converter and the redundant binary number output from the divisor converter, and a redundant binary representation. Allows three values {−1,0,1} for the addend or subtraction MSB and limits the possible values of each digit other than the addend or subtraction MSB to only binary {0,1} A redundant binary adder / subtractor for performing addition / subtraction between the redundant binary number output from the divisor converter and the redundant binary number obtained by shifting the output from the preceding redundant binary adder / subtractor by 1 bit to the left is a redundant binary adder / subtractor at the first stage. Redundant 2 stacked n stages after the binary adder / subtractor
The addition / subtraction operation is performed by the redundant addition / subtraction device array, the value of the dividend or the operation result of the redundant binary addition / subtraction device in the preceding stage and the sign of the divisor to determine whether addition or subtraction should be performed in the corresponding redundant binary addition / subtraction device. Also, a quotient determining circuit that determines the quotient digit corresponding to the stage and a redundancy 2 that combines each digit of the quotient determined by the quotient determining circuit in each stage
A quotient converter for converting a quotient of a binary expression into a two's complement expression number, and a residue converter for converting a redundant binary number which is the operation result of the redundant binary adder / subtractor at the final stage into a two's complement expression number In the quotient determination circuit, when the divisor is positive, the redundant binary adder / subtractor at the first stage has the upper 3 bits of the dividend, and the redundant binary adder / subtractor after the first stage has the redundant binary adder / subtractor at the preceding stage. If the upper 3 bits (abbreviated as "A") of the operation result are negative, -1, if 0, 1 is taken as the value of the corresponding quotient digit. If the divisor is negative, if A is negative, then 1 0,
If positive, a divider that makes a decision that -1 is the value of the corresponding quotient digit. 2. A one-corrector for taking the one's complement of the divisor when the normalized divisor of the two's complement expression is negative and passing the divisor value through when it is not negative, and a positive or two-complement expression. A dividend converter for converting a negative dividend into a redundant binary number;
And a divisor converter for converting the output from the complementer of the above into a redundant binary number, limiting the possible values of all digits of the redundant binary representation of the addend or subtraction to binary {0,1} and A redundant binary adder / subtractor at the first stage for performing addition and subtraction between the redundant binary number output from the converter and the redundant binary number output from the divisor converter and further added to 1 when the divisor is negative; The possible values of all digits of the addend or the subtraction expressed in binary are limited to binary {0,1}, and the output from the redundant binary adder / subtractor at the preceding stage is shifted to the left by one bit and the redundant binary A redundant binary adder / subtractor for adding / subtracting to / from the redundant binary number output from the divisor converter and added with 1 when the divisor is negative is redundant 2 in which n stages are stacked after the redundant binary adder / subtractor at the first stage. Array of adder / subtractor and value of dividend or redundant binary add / subtract in the preceding stage A quotient determination circuit that determines which addition or subtraction operation should be performed in the redundant binary adder / subtractor of the corresponding stage and the quotient digit corresponding to that stage, and the quotient determination circuit in each stage. The respective digits of the quotient determined by the quotient determination circuit are combined into a quotient of redundant binary representation, and when the divisor is negative, the sign of this quotient is inverted and the quotient of redundant binary representation is converted into a two's complement representation. A quotient converter for converting and a residue converter for converting a redundant binary number, which is the operation result of the redundant binary adder / subtractor at the final stage, into a two's complement representation number. Then -1,
A divider which makes a determination that 0 is 0 if 0 and 1 is positive if the value is a digit of a corresponding quotient. 3. A normalizer for normalizing by shifting a divisor of a positive or negative two's complement representation to the left or right, inputting the value to the divisor converter, and counting the number of bits shifted at that time. , A quotient barrel shifter that shifts the output of the quotient converter by the number of shifts counted by the normalizer and in the direction opposite to the direction shifted by the normalizer, and the number of shifts counted by the normalizer. The divider according to claim 1, further comprising: a remainder barrel shifter that shifts the output of the remainder converter in the direction opposite to the direction shifted by the normalizer. 4. A normalizer for normalizing an output of a one's complementer by shifting it to the left or right, using the value as an input to a divisor converter and counting the number of bits shifted at that time, and the normalization. The shift number counted by the normalizer and the quotient barrel shifter for shifting the output of the quotient converter in the direction opposite to the direction shifted by the normalizer, and the shift number counted by the normalizer and the normal number. The divider according to claim 2, further comprising: a remainder barrel shifter that shifts an output of the remainder converter in a direction opposite to a direction shifted by the digitizer.