JPH0777227B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0777227B2 JPH0777227B2 JP61299483A JP29948386A JPH0777227B2 JP H0777227 B2 JPH0777227 B2 JP H0777227B2 JP 61299483 A JP61299483 A JP 61299483A JP 29948386 A JP29948386 A JP 29948386A JP H0777227 B2 JPH0777227 B2 JP H0777227B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor wiring
- semiconductor element
- lsi chip
- pulse heating
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、マイクロコンピュータやゲートアレク等の多
電極、狭ピッチのLSIチップの実装に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting of a multi-electrode, narrow-pitch LSI chip such as a microcomputer or a gate Alex.
従来の技術 従来の技術を第２図に参照して説明する。Conventional Technology Conventional technology will be described with reference to FIG.
まず第２図ａに示す用に、セラミック，ガラス等よりな
る配線基板11のAl,iTO,Cr−Au等よりなる導体配線12を
有した面に、紫外線硬化あるいは熱硬化等の接続樹脂13
を塗布する。次に第２図ｂのごとく、Au,Al,Cu等よりな
る突起電源15を有したLSIチップ14を突起電極15と導体
配線12が一致する様に配線基板11に加圧ツール16により
加圧する。次にLSIチップ14を加圧した状態で接続樹脂1
3を硬化し、第２図ｃに示す様に、LSIチップ14を配線基
板11に固着するとともに、LSIチップ14の突起電極15と
導体配線12を接触により電気的に接続したものである。
接続樹脂13の硬化は、紫外線硬化の場合は、LSIチップ1
4の周囲から紫外線を照射し硬化する。また熱硬化の場
合は常時加熱された加圧ツール16によりLSIチップ14を
加熱し、加熱硬化する。First, as shown in FIG. 2a, a connecting resin 13 such as ultraviolet curing or thermosetting is formed on the surface of the wiring substrate 11 made of ceramic, glass or the like having the conductor wiring 12 made of Al, iTO, Cr-Au or the like.
Apply. Next, as shown in FIG. 2B, the LSI chip 14 having the protruding power source 15 made of Au, Al, Cu or the like is pressed against the wiring board 11 by the pressing tool 16 so that the protruding electrode 15 and the conductor wiring 12 are aligned with each other. . Next, with the LSI chip 14 under pressure, connect resin 1
3 is hardened and the LSI chip 14 is fixed to the wiring board 11 as shown in FIG. 2C, and the protruding electrode 15 of the LSI chip 14 and the conductor wiring 12 are electrically connected by contact.
If the connection resin 13 is cured by UV, the LSI chip 1
It is hardened by irradiating ultraviolet rays from around 4. Further, in the case of heat curing, the LSI chip 14 is heated by the pressure tool 16 that is constantly heated to heat cure.
発明が解決しようとする問題点 前述した従来の技術では、接続樹脂の硬化方法として、
紫外線硬化あるいは、常時加熱された加圧ツールによる
加熱硬化を用いていることや、LSIチップの電極と配線
基板の導体配線との電気的な接続が接触のみにより行わ
れている為、次に示す問題点がある。Problems to be Solved by the Invention In the above-described conventional technique, as a method for curing the connection resin,
Since it uses UV curing or heat curing with a pressure tool that is constantly heated, and the electrical connection between the electrodes of the LSI chip and the conductor wiring of the wiring board is made only by contact, There is a problem.
（１） 紫外線硬化の場合において、配線基板にセラミ
ック等の不透明な基板を用いたとき、LSIチップと配線
基板間にある接続樹脂への紫外線のまわり込み量が少
く、硬化に長い時間を必要とし、コストの高いものとな
る。(1) In the case of ultraviolet curing, when an opaque substrate such as ceramic is used as the wiring substrate, the amount of ultraviolet rays that penetrate into the connection resin between the LSI chip and the wiring substrate is small, and it takes a long time to cure. , Costly.
（２） 上記加熱による加熱硬化の場合は、加熱硬化後
の加圧解除は、接続樹脂がやわらかい状態で行われる
為、LSIチップや配線基板の弾性回復力により、電気的
な接続不良をきたし歩留りが低下する。(2) In the case of heat curing by the above heating, the pressure release after heat curing is performed while the connection resin is in a soft state, so the elastic recovery force of the LSI chip or wiring board causes electrical connection failure and yield. Is reduced.
この問題を解決する方法とし、空冷等で強制的にツール
を冷却し後に加圧を解除する方法があるが、冷却に長い
時間を要する為、生産性が悪い。例えば、加圧時のツー
ル温度を250℃，加圧解除を50℃以下で行う場合１サイ
クルの所要時間は５分〜10分と非常に長い時間である。As a method of solving this problem, there is a method of forcibly cooling the tool by air cooling or the like and then releasing the pressure, but it takes a long time for cooling, and thus the productivity is poor. For example, when the tool temperature at the time of pressurization is 250 ° C. and the pressure release is performed at 50 ° C. or less, the time required for one cycle is 5 to 10 minutes, which is a very long time.
（３） LSIチップの電極と配線基板の導体配線との電
気的な接続は接触のみにより行っている為、LSIチップ
の電極及び導体配線の材質がAl,Cu等の場合は、表面の
酸化膜の影響により、接触抵抗が非常に大きい。(3) Since the electrical connection between the electrodes of the LSI chip and the conductor wiring of the wiring board is made only by contact, when the material of the electrodes and conductor wiring of the LSI chip is Al, Cu, etc., the oxide film on the surface Due to the effect of, the contact resistance is very large.
問題点を解決するための手段 本発明は前記問題点を解決する為に、接続樹脂の硬化を
パルス加熱に行うものである。Means for Solving the Problems In order to solve the above problems, the present invention is to cure the connection resin by pulse heating.
作用 接続樹脂の硬化をパルス加熱にて行うことにより、短時
間でLSIチップの固着と電気的な接続を得ることができ
る。By hardening the connecting resin by pulse heating, it is possible to fix the LSI chip and obtain electrical connection in a short time.
実施例 本発明の一実施例を、第１図を参照して説明する。Embodiment An embodiment of the present invention will be described with reference to FIG.
まず第１図ａに示す様に、セラミック，ガラス，ガラス
ポリイミド等よりなる配線基板１の導体配線２を有した
面に、熱硬化型の接続樹脂３を塗布する。導体配線２は
Al,iTO,Cr−Au,Cu等であり、その厚み120.1〜35μｍ程
度である。また接続樹脂３は、エポキシ，シリコーンア
クリル等である。接続樹脂３の塗布方法は、ディスペン
ス法，印刷法等を用いる。次に第１図ｂに示す様に、突
起電極５を有したLSIチップ４を突起電極５と導体配線
２が一致する様に配線基板１にパルス加熱ツール６によ
り加圧する。突起電極５は、Au,Cu,Alハンダ等でありそ
の厚みは１μｍ〜30μｍ程度である。LSIチップ４の加
圧時に、導体配線２上にあった接続樹脂３は周囲に押し
出され、突起電極５と導体配線２は電気的に接触する。
加圧力は5g/バンプ〜150g/バンプ程度である。この状態
で、パルス加熱ツール６に電流を通電し、パルス加熱ツ
ール６を加熱し、接続樹脂３を硬化する。パルス加熱ツ
ール６の温度は、100℃〜250℃程度であり、時間は0.5
秒〜５秒程度であり、従来の常時加熱法に比べて非常に
生産性がよい。硬化する接続樹脂３の量は、LSIチップ
４と配線基板１の間の非常に少い量である為、前記した
温度と時間で硬化は十分である。次に、第１図ｃに示す
様に、パルス加熱ツール６の温度が50℃〜室温以下にな
った時点で加圧を解除し、LSIチップ４を配線基板１に
固着するとともに、LSIチップ４の突起電極５と導体配
線２を電気的に接続したものである。加圧の解除は、パ
ルス加熱ツール６が十分に冷却された後に行う為、接続
樹脂３は十分な接着強度を有しており、従来の様な電気
的な接続不良は生じない。加熱方法がパルス加熱である
為、ツール６の冷却は、電流通電後05〜１秒程度の短い
時間で自然冷却でき、生産性がよい。突起電極５及び導
体配線２に、Al,Cu等の表面に酸化膜を形成しやすい金
属を用いた場合には、パルス加熱ツール６の温度を高温
に設定することにより、突起電極５と導体配線２の金属
材料間で拡散あるいは合金を生成させることができ、低
抵抗な接続を続けることができる。例えば、突起電極５
にAu,導体配線２にAlを用いた場合、接続樹脂３の硬化
に紫外線を用いた場合は、接触抵抗は10-1〜10′Ω／電
極程度と大きいが、250℃程度の加熱によるパルス加熱
を用いた場合は、10-3Ω／電極と、２桁〜４桁程度接触
抵抗は小さくなる。First, as shown in FIG. 1A, a thermosetting connection resin 3 is applied to the surface of the wiring substrate 1 made of ceramic, glass, glass polyimide or the like having the conductor wiring 2. Conductor wiring 2
Al, iTO, Cr-Au, Cu, etc., having a thickness of about 120.1 to 35 μm. The connection resin 3 is epoxy, silicone acrylic, or the like. A dispensing method, a printing method, or the like is used as a method for applying the connection resin 3. Next, as shown in FIG. 1B, the LSI chip 4 having the protruding electrode 5 is pressed against the wiring board 1 by the pulse heating tool 6 so that the protruding electrode 5 and the conductor wiring 2 are aligned with each other. The protruding electrode 5 is Au, Cu, Al solder or the like and has a thickness of about 1 μm to 30 μm. When the LSI chip 4 is pressed, the connection resin 3 on the conductor wiring 2 is pushed out to the surroundings, and the protruding electrode 5 and the conductor wiring 2 are electrically contacted.
The applied pressure is about 5g / bump to 150g / bump. In this state, a current is applied to the pulse heating tool 6 to heat the pulse heating tool 6 and cure the connection resin 3. The temperature of the pulse heating tool 6 is about 100 to 250 ° C, and the time is 0.5
It is about 2 to 5 seconds, which is very good in productivity as compared with the conventional constant heating method. Since the amount of the connecting resin 3 to be cured is a very small amount between the LSI chip 4 and the wiring board 1, the curing is sufficient at the above temperature and time. Next, as shown in FIG. 1c, the pressure is released when the temperature of the pulse heating tool 6 falls below 50 ° C. to room temperature, the LSI chip 4 is fixed to the wiring board 1, and the LSI chip 4 The projecting electrode 5 and the conductor wiring 2 are electrically connected. Since the pressure is released after the pulse heating tool 6 is sufficiently cooled, the connection resin 3 has a sufficient adhesive strength, and the electrical connection failure as in the past does not occur. Since the heating method is pulse heating, the tool 6 can be naturally cooled in a short time of about 05 to 1 second after the electric current is supplied, and the productivity is good. When a metal such as Al, Cu that easily forms an oxide film on the surface is used for the protruding electrode 5 and the conductor wiring 2, by setting the temperature of the pulse heating tool 6 to a high temperature, the protruding electrode 5 and the conductor wiring 2 A diffusion or an alloy can be formed between the two metal materials, and a low resistance connection can be continued. For example, the protruding electrode 5
When Au is used for the conductor wiring and Al is used for the conductor wiring 2, and when ultraviolet rays are used for curing the connection resin 3, the contact resistance is as large as 10 -1 to 10'Ω / electrode, but the pulse generated by heating at about 250 ° C When heating is used, the contact resistance becomes 10 -3 Ω / electrode and the contact resistance becomes small by 2 to 4 digits.
発明の硬化 本発明では、接続樹脂の硬化に、パルス加熱を用いる
為、次に示す硬化がある。Curing of the Invention In the present invention, since the pulse heating is used to cure the connection resin, there are the following curing methods.
（１） LSIチップの加圧−加熱−冷却−加圧解除まで
の時間が非常に短い為、従来の常時加熱方式に比べ生産
性がよく低コストである。また、加圧解除はパルス加熱
シールを十分に冷却した後に行う為、接続樹脂の軟化に
ともなう接続不良の発生がなく、歩留りが向上する。(1) Since the time from pressurization-heating-cooling-release of pressure of the LSI chip is very short, the productivity is better and the cost is lower than the conventional constant heating method. Further, the pressure release is performed after the pulse heating seal has been sufficiently cooled, so that the connection failure due to the softening of the connection resin does not occur and the yield is improved.
（２） パルス加熱ツールの温度を高温に設定すること
により、LSIチップの突起電極と配線基板の導体配線の
金属材料間で、拡散あるいは合金を生成させることがで
きる為、安価なAl,Cu等の金属を用いても表面の酸化膜
の影響による接触抵抗の増大はなく、低抵抗な接続が得
られ、高性能，高信頼性を実現することができる。(2) By setting the temperature of the pulse heating tool to a high temperature, it is possible to generate diffusion or an alloy between the protruding electrodes of the LSI chip and the metal material of the conductor wiring of the wiring board. Even if the above metal is used, the contact resistance does not increase due to the influence of the oxide film on the surface, a low resistance connection is obtained, and high performance and high reliability can be realized.
（３） （２）で示した理由により、LSIチップの突起
電極及び導体配線の材料の選択の自由度が大きくなり、
適用範囲が広がるとともに、安価な材料を用いることが
できる為、低コストである。(3) Due to the reason shown in (2), the degree of freedom in selecting the material for the protruding electrode and the conductor wiring of the LSI chip is increased,
Since the range of application is wide and inexpensive materials can be used, the cost is low.
（４） 接触抵抗が非常に小さくなる為、パワーデバイ
ス等への適用が可能になり、デバイスの適用範囲が広が
る。(4) Since the contact resistance is extremely small, it can be applied to power devices and the like, and the applicable range of devices is expanded.
【図面の簡単な説明】 第１図は本発明の一実施例を工程順に示す断面図、第２
図は従来例を工程順に示す断面図である。 １……配線基板、２……導体配線、３……接続樹脂、４
……LISチップ、５……突起電極、６……パルス加熱ツ
ール。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps,
The drawings are sectional views showing a conventional example in the order of steps. 1 ... Wiring board, 2 ... Conductor wiring, 3 ... Connection resin, 4
...... LIS chip, 5 ...... projection electrode, 6 …… Pulse heating tool.
Claims (1)
を設置する領域に絶縁性を有する熱硬化型樹脂を塗布す
る熱硬化型樹脂塗布工程と、前記導体配線と前記半導体
素子の電極を一致させかつ前記電極が前記導体配線に接
触するようにパルス加熱ツールを用いて前記半導体素子
を前記絶縁性基板に加圧し前記導体配線上に存在する前
記熱硬化型樹脂をその周囲に除去する加圧工程と、前記
加圧工程の後、前記半導体素子を前記絶縁性基板に加圧
した状態で、前記パルス加熱ツールに電流を通電して前
記半導体素子の加熱を行い前記熱硬化型樹脂を加熱硬化
させ、前記半導体素子を前記絶縁性基板に固着するとと
もに、前記半導体素子の電極と前記導体配線とを電気的
に接続する工程とを有する半導体装置の製造方法。1. A thermosetting resin applying step of applying a thermosetting resin having an insulating property to an area where a semiconductor element is mounted on an insulating substrate having a conductor wiring, and the conductor wiring and an electrode of the semiconductor element are aligned. And pressurizing the semiconductor element to the insulating substrate by using a pulse heating tool so that the electrodes come into contact with the conductor wiring, and removing the thermosetting resin existing on the conductor wiring to the periphery thereof. After the step and the pressing step, while the semiconductor element is pressed against the insulating substrate, a current is passed through the pulse heating tool to heat the semiconductor element and heat cure the thermosetting resin. And a step of fixing the semiconductor element to the insulating substrate and electrically connecting the electrode of the semiconductor element and the conductor wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299483A JPH0777227B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299483A JPH0777227B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63151033A JPS63151033A (en) | 1988-06-23 |
| JPH0777227B2 true JPH0777227B2 (en) | 1995-08-16 |
Family
ID=17873154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61299483A Expired - Fee Related JPH0777227B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777227B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL105772A (en) * | 1992-06-01 | 1998-07-15 | Univ Florida | Methods and materials for combating pests |
| JP2000036520A (en) | 1998-05-15 | 2000-02-02 | Nec Corp | Method for mounting flip chip and device therefor |
| JP2002231754A (en) * | 2001-02-05 | 2002-08-16 | Nec Corp | Manufacturing method for semiconductor device |
| JP2002270642A (en) * | 2001-03-12 | 2002-09-20 | Sony Corp | Manufacturing method for semiconductor device |
| US6713318B2 (en) * | 2001-03-28 | 2004-03-30 | Intel Corporation | Flip chip interconnection using no-clean flux |
| JP2005520563A (en) | 2002-03-22 | 2005-07-14 | ユニバーシティ・オブ・フロリダ・リサーチ・ファンデーション・インコーポレーテッド | Airtight sealed bait for termites in the ground |
| JP3871634B2 (en) | 2002-10-04 | 2007-01-24 | シャープ株式会社 | COF semiconductor device manufacturing method |
| US7037805B2 (en) * | 2003-05-07 | 2006-05-02 | Honeywell International Inc. | Methods and apparatus for attaching a die to a substrate |
| JP4024773B2 (en) | 2004-03-30 | 2007-12-19 | シャープ株式会社 | WIRING BOARD, SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR MODULE DEVICE |
| JP3833669B2 (en) | 2004-04-08 | 2006-10-18 | シャープ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0638436B2 (en) * | 1985-02-22 | 1994-05-18 | カシオ計算機株式会社 | Method of joining semiconductor pellet and substrate |
-
1986
- 1986-12-16 JP JP61299483A patent/JPH0777227B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63151033A (en) | 1988-06-23 |
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