JPH0773682A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide an effective forced refreshing method of an FRAM, etc., to enhance its access efficiency, and further, to prevent the omission of the retreated data due to power source interruption while executing forced refresh and to enhance the reliability of the FRAM, etc. CONSTITUTION:This device is provided with access counters DC and SC provided in the FRAM, etc., making a ferroelectric capacitor a storage element corresponding to respective word lines or plate lines and for counting the number of times of selection and an access counter control circuit CC updating the count value of the corresponding access counter when the word line or the plate line is selected and identifying that the value arrives at a prescribed value. Then, the forced refresh is executed making prescribed number of ferroelectric capacitors connected to respective word lines or plate lines a unit. Further, at the time of the forced refresh, a retreat memory SM for temporarily retreating the holding data in the objective ferroelectric capacitor is constituted of a nonvolatile ferroelectric capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a ferro electric device.
RAM) (Random Access M)
The present invention relates to a technology that is especially effective when used for random access memory).

[0002]

2. Description of the Related Art There is a so-called ferroelectric RAM (hereinafter abbreviated as FRAM) using a ferroelectric capacitor as a memory element. Further, in such an FRAM, rewriting is performed by applying a predetermined high voltage exceeding the write voltage or applying a voltage having the same potential as the write voltage for a predetermined time or more between both electrodes of a ferroelectric capacitor serving as a memory element. There is known so-called forced refresh (polling) for recovering the decrease in spontaneous polarization of a ferroelectric capacitor due to fatigue. Furthermore, one selection M
OSFET (Metal Oxide Semiconductor)
ductor Field Effect Trans
istor: metal oxide semiconductor type field effect transistor. In this specification, a plurality of ferroelectric capacitors are provided corresponding to MOSFETs (collectively referred to as insulated gate field effect transistors), thereby suppressing stress on the ferroelectric capacitors in the non-selected state. So-called 1MOS / multi-capacitor type FRA designed for high integration
There is M.

Regarding FRAM and its forced refresh, for example, in 1992, Gordon and Breach Science Publishing Company (Gordon and Br).
published by "Each Science Publishers", "Integrated Ferroelectrics (I
ntegrated Ferroelectrics ”
See pages 1-15. Also, 1MOS
Regarding the multi-capacitor type FRAM, there is, for example, Japanese Patent Laid-Open No. 4-90189.

[0004]

As described in the above-mentioned material, the ferroelectric capacitor used as the storage element of the FRAM causes a decrease in spontaneous polarization due to rewriting fatigue, but the degree of access to the FRAM is increased. It can be determined by the number of times, that is, the number of times of rewriting of the ferroelectric capacitor. Therefore, if a counter for counting the number of times of access is provided in the FRAM and the forced refresh is performed when the count value reaches a predetermined value, an abnormal decrease in spontaneous polarization of the ferroelectric capacitor can be prevented, and FR
The reliability of AM can be maintained. However, in reality, the number of times the FRAM is accessed varies from address to address, so if the forced refresh start condition is determined based on the number of times the entire FRAM is accessed, meaningless forced refresh will be performed on an address with a small number of accesses. As a result, the time required for the forced refresh is correspondingly increased, and the access efficiency of the FRAM is reduced.

On the other hand, when the FRAM is forcibly refreshed, it is necessary to temporarily save the data held in the target ferroelectric capacitor. The save memory for this purpose is generally a volatile memory such as a random access memory. Composed. However, as the FRAM becomes larger and the time required for the forced refresh increases, the possibility that the power will be cut off during the forced refresh increases. As a result, the data saved in the random access memory or the like is lost, and the reliability of the FRAM is lowered.

An object of the present invention is to provide an effective forcible refresh method for FRAM or the like and improve its access efficiency. Another object of the present invention is to prevent loss of saved data due to power-off and improve reliability of FRAM and the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a semiconductor memory device such as an FRAM having a ferroelectric capacitor as a memory element is provided corresponding to, for example, each word line or plate line, and an access counter for counting the number of times of selection and each word line or plate line. And an access counter control circuit for updating the count value of the corresponding access counter and for identifying that the count value has reached a predetermined value, forcibly refreshing the ferroelectric capacitor for each word line or plate. It is implemented in units of a predetermined number of ferroelectric capacitors coupled to the line. Further, during the forced refresh, the saving memory for temporarily saving the data held in the ferroelectric capacitor that is the target of the forced refresh is composed of a nonvolatile ferroelectric capacitor.

[0009]

According to the above means, even when the access to the FRAM or the like is concentrated on a specific address, the forced refresh is performed only on the ferroelectric capacitor which is selected a lot, and the forced refresh judgment condition is made substantially uniform. In addition to being able to do it, subdivide the forced refresh execution unit,
The required time can be shortened and the access efficiency of the FRAM or the like can be improved. Further, even when the FRAM or the like becomes large in scale and the time required for the forced refresh increases, it is possible to prevent the saved data from being lost due to the power-off during the forced refresh and improve the reliability of the FRAM or the like.

[0010]

1 is a block diagram showing an embodiment of a single chip microcomputer including an FRAM to which the present invention is applied. According to the figure, first the FRAM
An outline of the configuration and operation of the microcomputer including the above will be described. The circuit elements forming each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the single-chip microcomputer of this embodiment has a central processing unit CPU of a stored program system as its basic constituent element. An FRAM, a random access memory RAM, a timer circuit TIM, a serial communication interface SCI, an input / output interface I / O, an analog / digital conversion circuit A / D, etc. are coupled to the central processing unit CPU via an internal bus BUS. It The microcomputer is supplied with a power supply voltage VCC and a ground potential VSS via external terminals VCC and VSS, and is supplied with a power supply voltage AVCC via external terminals AVCC and AVSS.
And the ground potential AVSS. Of these, the power supply voltage AVCC and the ground potential AVSS are supplied as operating power supplies for analog circuits such as the analog / digital conversion circuit A / D, and the power supply voltages VCC and VSS are supplied as operating power supplies for other digital circuits.

In this embodiment, the central processing unit C
A refresh request signal RFQB, which is one of interrupt request signals from the FRAM, is added to the PU (here, a so-called inverted signal or the like which is selectively brought to a low level when it is enabled is appended with B at the end of its name). The same applies hereinafter) is supplied, and the FRAM is supplied with a refresh start signal RF which is an acceptance signal for the refresh request signal RFQB from the central processing unit CPU. The refresh request signal RFQB has a low level as its effective level, and the refresh start signal RF has a high level as its effective level, although not particularly limited.

Here, the central processing unit CPU executes predetermined arithmetic processing according to a control program stored in advance in the FRAM, and controls / controls each unit of the microcomputer. Further, the FRAM is configured with a ferroelectric capacitor as a storage element, and has a central processing unit C.
It stores control programs, fixed data, etc. required for PU operation. In this embodiment, the FRAM has an access counter provided corresponding to each plate line of the memory array, and an overflow not shown when the access counter is updated and its count value reaches a predetermined value, as will be described later. An access counter control circuit CC for selectively raising the signal OF to a high level. Overflow signal OF
Is set to the high level, the FRAM sets the refresh request signal RFQB to the low level and requests the central processing unit CPU to start the forced refresh. The central processing unit CPU uses the refresh request signal RFQ.
When B is accepted, the refresh activation signal RF is set to a high level to activate FRAM forced refresh. Then, the timer circuit TIM measures the time required for the forced refresh, and the access to the FRAM is prohibited during this period.

Next, the random access memory RAM is
It is composed of a static RAM having a predetermined storage capacity, and temporarily stores the calculation result of the central processing unit CPU, control data, and the like. On the other hand, the timer circuit TIM measures a predetermined time based on a clock signal supplied from a clock generation circuit (not shown), and the central processing unit C
Realizes PU time management and calendar function. The serial communication interface SCI controls and manages data exchange between the serial input / output device coupled to the outside of the microcomputer and the central processing unit CPU or the random access memory RAM, and the input / output interface I / O is It controls and manages data exchange between a parallel input / output device coupled to the outside and a central processing unit CPU or a random access memory RAM.
Further, the analog / digital conversion circuit A / D converts an analog signal input from an external sensor or the like into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like.

FIG. 2 is a block diagram of an embodiment of the FRAM included in the single chip microcomputer shown in FIG. In addition, in FIGS. 3 and 4, F of FIG.
A circuit diagram of one embodiment of the memory array MARY included in the RAM is shown, and a circuit diagram of one embodiment of the Y switch YS is shown in FIG. 6 and 8 are block diagrams of an embodiment of the read / write circuit RW and the access counter control circuit CC included in the FRAM of FIG. 2, respectively, and FIG. 7 is a read / write circuit of FIG. RW
A block diagram of an embodiment of the unit read / write circuit DRW0 included in FIG. Based on these figures, the outline and characteristics of the configuration and operation of the FRAM of this embodiment will be described. In the circuit diagram below, M shown in the figure
The OSFETs are all N-channel type, although not particularly limited.

In FIG. 2, the FRAM of this embodiment is
A memory array MARY in which storage elements made of ferroelectric capacitors are arranged substantially in a lattice is used as a basic constituent element. In this embodiment, the memory array MAR
Y is divided into a data memory DM, a save memory SM, a data memory access counter DC, and a save memory access counter SC according to its function.

Here, the data memory DM forming the memory array MARY is not particularly limited, but as shown in FIG. 3, 8 × (P + 1) memory blocks DB0.
Each of these memory blocks is divided into 0 to DB07 to DBp0 to DBp7, and each of these memory blocks includes (m + 1) × (n + 1) storage elements or ferroelectric capacitors C and n + 1 selection MOSFETs Q. including. One electrode of the m + 1 ferroelectric capacitors C arranged in the same column of each memory block corresponds to the corresponding sub data line d000 to d00n to d070 to d07n to dp00 to dp0n to dp70 to dp7n. Are commonly coupled to the sources of the selection MOSFETs Q. The other electrodes of the n + 1 ferroelectric capacitors C arranged in the same row of each memory block have corresponding plate lines P00 to P0m to Pp0.
Commonly coupled to Ppm. Further, the drains of the selection MOSFETs Q of the respective memory blocks are commonly coupled to the corresponding data lines D00 to D0n to D70 to D7n, and the gates thereof correspond to the corresponding word lines W0 to W0.
Commonly coupled to Wp.

On the other hand, the save memory SM is divided into eight memory blocks SB0 to SB7 arranged in the horizontal direction in the figure, and each of these memory blocks is composed of n + 1 storage elements, that is, ferroelectric capacitors C. Equal number of choices M
And OSFETQ. One electrode of the ferroelectric capacitor C forming each memory block is connected to the corresponding select MO.
The other electrodes are respectively coupled to the sources of the SFETQ, and the other electrodes are commonly coupled to the plate line Ps. In addition, the drain of the selection MOSFET Q forming each memory block has corresponding data lines D00 to D0n to D70 to D.
7n, each of which has its gate connected to the word line Ws
Are commonly combined with.

Next, the data memory access counter D
As shown in FIG. 4, C is vertically divided into p + 1 memory blocks DCB0 to DCBp, and each of these memory blocks is arranged in a grid pattern (m
+1) × (q + 1) storage elements, that is, ferroelectric capacitors C, and q + 1 selection MOSFETs Q. One electrode of the m + 1 ferroelectric capacitors C arranged in the same column of each memory block is common to the source of the corresponding select MOSFET Q via the corresponding sub data lines dc00 to dc0q to dcp0 to dcpq. Be combined. The other electrodes of the q + 1 ferroelectric capacitors C arranged in the same row of each memory block have corresponding plate lines P00 to P0m to Pp0.
Commonly coupled to Ppm. Further, the drains of the selection MOSFETs Q of the memory blocks are commonly coupled to the corresponding data lines DC0 to DCq, respectively, and the gates thereof are commonly coupled to the corresponding word lines W0 to Wp, respectively.

On the other hand, the save memory access counter SC
Is composed of one memory block SCB, and this memory block SCB includes q + 1 storage elements, that is, ferroelectric capacitors C and the same number of selection MOSFETs Q. One electrode of the ferroelectric capacitor C forming the memory block SCB is coupled to the source of the corresponding selection MOSFET Q, and the other electrode is connected to the plate line Ps.
Are commonly combined with. The drain of the selection MOSFET Q is coupled to the corresponding data line DC0 to DCq, and the gate thereof is commonly coupled to the word line Ws.

In this embodiment, a data memory access counter DC and a save memory access counter S
C is the corresponding plate line P00 to P0m to Pp0
~ Used to count the number of times Ppm or Ps is accessed. These access counters are counted up by the access counter control circuit CC described later,
Count the number of accesses of the corresponding plate line from 1 to 2 q + 1.sup.-1 times. The number of times the corresponding plate line is accessed becomes 2 to the power of q + 1, the access counter DC for the data memory or the access counter SC for the save memory.
Substantially overflows, the FRAM sets the refresh request signal RFQB to the low level and interrupts the central processing unit CPU to request the start of the forced refresh, as described later.

That is, in the FRAM of this embodiment, the number of access times of the ferroelectric capacitors forming the memory array MARY is managed in units of n + 1 ferroelectric capacitors coupled to each plate line, and these ferroelectric capacitors are accessed. The forced refresh is performed in units of dielectric capacitors. As a result, for example, even when access is concentrated on a specific address, the forced refresh is selectively performed only on the ferroelectric capacitors that are frequently selected, and the forced refresh determination condition can be made substantially uniform. The execution unit of forced refresh can be subdivided, the required time can be shortened, and the access efficiency of FRAM can be improved.

The word lines W0 to Wp and Ws forming the memory array MARY are coupled to the X address decoder XD on the left side thereof, and are alternatively selected. Further, the plate lines P00 to P0m to Pp0 to Ppm and Ps forming the memory array MARY are
On the right side thereof, it is coupled to the plate driver PD and selectively becomes a predetermined selection level or a non-selection level. X
The address decoder XD is supplied with the i + 1-bit internal address signals x0 to xi from the X address buffer XB and the internal voltage VW from the internal voltage generating circuit VG. Further, the plate driver PD is supplied with internal address signals x0 to xi from the X address buffer XB,
Internal voltage VP and VO and HVO are supplied from internal voltage generation circuit VG. In the X address buffer XB,
X address signals AX0 to AXi are supplied via address input terminals AX0 to AXi, and power supply voltage VCC is supplied to internal voltage generating circuit VG via power supply voltage input terminal VCC.

The internal voltage generating circuit VG has a power supply voltage VCC.
Is boosted to form predetermined internal voltages VP, VW and VO, and at the same time, an internal voltage HVO which is an intermediate potential between the internal voltage VO and the ground potential VSS is formed. Of these, the internal voltage VO is supplied to the plate driver PD and the read / write circuit RW as a so-called write voltage for the ferroelectric capacitor, and the internal voltage HVO is also supplied to the plate driver PD and the read / write circuit RW. Further, the internal voltage VW is set to a potential higher than the internal voltage VO by at least the threshold voltage of the selection MOSFET Q,
The voltage is supplied to the X address decoder XD as a selection voltage for the word lines W0 to Wp and Ws. Furthermore, the internal voltage V
P has a potential higher than the internal voltage VW and is supplied to the plate driver PD as a refresh voltage of the ferroelectric capacitor C.

The X address buffer XB takes in and holds the X address signals AX0 to AXi input via the address input terminals AX0 to AXi, and at the same time, based on these X address signals, the internal address signals x0 to xi.
Are formed and supplied to the X address decoder XD and the plate driver PD.

On the other hand, the X address decoder XD is the FRA.
Depending on the operation mode of M, the internal address signals x0 to xi supplied from the X address buffer XB are selectively decoded to selectively set the word lines W0 to Wp and Ws to a selected level such as the internal voltage VW. To do. Further, the plate driver PD selectively decodes the internal address signals x0 to xi according to the operation mode of the FRAM, and the plate lines P00 to P0m to Pp0 to Ppm and Ps.
Is selectively set as a predetermined selection level or a non-selection level.
The plate lines P00 to P0m in each operation mode
The selection and non-selection levels of Pp0 to Ppm and Ps will be described later.

Next, the data lines D00 to D0n to D70 to D7n forming the memory array MARY are coupled to the Y switch YS under the data lines, and eight common data lines B0 to B7 are provided via the Y switch YS. Connected selectively. Further, the data lines DC0 to DCq are coupled to the Y switch YS below them, and are directly coupled to the read / write circuit RW via the Y switch YS.

As shown in FIG. 5, the Y switch YS is provided for 8 × (n +) corresponding to the data lines D00 to D0n to D70 to D7n and DC0 to DCq.
1) + (q + 1) MOSFETs Q1 to Q6 and 2 corresponding to the data lines D00 to D0n to D70 to D7n
2 × 8 × (n + 1) MOSFETs provided one by one
Including Q7 to QE. Of these, MOSFETs Q1 to Q
The drains of 6 are coupled to the corresponding data lines D00 to D0n to D70 to D7n and DC0 to DCq, respectively. Further, its source is coupled to the ground potential VSS, and its gate is commonly supplied with the internal control signal FM from the timing control circuit TC. On the other hand, MOSFE
The drains of TQ7 to QE have corresponding data lines D00 to D00.
D0n to D70 to D7n, respectively. In addition, eight MOSFETs MOSFETQ7- corresponding to the data lines D00-D70 to D0n-D7n, respectively.
The sources of Q8 to QB to QC are sequentially commonly coupled to the corresponding common data lines B0 to B7, and their gates are connected to Y.
The corresponding data line selection signal Y from the address decoder YD
0 to Yn are commonly supplied. Further, the sources of the eight MOSFETs Q9 to QA to QD to QE respectively corresponding to the data lines D00 to D70 to D0n to D7n are commonly connected to the internal voltage supply point HVO, and the gates thereof are not connected to the corresponding data lines. Signal YN0 to YN
n are commonly supplied.

The internal control signal FM is set at a predetermined timing when the FRAM is set to the forced refresh mode for recovering the decrease in spontaneous polarization due to the rewriting fatigue of the ferroelectric capacitors C constituting the memory array MARY. Selectively set to high level. The data line selection signals Y0 to Yn are the Y address signals AY0 to AYj when the FRAM is selected in a predetermined operation mode.
According to the above, it is alternatively set to a predetermined high level. At this time, the data line non-selection signals YN0 to YNn are set to the high level complementarily to the corresponding data line selection signals Y0 to Yn.

MOSFET Q constituting Y switch YS
1 to Q6 are turned on all at once in response to the high level of the internal control signal FM when the FRAM is in the forced refresh mode, and the corresponding data lines D00 to D0n to D70 to D7n and DC0 to DCq are all grounded. Connect to potential VSS. In addition, MOSFETs Q7 to Q8
Through QB-QC are corresponding data line selection signals Y0-Y0.
Upon receiving the high level of Yn, eight data lines are selectively turned on, and the corresponding eight data lines D00 to D0n to D are connected.
70 to D7n and the common data lines B0 to B7 are selectively connected. At this time, the MOSFETs Q9 to QA to QD to QE have corresponding data line non-selection signals YN0 to YN0.
In response to the high level of YNn, eight data lines are selectively turned on, and the corresponding eight data lines D00 to D0n to D70 to D7n are connected to the internal voltage supply point HVO.

The Y address decoder YD has a j + 1-bit internal address signal y0 from the Y address buffer YB.
~ Yj are provided. The Y address buffer YB is supplied with Y address signals AY0 to AYj via address input terminals AY0 to AYj.

The Y address buffer YB has address input terminals AY0 to AYj when the FRAM is selected.
Y address signals AY0 to AYj supplied via the Y address signals AY0 to AYj are stored and stored, and internal address signals y0 to yj are formed based on these Y address signals and supplied to the Y address decoder YD. Y address decoder YD
Decodes the internal address signals y0 to yj supplied from the Y address buffer YB to generate corresponding data line selection signals Y0 to Yn and data line non-selection signals YN0 to YN0.
YNn is selectively set to a predetermined high level.

The common data lines B0 to B7 to which the designated eight data lines D00 to D0n to D70 to D7n of the memory array MARY are selectively connected are coupled to the read / write circuit RW therebelow. . As described above, the read / write circuit RW includes the memory array MA.
The data lines DC0 to DCq of RY are also coupled.

As shown in FIG. 6, the read / write circuit RW corresponds to eight unit read / write circuits DRW0 to DRW7 provided corresponding to the common data lines B0 to B7 and the data lines DC0 to DCq. It is provided with q + 1 unit read / write circuits CRW0 to CRWq.
Of these, the unit read / write circuits DRW0 to DRW7
Are the corresponding common data lines B0 to B7 above them.
Be combined with. Further, below that, it is coupled to the corresponding unit circuit of the data output buffer OB via the read data lines RD0 to RD7, and is coupled to the corresponding unit circuit of the data input buffer IB via the write data lines WD0 to WD7. To be done. On the other hand, the unit read / write circuits CRW0 to CRWq are coupled to the corresponding data lines DC0 to DCq above them. Further, below that, it is coupled to the access counter control circuit CC via the corresponding read data lines RC0 to RCq and write data lines WC0 to WCq. In the unit read / write circuits DRW0 to DRW7 and CRW0 to CRWq,
The internal control signal PCD is commonly supplied from the timing control circuit TC. The internal control signal PCD is FRAM.
Is set to the read mode, it is selectively set to the high level at a predetermined timing.

Here, the unit read / write circuits DRW0 to DRW7 and CR which form the read / write circuit RW.
Each of W0 to CRWq is provided between the corresponding common data lines B0 to B7 and data lines DC0 to DCq and the ground potential VSS, as represented by the unit read / write circuit DRW0 in FIG. MOSFET
QF, one sense amplifier SA0 to SA7 and SAC0 to SACq, and output latches OL0 to OL7
And OLC0 to OLC7, write amplifiers WA0 to W
A7 and WAC0 to WACq, input latches IL0 to
IL7 as well as ILC0 to ILCq.

Of these, the internal control signal PCD is commonly supplied to the gate of the MOSFET QF. In addition, sense amplifiers SA0-SA7 and SAC0-S
The input terminals of ACq are corresponding common data lines B0 to B7.
And data lines DC0-DCq, the output terminals of which are associated with corresponding output latches OL0-OL7 and O.
It is coupled to the input terminals of LC0-OLCq. The output terminals of the output latches OL0 to OL7 are coupled to the corresponding unit circuits of the data output buffer OB via the corresponding read data lines RD0 to RD7, and the output latches OLC0 to OLC are connected.
The output terminal of q has corresponding read data lines RC0 to RC.
It is coupled to the access counter control circuit CC via q. The output terminals of each unit circuit of the data output buffer OB are coupled to the corresponding data input / output terminals IO0 to IO7.

On the other hand, the input terminals of each unit circuit of the data input buffer IB correspond to the corresponding data input / output terminals IO0-I0.
It is coupled to O7 and its output terminal is the write data line WD
It is coupled to the input terminals of corresponding input latches IL0-IL7 of read / write circuit RW via 0-WD7. The output terminals of these input latches correspond to the corresponding write amplifier W.
It is coupled to the input terminals of A0 to WA7. Input latch IL
The input terminals of C0 to ILCq are connected to the access counter control circuit CC via the corresponding write data lines WC0 to WCq.
Is connected to the output terminal of the corresponding write amplifier W.
It is coupled to the input terminals of AC0-WACq. The output terminals of the write amplifiers WA0 to WA7 are coupled to the corresponding common data lines B0 to B7, and the write amplifiers WAC0 to WAC are connected.
The output terminals of q are coupled to the corresponding data lines DC0-DCq.

As will be described later, the MOSFET QF has an F
When the RAM is in the read mode, the internal control signal P
It is selectively turned on in accordance with CD, and the corresponding data line of the memory array MARY is precharged to the ground potential VSS before the plate driver PD selects the plate line. The sense amplifiers SA0 to SA7 and SAC0 to SACq perform the selection operation of the plate line by the plate driver PD so that the memory array MA.
The read current obtained via the corresponding data line of RY is converted into a voltage signal and amplified, and the corresponding output latch OL
0-OL7 as well as OLC0-OLCq. The output signals of the output latches OL0 to OL7 are transferred to the data output buffer O via the corresponding read data lines RD0 to RD7.
It is transmitted to B and output to the outside of FRAM. The output signals of the output latches OLC0 to OLCq are transmitted to the access counter control circuit CC via the corresponding read data lines RC0 to RCq, and undergo a predetermined update process.

On the other hand, the input latches IL0 to IL7 are connected to the corresponding write data line WD0 from the data input buffer IB.
To write data input via WD7, the write data is held and the corresponding write amplifiers WA0 to WA0
Transmit to WA7. The write amplifiers WA0 to WA7 convert these write data into predetermined write signals,
From the corresponding common data lines B0 to B7 to the memory array MA
Write to the selected ferroelectric capacitor via the corresponding data line of RY.

In this embodiment, the output latches OL0-OL0
Data feedback signal lines FB0-FB7 and FBC0 are provided between OL7 and OLC0-OLCq and corresponding input latches IL0-IL7 and ILC0-ILCq.
~ FBCq are provided respectively. As is well known, FR
In AM, so-called destructive reading is used to read stored data. Therefore, in the FRAM of this embodiment, the output latches OL0-OL7 and OLC0-OL are output from the selected ferroelectric capacitors via the corresponding sense amplifiers SA0-SA7 and SAC0-SACq.
The stored data read to Cq is the data feedback signal line F
Corresponding input latches IL0-IL7 and ILC0-IL via B0-FB7 and FBC0-FBCq
It is transmitted to Cq and rewritten in the selected ferroelectric capacitor.

The FRAM of this embodiment includes an access counter control circuit CC provided corresponding to the data memory access counter DC and the save memory access counter SC. The access counter control circuit CC includes a count-up circuit + 1 and an overflow detection circuit OFD, as shown in FIG. Of these, the input terminal of the count-up circuit +1 is coupled to the unit read / write circuits CRW0 to CRWq of the read / write circuit RW via the read data lines RC0 to RCq.
The output terminals of the write data lines WC0 to WCq
Is connected to the unit read / write circuits CRW0 to CRWq of the read / write circuit RW, and further to the input terminal of the overflow detection circuit OFD. Output signal of overflow detection circuit OFD, that is, overflow signal OF
Is supplied to the count-up circuit +1 and is also supplied to the timing control circuit TC.

The count-up circuit +1 of the access counter control circuit CC includes unit read / write circuits CRW0 to CRW of the memory array MARY to the read / write circuit RW.
The unit read / write circuit CRW of the read / write circuit RW is incremented from the write data lines WC0 to WCq by counting up the count value of the data memory access counter DC or the save memory access counter SC read via q.
The data is rewritten to the data memory access counter DC or the save memory access counter SC via 0 to CRWq. As a result, the access counter DC for the selected data memory or the access counter SC for the save memory is selected.
The count value of is incremented each time the corresponding plate line is selected.

On the other hand, the overflow detection circuit OFD monitors the count value of the data memory access counter DC or the save memory access counter SC updated by the count-up circuit +1. When the count value reaches a predetermined value, an overflow occurs. The signal OF is selectively set to the high level. When the overflow signal OF is set to the high level, the count-up circuit +1 sets its output signal to the logic "0" for all bits, and the data memory access counter D
C or the save memory access counter SC is cleared to the initial state. Further, the timing control circuit TC sets the refresh request signal RFQB to low level, and interrupts the central processing unit CPU of the microcomputer to request the start of forced refresh.

The timing control circuit TC includes an FRAM enable signal FRE and a read / write signal R / which are supplied as start-up control signals from the preceding circuit of the microcomputer.
Based on W and the refresh activation signal RF, the various internal control signals are selectively formed and supplied to each part of the FRAM. Further, as described above, the refresh request signal RFQB is selectively set to the low level in response to the high level of the overflow signal OF output from the overflow detection circuit OFD of the access counter control circuit CC, and the central processing unit CPU is interrupted. Call.

FIG. 9 shows a process flow chart of an embodiment of the access counter control circuit CC included in the FRAM of FIG. A specific control procedure of the data memory access counter DC and the save memory access counter SC by the FRAM access counter control circuit CC of this embodiment will be described with reference to FIG.

In FIG. 9, the control of the data memory access counter DC and the save memory access counter SC by the access counter control circuit CC is started when one of the plate lines of the memory array MARY is set to the access state, that is, the selected state. To be done. Although the spontaneous polarization of the ferroelectric capacitor decreases as the number of times of rewriting increases as described above, since rewriting is performed after destructive reading even in the read mode, the data memory access counter DC and The number of access to the word line by the save memory access counter SC is counted regardless of the write and read modes.

In the FRAM, in step ST11, the ferroelectric capacitor coupled to the selected plate line of the data memory DM is accessed, and the content held in the data memory access counter DC, that is, the count value is read out. Access counter control circuit C
It is transmitted to the C count-up circuit + 1.

The count-up circuit +1 has step ST
In 12, the count value (DC) of the data memory access counter DC is incremented by +1, that is, a new count value NDC is obtained, and the new count value NDC is output to its output terminal, that is, the write data lines WC0 to WCq. This new count value NDC
Receives the determination by the overflow detection circuit OFD in step ST13, and if it does not reach the predetermined value and does not overflow, jumps to the process of step ST16.

On the other hand, when the new count value NDC exceeds the predetermined value and overflows, the overflow detection circuit OFD
Is the overflow signal OF in step ST14.
Is asserted to a valid or high level. As a result, the count-up circuit +1 clears its output signal, that is, the new count value NDC to 0 in step ST15. Further, the timing control circuit TC asserts the refresh request signal RFQB at a low level and issues an interrupt for requesting the start of forced refresh to the central processing unit CPU.

The new count value NDC counted up or cleared by the count-up circuit +1 is
In step ST16, the data is written into the data memory access counter DC of the memory array MARY, and the access is completed.

As described above, in the FRAM of this embodiment, the plate lines P00 to P0m of the memory array MARY are used.
Through Pp0 to Ppm and Ps corresponding to a predetermined number, that is, 8 × (n + 1) ferroelectric capacitors, a q + 1 bit data memory access counter D.
C or a save memory access counter SC is provided respectively. These access counters are updated by the access counter control circuit CC every time the corresponding plate line is accessed, and undergo overflow detection processing. In other words, in the FRAM of this embodiment, the number of times the ferroelectric capacitors are accessed is managed in units of 8 × (n + 1) ferroelectric capacitors coupled to each plate line. Since forced refresh is performed in units of capacitors, FRA
Even when the access to M is concentrated at a specific address, the forced refresh is performed only on the ferroelectric capacitor that is frequently selected. As a result, the judgment conditions for the forced refresh can be made substantially uniform, the units for executing the forced refresh can be subdivided, the required time can be shortened, and the access efficiency of the FRAM can be improved.

On the other hand, in the FRAM of this embodiment, the data memory access counter DC or the save memory access counter SC is configured with the nonvolatile ferroelectric capacitor as a storage element as described above. Therefore,
Even if the FRAM becomes large-scale and the time required for the forced refresh increases, it is possible to prevent the loss of the saved data due to the power-off during the forced refresh, thereby improving the reliability of the FRAM. is there.

FIG. 10 shows a process flow chart of an embodiment of the forced refresh mode of the FRAM of FIG. Further, FIG. 11 is a connection diagram of one embodiment of the memory array in step ST22 of the forced refresh mode of FIG. 10, and FIG. 12, FIG. 13, FIG. 14 and FIG.
In steps ST23, ST24, ST25, respectively.
And ST27 shows a connection diagram of one embodiment of the memory array. Based on these figures, F of this embodiment
A specific control procedure, connection form and characteristics of the RAM forced refresh mode will be described.

In the connection diagram below, the forced refresh is performed in the memory blocks DB00 to DB0 of the data memory DM.
7 and a case where a total of 8 × (n + 1) + (q + 1) ferroelectric capacitors which constitute the memory block DCB0 of the data memory access counter DC and are coupled to the plate line P00 are targeted are shown as an example. There is. Further, in each connection diagram, eight ferroelectric capacitors C000 to C030 and C00m to C0 which constitute the memory blocks DB00, DB01, DB02 and DB03 of the data memory DM and are coupled to the plate lines P00 and P0m.
3 m and memory blocks SB0 and SB of the save memory SM
1, SB2 and SB3, the four ferroelectric capacitors Cs00 to Cs30 or the memory blocks DBp0, DBp1, DBp2 and DBp of the data memory DM.
3 and 8 coupled to plate lines Pp0 and Ppm
Ferroelectric capacitors Cp00 to Cp30 and C
p0m to Cp3m are exemplarily shown. The direction of spontaneous polarization of the ferroelectric capacitor to be written or forcibly refreshed is indicated by an arrow, and the ferroelectric capacitor whose polarization direction changes by writing or forced refresh is indicated by a solid line. It is marked with a square. Further, in each connection diagram, the connection form in the X address decoder XD, the plate driver PD, and the read / write circuit RW is represented by a switch symbol. It goes without saying that the following description is sufficient to infer the write or read operation of the FRAM in the normal write or read mode.

In FIG. 10, the forced refresh mode of the FRAM of this embodiment is started by supplying the high level refresh activation signal RF to the FRAM from the central processing unit CPU as described above. In the FRAM, first in step ST21, the refresh request signal R to the central processing unit CPU is sent.
After the FQB is negated to the invalid level, that is, the high level, the save memory SM is prewritten in step ST22. This pre-write saves the data held in the ferroelectric capacitor to be subject to forced refresh to the save memory SM before saving the save memory S.
This is carried out to align the polarization directions of the ferroelectric capacitors forming M in the same direction.

At this time, in the FRAM, as shown in FIG. 11, the word line Ws corresponding to the save memory SM is set to the selection level of the internal voltage VW by the X address decoder XD, and the save memory S by the plate driver PD.
The plate line Ps corresponding to M is set to the selection level of the internal voltage VO. Further, the X address decoder XD sets all the word lines including the word line W0 to the non-selection level of the ground potential VSS, and the plate driver PD sets all the plate lines including the plate lines P00 to P0m to the non-selection level of the ground potential VSS. It is a selection level. Further, in the Y switch YS, the MOSFETs Q1 to Q6 are simultaneously turned on in response to the high level of the internal control signal FM, and all the data lines including the data lines D00 to D30 are set to the low level of the ground potential VSS.

From these facts, the polarization of all the ferroelectric capacitors Cs00 to Cs30, etc. constituting the save memory SM is unified in the left direction of FIG. 11, and the logic "0" is given.
It is supposed to hold the stored data of. Further, in the data memory DM, since all the word lines are set to the non-selection level and the selection MOSFETs are simultaneously turned off, the polarization direction of each ferroelectric capacitor does not change.

When the pre-writing of the save memory SM is completed, in step ST23, eight ferroelectric capacitors are selected from the ferroelectric capacitors to be subjected to the forced refresh, and pre-charge for the save read is performed. In step ST24, the holding data of the eight selected ferroelectric capacitors are read. In step ST23, in FRAM, as shown in FIG.
As shown in 2, by the X address decoder XD,
The word line W0 corresponding to the ferroelectric capacitor to be forcibly refreshed is set to the selection level of the internal voltage VW, and all the other word lines including the word line Wp are set to the non-selection level of the ground potential VSS. Further, the plate driver PD allows the memory blocks DB00 to DB07 to be stored.
And m + 1 plate lines P0 corresponding to DCB0
0 to P0m are set to the intermediate level of the internal voltage HVO, and all other plate lines are set to the non-selection level of the ground potential VSS. In the Y switch YS, for example, eight data lines D00 to D70 are selected and connected to the common data lines B0 to B7, and in the read / write circuit RW, the MOSFETs QF of the unit read / write circuits DRW0 to DRW7 are turned on all at once. .

As a result, in the memory array MARY, 8 × (n + 1) + (q + corresponding to the word line W0.
1) The select MOSFETs are turned on all at once, and the eight ground blocks VSS of the memory blocks DB00 to DB07 are supplied by the ground potential VSS supplied via the common data lines B0 to B7, that is, eight selected data lines D00 to D70. The sub data lines d000 to d070 are precharged to the ground potential VSS. The m + 1 plate lines P00 to P0m corresponding to the memory blocks DB00 to DB07 are set to the intermediate level like the internal voltage HVO via the plate driver PD as described above. In this embodiment, the two ferroelectric capacitors C000 and C030 that are subject to the forced refresh have, for example, the polarizations shown in FIG.
It is assumed that the stored data of logical "1" is held to be performed toward the left side of 2, and the polarization of the other two ferroelectric capacitors C010 and C020 is performed toward the right side of FIG. It is supposed to hold the storage data of logic "0". Other ferroelectric capacitors that are not subject to forced refresh are the corresponding select MOSFETs.
When T is turned off and the corresponding plate line is at the ground potential V
By setting the SS to the non-selected state level, the stored data up to that point is continuously held.

Next, in step ST24, as shown in FIG. 13, the plate driver PD sets only the plate line P00 corresponding to the ferroelectric capacitor to be subjected to the forced refresh to the selection level of the internal voltage VO. . Further, the MOSFETs QF of the unit read / write circuits DRW0 to DRW7 of the read / write circuit RW are turned off, and the connection between the common data lines B0 to B7 and the corresponding sense amplifiers SA0 to SA7 becomes effective. In the memory array MARY, by setting the plate line P00 to the selection level of the internal voltage VO, for example, the polarization directions of the ferroelectric capacitors C000 and C030 and the like indicated by solid-line squares are inverted to store a logic "0". Other ferroelectric capacitors C010 and C020 are supposed to retain data.
Etc. retain the stored data of logic "0" as they are. Therefore, a current corresponding to the amount of charge transfer necessary for polarization reversal flows through the data lines D00 and D30, etc., that is, the common data lines B0 and B3, and the data lines D010 and D020, etc., that is, the common data lines B1 and B2, etc. Does not flow current. These read currents are converted into voltage signals by the corresponding sense amplifiers SA0 to SA7 of the read / write circuit RW, amplified, and determined as storage data of logic "1" or logic "0", and then the corresponding output latches. Held by OL0-OL7.

Memory blocks DB00 to DB07
In the ferroelectric capacitors coupled to the plate lines P01 to P0m, the corresponding plate line is set to the intermediate level of the internal voltage HVO, so that the polarization inversion does not occur and the read current does not flow. Further, in the ferroelectric capacitors forming the other memory blocks of the data memory DM, the corresponding selection MOSFET is turned off and the corresponding plate line is set to the non-selection level of the ground potential VSS. Do not shed.

The read data (DM) held by the corresponding output latches OL0 to OL7 of the read / write circuit RW is stored in the save memory S in step ST25.
It is written in the corresponding eight ferroelectric capacitors of M. At this time, the access counter control circuit CC counts up the number of accesses to the save memory SM and performs an overflow check in step ST26.

At step ST25, in the FRAM, as shown in FIG. 14, the X address decoder XD
Thus, the word line Ws corresponding to the save memory SM is set to the selection level of the internal voltage VW, and the other word lines W0 to W0.
Wp is set to the non-selection level of the ground potential VSS. Also,
In the plate driver PD, the ground potential VSS is supplied to the plate line Ps corresponding to the save memory SM, and the other plate lines P00 to P0m are ground potential V.
It is a non-selection level like SS. In the Y switch YS, eight data lines D00 to D70 are continuously selected and connected to the corresponding write amplifiers WA0 to WA7 of the read / write circuit RW via the common data lines B0 to B7. At this time, the input latches IL0 to IL7 have data feedback signal lines FB from the corresponding output latches OL0 to OL7.
Read data to be saved, that is, save data is transmitted via 0 to FB7, and the common data lines B0 to B7 are
Write signals corresponding to the save data are supplied from the corresponding write amplifiers WA0 to WA7. This write signal is at a high level of the internal voltage VO when the corresponding read data is at a logic "1", and is at an intermediate level of the internal voltage HVO when it is at a logic "0". As a result, the write signal output to the common data lines B0 and B3 and the like is set to the high level, that is, the internal voltage VO, and the write signal output to the common data lines B1 and B2 and the like is set to the intermediate level, that is, the internal voltage HVO. .

From these facts, in the save memory SM in which the storage data of logic "0" has been written in advance by the pre-writing in step ST22, the word line Ws is first set to the selection level to select all the selections including Qs00 to Qs70. The MOSFETs are turned on all at once. Further, the common data lines B0 and B3, that is, the data lines D00 and D30
Polarization inversion occurs in the ferroelectric capacitors Cs00 and Cs30 and the like to which a high-level write signal is supplied via, etc., and the held data is inverted from logic “0” to logic “1”. The ferroelectric capacitors Cs10 and Cs to which the intermediate level write signal is supplied via the common data lines B1 and B2 and the like, that is, the data lines D10 and D20 and the like.
At s10 and the like, polarization inversion does not occur, and the held data is left as logic "0". From the above, the memory array MA
The read data of the eight selected RY ferroelectric capacitors are saved and written to the corresponding eight ferroelectric capacitors of the save memory SM. Then, by repeating such a write operation in units of 8 bits, 8 × (n + 1) + (q + 1) to be the target of the forced refresh.
The saving of the data held in each ferroelectric capacitor is completed.

Upon completion of the save write of the held data, the target 8 × (n + 1) + is reached in step ST27.
The forced refresh for the (q + 1) ferroelectric capacitors is started. At this time, in the FRAM, as shown in FIG.
As shown in, the X address decoder XD selectively sets the word line W0 to the selection level of the internal voltage VW, and the other word lines W1 to Wp and Ws to the non-selection level of the ground potential VSS. Further, the plate driver PD sets the plate line P00 to a refresh voltage such as the internal voltage VP, and sets all other plate lines to the non-selection level of the ground potential VSS. And
In the Y switch YS, the MOSFETs Q1 to Q6 are turned on all at once in response to the high level of the internal control signal FM, and all the data lines D00 to D00 of the memory array MARY.
A low level of the ground potential VSS is supplied to D0n to D70 to D7n and DC0 to DCq.

As a result, a high voltage VP exceeding the write voltage VO is provided between both electrodes of the 8 × (n + 1) + (q + 1) ferroelectric capacitors coupled to the plate line P00.
As a result, a forced refresh for returning the spontaneous polarization lowered by the writing fatigue to the initial state is realized. In the ferroelectric capacitors that form the memory blocks DB00 to DB07 and DCB0 and are coupled to the plate lines P01 to P0m, the corresponding plate lines are set to the ground potential VSS, so that forced refresh is not performed, and the other memory blocks are not. In the ferroelectric capacitor constituting the above, the corresponding selection MOSFET is turned off and the corresponding plate line is set to the ground potential VSS, so that the forced refresh is not performed.

When the forced refresh of the target ferroelectric capacitor is completed, in step ST28, eight ferroelectric capacitors are selected from the save memory SM and precharge before reading the save data is performed.
In step ST29, the save data is read from these ferroelectric capacitors, and in step ST30, the read save data (SM) is rewritten to the data memory DM or the data memory access counter DC. Be seen. Then, such a series of operations is the target of the forced refresh, 8 × (n
8 for +1) + (q + 1) ferroelectric capacitors
The forced refresh mode is ended by repeating the operation in units. The precharge of the save memory SM and the save memory access counter SC in step ST28 is performed in the same manner as the precharge of the data memory DM and the data memory access counter DC in step ST23. Further, the save memory SM and the save memory access counter SC in step ST29
Is read by the same method as the reading of the data memory DM and the access counter DC for the data memory in step ST24, and the data memory DM and the access counter DC for the data memory in step ST30 are read.
Is written in the save memory S in step ST25.
It is performed in the same manner as the writing of the access counter SC for M and the save memory.

As shown in the above-mentioned embodiment, by applying the present invention to a semiconductor memory device such as an FRAM using a ferroelectric capacitor as a memory element and its forced refresh, the following effects can be obtained. To be That is, (1) an access counter provided in a semiconductor memory device such as an FRAM having a ferroelectric capacitor as a memory element for counting each plate line, and an access counter for counting the number of times the plate line is selected By providing an access counter control circuit that updates the count value of the access counter and identifies that the count value has reached a predetermined value.
Even when accesses to M or the like are concentrated at a specific address, the forced refresh is performed only on the ferroelectric capacitors that are frequently selected, and the forced refresh determination condition can be made substantially uniform.

(2) In the above item (1), the forced refresh is performed in units of a predetermined number of ferroelectric capacitors coupled to each plate line, thereby subdividing the forced refresh execution unit and the required The effect is that the time can be shortened. (3) In the above items (1) and (2), the save memory for temporarily saving the data held in the target ferroelectric capacitor at the time of forced refresh is configured by the ferroelectric capacitor. Even if the FRAM becomes large in scale and the time required for the forced refresh increases, it is possible to obtain an effect that the saved data can be prevented from being lost due to the power-off during the forced refresh. (4) According to the above items (1) to (3), it is possible to obtain the effect that the access efficiency of the FRAM and the like can be improved and the reliability thereof can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the microcomputer is not particularly required to be a single chip type, and its block configuration is not restricted by this embodiment. The start request of the forced refresh from the FRAM to the central processing unit CPU may be identified by, for example, so-called polling, or the refresh request signal R
The logic levels of the FQB and the refresh activation signal RF can also be set arbitrarily. If the program for forced refresh stored in the FRAM may be destroyed by the forced refresh, it may be read in advance to the random access memory RAM or the like, or a dedicated mask ROM is prepared. Good.

In FIG. 2, the FRAM memory array M
The ARY and the peripheral part can be divided into a plurality of memory mats. Further, the access counter D for the data memory
The C and the save memory access counter SC may be of a so-called countdown method, and the number of times of access may be determined by comparing and collating with a predetermined value. The access count for starting the forced refresh can be determined based on, for example, the access count of the FRAM as a whole, or can be determined for each divided memory mat, for example. The forced refresh can be performed in units of, for example, eight memory blocks connected to the same word line. In this case, the save memory SM needs to include m + 1 plate lines Ps0 to Psm and 8 × (n + 1) ferroelectric capacitors, as shown in FIG. And access counter SC for save memory
May be provided one by one corresponding to the word lines W0 to Wp or Ws.

On the other hand, in the memory array MARY, as shown in FIG. 17, the selection MOSFET Q and the ferroelectric capacitor C can be associated with each other in a one-to-one correspondence. In this case, the data memory access counter DC and the save memory access counter SC are provided corresponding to both the word line and the plate line, and the intermediate potential HV for reducing the stress of the non-selected ferroelectric capacitors.
O is also unnecessary. It goes without saying that the forced refresh is performed in units of (n + 1) + (q + 1) ferroelectric capacitors coupled to each word line or plate line. The FRAM can have any bit configuration such as so-called x1 bit or x16 bit, and the block configuration, the combination of the activation control signals, the potential relationship of each internal voltage, and the like can adopt various embodiments.

In FIG. 5, MOSFETs Q1 to Q6
May be provided in the memory array MARY. Also, each MOSFET can be replaced with a P-channel MOSFET, and P-channel and N-channel MO
It is also possible to replace it with a complementary gate formed by connecting SFETs in parallel. In FIG. 8, the access counter control circuit CC can have an arbitrary block configuration, and the overflow signal OF has an arbitrary logic level. In FIG. 10, the prewrite of the save memory SM may be performed immediately before the save write. Furthermore, the connection form in each step of FIGS. 11 to 15 can adopt a modified example within a range in which a predetermined condition is satisfied.

In the above description, the case where the invention made by the present inventor is mainly applied to the FRAM of the single-chip microcomputer which is the field of application which is the background of the invention has been described, but the present invention is not limited to this. , FRAM formed as a single unit or FRAM
It can also be applied to various digital integrated circuit devices having a built-in RAM. The present invention can be widely applied to at least a semiconductor memory device having a ferroelectric capacitor as a memory element and its forced refresh.

[0075]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a semiconductor memory device such as an FRAM having a ferroelectric capacitor as a memory element is provided corresponding to, for example, each word line or plate line, and an access counter for counting the number of times of selection and each word line or plate line. And an access counter control circuit for updating the count value of the corresponding access counter and for identifying that the value has reached a predetermined value, forcibly refreshing a predetermined value that is coupled to each word line or plate line. The FRAM is implemented by using a number of ferroelectric capacitors as a unit, and by configuring the save memory for temporarily saving the data held in the target ferroelectric capacitors at the time of forced refresh with the ferroelectric capacitors. Even when the access to etc. concentrates on a specific address, it is possible to select a ferroelectric capacitor that is frequently selected. The forced refresh is performed only by, it is possible to substantially equalize the determination condition for forced refresh, subdivide implementation unit of forced refresh, and shorten the time required, it is possible to increase the access efficiency of FRAM and the like. Further, even when the FRAM or the like becomes large in scale and the time required for the forced refresh increases, it is possible to prevent the saved data from being lost due to the power-off during the forced refresh and improve the reliability of the FRAM or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer including an FRAM to which the present invention is applied.

2 is a block diagram showing an embodiment of an FRAM included in the single chip microcomputer shown in FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of a memory array included in the FRAM of FIG.

FIG. 4 is another partial circuit diagram showing an embodiment of a memory array included in the FRAM of FIG.

5 is a circuit diagram showing an embodiment of a Y switch included in the FRAM of FIG.

FIG. 6 is a block diagram showing an embodiment of a read / write circuit included in the FRAM of FIG.

7 is a block diagram showing an embodiment of a unit read / write circuit included in the read / write circuit of FIG.

8 is a block diagram showing an embodiment of an access counter control circuit included in the FRAM of FIG.

9 is a processing flowchart showing an embodiment of the access counter control circuit of FIG.

10 is a process flow chart showing an embodiment of a forced refresh mode of the FRAM of FIG.

FIG. 11 is a connection diagram showing an example of a memory array in step ST22 of the forced refresh mode of FIG.

12 is a connection diagram showing an embodiment of a memory array in step ST23 of the forced refresh mode of FIG.

13 is a connection diagram showing an embodiment of a memory array in step ST24 of the forced refresh mode of FIG.

14 is a connection diagram showing an embodiment of a memory array in step ST25 of the forced refresh mode of FIG.

15 is a connection diagram showing an embodiment of a memory array in step ST27 of the forced refresh mode of FIG.

FIG. 16 is a circuit diagram showing a second embodiment of the memory array included in the FRAM of FIG.

FIG. 17 is a circuit diagram showing a third embodiment of the memory array included in the FRAM of FIG.

[Explanation of symbols]

CPU: Central processing unit, BUS ... Internal bus,
RAM ... Random access memory, FRAM ...
Ferroelectric RAM, TIM ... timer circuit, SCI ... serial communication interface, I / O ... input / output interface, A / D.
..Analog / digital conversion circuits. MARY ... memory array, DM ... data memory, SM ... save memory, DC ... data memory access counter,
SC: Access memory access counter, XD ...
X address decoder, PD ... Plate driver, X
B ... X address buffer, YS ... Y switch,
YD ... Y address decoder, YB ... Y address buffer, RW ... Read / write circuit, CC ... Access counter control circuit, OB ... Data output buffer, IB ... Data input buffer, VG ... Internal voltage generation circuit, TC ... Timing control circuit. DB00
~ DB07 to DBp0 to DBp7, SB0 to SB
7, DCB0 to DCBp, SCB ... Memory block, W0 to Wp, Ws ... Word line, P00 to P0m
To Pp0 to Ppm, Ps ... plate line, D00
~ D0n to D70 to D7n, DC0 to DCq ...
Data lines, d000-d00n to d070-d07n
To dp00 to dp0n to dp70 to dp7n, d
From c00 to dc0q to dcp0 to dcpq, ds00 to
ds0n to ds70 to ds7n ... Sub data line,
C, C000 to C00m to C070 to C07m to Cp00 to Cp0m to Cp70 to Cp7m ... Ferroelectric capacitor, Q, Q000 to Q00m to Q070
From Q07m to Qp00 to Qp0m to Qp70 to Q
p7m, Q1 to QQ ... N-channel MOSFET.
B0 to B7 ... Common data lines. DRW0 to DRW7,
CRW0 to CRWq ... Unit read / write circuit, SA
0-SA7 ... sense amplifier, WA0-WA7 ...
Write amplifier, IL0 to IL7 ... Input latch, OL
0-OL7 ... Output latch. +1 ... Count-up circuit, OFD ... Overflow detection circuit. W0-W
m, Ws ... Word line, P0-Pm, Ps ... Plate line, D0-Dn, DC0-DCq ... Data line.

Claims (8)

[Claims] 1. A semiconductor memory device comprising a memory array having a ferroelectric capacitor as a storage element, and forcibly refreshing the ferroelectric capacitor when the number of times of access reaches a predetermined value. 2. The semiconductor device according to claim 1, wherein the forced refresh is performed by applying a predetermined high voltage exceeding a write voltage between both electrodes of a target ferroelectric capacitor. Storage device. 3. The forced refresh is performed in units of a predetermined number of ferroelectric capacitors coupled to each word line or plate line of the memory array, and the semiconductor memory device has each word line. Alternatively, an access counter control circuit for updating the access counter provided for the plate line and the access counter for the selected word line or plate line and discriminating that the count value has reached a predetermined value And a save memory for temporarily saving the data held in a predetermined number of ferroelectric capacitors coupled to the word line or plate line to be forcibly refreshed. The semiconductor memory device according to claim 1 or 2. 4. The escape memory uses a ferroelectric capacitor as a storage element.
Semiconductor memory device. 5. Each of the word lines is coupled to the gates of a corresponding predetermined number of select MOSFETs, the source of these select MOSFETs having one electrode coupled to the corresponding plate line. Each done 1
4. The other electrode of each ferroelectric capacitor is coupled to the other ferroelectric capacitor, claim 1, claim 2, claim 3
Alternatively, the semiconductor memory device according to claim 4. 6. Each of the word lines is coupled to a gate of a corresponding predetermined number of select MOSFETs, the source of each of the select MOSFETs having one of its electrodes connected to a corresponding plate line. 3. The other electrode of each of a plurality of ferroelectric capacitors to be coupled is coupled to each other.
The semiconductor memory device according to claim 3 or 4. 7. The semiconductor memory device is included in a single-chip microcomputer, the forced refresh is started in response to an instruction from the central processing unit, and the semiconductor memory device comprises: 4. When the count value of the access counter reaches a predetermined value, the central processing unit is interrupted to request the start of forced refresh.
The semiconductor memory device according to claim 4, claim 5, or claim 6. 8. A data memory that uses a ferroelectric capacitor as a storage element to hold normal storage data, and a data memory that uses a ferroelectric capacitor as a storage element and temporarily holds the storage data of the target storage element when the data memory section is forcibly refreshed. A semiconductor memory device comprising: a save memory for temporarily saving.