JPH0772510A - Active matrix liquid crystal display - Google Patents
Active matrix liquid crystal displayInfo
- Publication number
- JPH0772510A JPH0772510A JP22187393A JP22187393A JPH0772510A JP H0772510 A JPH0772510 A JP H0772510A JP 22187393 A JP22187393 A JP 22187393A JP 22187393 A JP22187393 A JP 22187393A JP H0772510 A JPH0772510 A JP H0772510A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- liquid crystal
- drain
- gate
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜トランジスタ（ＴＦ
Ｔ）によって駆動するアクティブマトリクス型液晶表示
装置に関する。BACKGROUND OF THE INVENTION The present invention relates to a thin film transistor (TF).
The present invention relates to an active matrix type liquid crystal display device driven by T).
【０００２】[0002]
【従来の技術】性能価格比が高い、ＴＦＴ駆動方式のア
クティブマトリクス型液晶ディスプレイ（ＬＣＤ）装置
の要求が強まっている。2. Description of the Related Art There is an increasing demand for an active matrix type liquid crystal display (LCD) device of a TFT driving system having a high performance price ratio.
【０００３】この実現のためには、アモルファスシリコ
ン（ａ−Ｓｉ）を適用したＴＦＴ−ＬＣＤの製造プロセ
スコストの低減、すなわち製造工程数の低減、スループ
ットの向上及び歩留まりの向上等を実現すると共に、大
型、高精細及び多階調表示等の高性能化を図ることが必
要である。このような目的のため、特公平４−２６０８
４号公報では、絶縁基板上に被着された透明電極膜から
なる第１導電膜により形成された複数本の列選択線、各
列選択線と一体のドレイン電極、各画素位置に配列され
た表示画素電極及びこれと一体のソース電極と、これら
ドレイン、ソース電極上にまたがるように形成された半
導体膜と、この半導体膜上にゲート絶縁膜を介して被着
された第２層導電膜により形成された複数本の行選択線
及びこれと一体のゲート電極とを備え、前記半導体膜及
びゲート絶縁膜は前記行選択線及びこれと一体のゲート
電極と同一形状にパターニングされているアクティブマ
トリクス型表示装置が提案されている。このような構造
にすることによって、製造工程の簡略化を図ると共に、
電極配線の断切れを防止して信頼性向上及び歩留まりの
向上を図っている。In order to realize this, the manufacturing process cost of the TFT-LCD using amorphous silicon (a-Si) is reduced, that is, the number of manufacturing steps is reduced, the throughput is improved, and the yield is improved. It is necessary to improve performance such as large size, high definition and multi-gradation display. For this purpose, Japanese Examined Patent Publication 4-2608
In Japanese Patent Laid-Open No. 4 (1994), a plurality of column selection lines formed of a first conductive film made of a transparent electrode film deposited on an insulating substrate, a drain electrode integrated with each column selection line, and arranged at each pixel position. The display pixel electrode and the source electrode integrated therewith, the semiconductor film formed over the drain and source electrodes, and the second-layer conductive film deposited on the semiconductor film via the gate insulating film. An active matrix type having a plurality of formed row selection lines and a gate electrode integrated therewith, wherein the semiconductor film and the gate insulating film are patterned in the same shape as the row selection lines and the gate electrode integrated with the same. Display devices have been proposed. This structure simplifies the manufacturing process, and
The disconnection of the electrode wiring is prevented to improve reliability and yield.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来技術によ
る素子構造では、製造工程の簡略化には有効であるもの
ゝ、大型，高精細及び多階調表示等の高性能化について
の対策が十分とは云えなかった。また歩留まりが低く価
格の低減化が困難であった。However, in the device structure according to the prior art, it is effective for simplifying the manufacturing process, and sufficient measures are taken for high performance such as large size, high definition and multi-gradation display. I couldn't say that. Moreover, the yield is low and it is difficult to reduce the price.
【０００５】本発明の目的は、簡略な工程で製造できる
と共に、高歩留まりで、かつ、大型，高精細及び多階調
表示等の高性能化を指向したＴＦＴ駆動方式のアクティ
ブマトリクス型液晶表示装置を提供することにある。An object of the present invention is a TFT drive type active matrix type liquid crystal display device which can be manufactured by a simple process and has a high yield and is aimed at high performance such as large size, high definition and multi-gradation display. To provide.
【０００６】[0006]
【課題を解決するための手段】前記課題を解決する本発
明の要旨は次のとおりである。Means for Solving the Problems The gist of the present invention for solving the above problems is as follows.
【０００７】（１） 一方の絶縁基板上に互いに直交す
るゲート配線及びドレーン配線が複数配設され、前記ゲ
ート配線とドレーン配線の交差部は互いに電気的に絶縁
されており、前記各交差部の近傍には薄膜トランジスタ
がそれぞれ配置され、各薄膜トランジスタのソース電極
はその近傍に設けられた各透明画素電極に、ドレーン電
極は前記ドレーン配線にそれぞれ接続され、また、前記
各薄膜トランジスタのゲート電極は前記ゲート配線にそ
れぞれ接続されており、これらは前記絶縁基板も含めて
配向膜または保護性絶縁膜及び配向膜で被覆されてお
り、該絶縁基板と対向して配置されたもう一方の透明絶
縁基板上には前記透明画素電極に対向して設けられた透
明電極と配向膜とを有し、前記２枚の絶縁基板間には液
晶が挾持されており、前記ゲート配線，ドレーン配線及
び対向する透明絶縁基板上の透明電極は外部の液晶駆動
回路に接続されているアクティブマトリクス型液晶表示
装置において、前記ドレーン配線及び前記薄膜トランジ
スタのドレーン電極及びソース電極は前記透明画素電極
と同一材料で形成されており、前記透明画素電極の膜厚
をドレーン配線部分より薄く構成したことを特徴とする
アクティブマトリクス型液晶表示装置にある。(1) A plurality of gate wirings and drain wirings which are orthogonal to each other are arranged on one insulating substrate, and intersections of the gate wirings and drain wirings are electrically insulated from each other, and Thin film transistors are arranged in the vicinity, the source electrode of each thin film transistor is connected to each transparent pixel electrode provided in the vicinity thereof, the drain electrode is connected to the drain wiring, and the gate electrode of each thin film transistor is the gate wiring. Are respectively covered with an alignment film or a protective insulating film and an alignment film including the insulating substrate, and on the other transparent insulating substrate arranged facing the insulating substrate, A transparent electrode provided to face the transparent pixel electrode and an alignment film, and a liquid crystal sandwiched between the two insulating substrates. In the active matrix liquid crystal display device, the gate wiring, the drain wiring, and the transparent electrodes on the opposing transparent insulating substrate are connected to an external liquid crystal driving circuit. In the active matrix type liquid crystal display device, the drain wiring and the drain electrode and the source electrode of the thin film transistor are transparent. The active matrix liquid crystal display device is characterized in that it is formed of the same material as the pixel electrode, and the film thickness of the transparent pixel electrode is thinner than that of the drain wiring portion.
【０００８】（２） 前記ドレーン配線、前記薄膜トラ
ンジスタのドレーン電極及びソース電極、並びに前記透
明画素電極は順テーパ端面を有し、かつそのテーパ角は
３０°以下であること。(2) The drain wiring, the drain electrode and the source electrode of the thin film transistor, and the transparent pixel electrode have a forward tapered end face, and the taper angle is 30 ° or less.
【０００９】（３） 前記薄膜トランジスタはドレーン
電極及びソース電極上に跨って形成された半導体層，ゲ
ート絶縁層，ゲート電極から構成され、前記半導体層と
ゲート絶縁層の積層部のパターンと前記ゲート電極パタ
ーンとは同一中心線上あり、かつ、中心線の左右のパタ
ーンが対称となるように形成されていること。(3) The thin film transistor is composed of a semiconductor layer, a gate insulating layer, and a gate electrode formed over a drain electrode and a source electrode, and a pattern of a laminated portion of the semiconductor layer and the gate insulating layer and the gate electrode. The pattern is on the same center line, and the patterns on the left and right of the center line are symmetrical.
【００１０】（４） 前記半導体層とゲート絶縁層の積
層部のパターン幅はゲート電極層が半導体層のパターン
幅より大きく、その両者の差は０.２〜５μｍであるこ
と。(4) The pattern width of the laminated portion of the semiconductor layer and the gate insulating layer is larger than the pattern width of the semiconductor layer of the gate electrode layer, and the difference between them is 0.2 to 5 μm.
【００１１】（５） 前記絶縁基板を被覆する保護性絶
縁膜は、前記透明画素電極上に該透明画素電極の寸法よ
りも大きくない寸法の貫通孔を有し、該貫通孔の平面パ
ターンは、前記ドレーン配線，前記薄膜トランジスタを
構成するドレーン電極及びソース電極と前記透明画素電
極との膜厚段差部の平面パターンとほぼ一致するよう形
成されていること。(5) The protective insulating film covering the insulating substrate has a through hole on the transparent pixel electrode, the through hole having a size not larger than the size of the transparent pixel electrode, and the plane pattern of the through hole is: The drain wiring, the drain electrode and the source electrode forming the thin film transistor, and the transparent pixel electrode are formed so as to substantially match the plane pattern of the film thickness step portion.
【００１２】（６） 前記ドレーン配線，前記薄膜トラ
ンジスタのドレーン電極及びソース電極と、前記透明画
素電極との膜厚段差部の平面パターンは、前記薄膜トラ
ンジスタの半導体層とゲート絶縁層との積層部の平面パ
ターンとほぼ一致するよう形成されていること。(6) A plane pattern of a film thickness step portion between the drain wiring, the drain electrode and source electrode of the thin film transistor, and the transparent pixel electrode is a plane of a laminated portion of the semiconductor layer and the gate insulating layer of the thin film transistor. Be formed so that it almost matches the pattern.
【００１３】（７） 前記ゲート配線及びドレーン配線
を形成する透明導電膜のシート抵抗は５Ω／□以下であ
ること。(7) The sheet resistance of the transparent conductive film forming the gate wiring and the drain wiring is 5Ω / □ or less.
【００１４】（８） 前記透明画素電極の透過率は波長
５５０ｎｍの照射光に対して８５％以上であること。(8) The transmittance of the transparent pixel electrode is 85% or more for irradiation light having a wavelength of 550 nm.
【００１５】（９） 前記ゲート電極はＡｌまたはＴａ
を主体とする金属材料からなり、該電極の表面と端面は
該電極材料の陽極酸化膜で被覆されていること。(9) The gate electrode is Al or Ta
And a surface of the electrode are covered with an anodic oxide film of the electrode material.
【００１６】[0016]
【作用】従来素子構造では構造を単純化するため、ドレ
ーン配線（ドレーン電極）膜材料としてソース電極及び
画素電極と同一のＩＴＯ（Ｉndium Ｔin Ｏxide）が用
いられていた。そして、その膜厚は透過率の確保及びソ
ース・ドレーン電極端面段差部のカバレージを考慮して
１００〜２００ｎｍ程度とするのが通例であった。In the conventional device structure, in order to simplify the structure, the same ITO (Indium Tin Oxide) as the source electrode and the pixel electrode is used as the material of the drain wiring (drain electrode) film. The film thickness is usually set to about 100 to 200 nm in consideration of ensuring the transmittance and the coverage of the source / drain electrode end face step portion.
【００１７】しかし、この場合のＩＴＯ膜のシート抵抗
は１０〜２０Ω／□以上となり、ドレーン電圧パルスの
立上り時間遅延を引き起こすために書き込み率が低下
し、パネルの大型化及び高精細化には限界があった。具
体的に見積もった結果、ＶＧＡクラス（ドット数６４０
×４８０、６４階調）に対しシート抵抗が２０Ω／□で
は対角７〜８インチ、１０Ω／□で対角１０インチが最
大であることが分かった。However, the sheet resistance of the ITO film in this case is 10 to 20 Ω / □ or more, and the writing rate is lowered due to the rise time delay of the drain voltage pulse, and there is a limit to the enlargement and high definition of the panel. was there. As a result of specific estimation, VGA class (dot number 640
It was found that when the sheet resistance was 20 Ω / □, the diagonal was 7 to 8 inches, and 10 Ω / □ was 10 inches.
【００１８】上記のドレーンパルスの立上り時間遅延に
よる問題を解決し、大型，高精細及び多階調表示等を可
能にするためには、シミュレーションによる検討の結果
では、ドレーン配線のシート抵抗を５Ω／□以下とする
ことが必要なことが分かった。In order to solve the above-mentioned problem caused by the rise time delay of the drain pulse and enable large-scale, high-definition and multi-gradation display, the result of examination by simulation shows that the sheet resistance of the drain wiring is 5Ω / □ We found that the following was necessary.
【００１９】このようにすることにより、ＸＧＡクラス
（１０２４×７６８、６４階調）の対角１１インチクラ
ス以上をカバーできる。By doing so, an XGA class (1024 × 768, 64 gradations) diagonal 11-inch class or more can be covered.
【００２０】ドレーン配線として金属配線を用いる場合
にはシート抵抗５Ω／□以下の実現は問題なかった。し
かし、ＩＴＯを用いてシート抵抗５Ω／□以下にするに
は、膜厚は４００ｎｍ以上が必要なため、画素電極の透
過率が８０％以下（照射光：５５０ｎｍ）に低下してし
まう。そこで、本発明では画素電極部分の膜厚をドレー
ン配線部分より薄くすることにより解決した。When metal wiring was used as the drain wiring, there was no problem in achieving a sheet resistance of 5Ω / □ or less. However, in order to reduce the sheet resistance to 5 Ω / □ or less using ITO, the film thickness needs to be 400 nm or more, so the transmittance of the pixel electrode is reduced to 80% or less (irradiation light: 550 nm). Therefore, the present invention has solved the problem by making the film thickness of the pixel electrode portion thinner than that of the drain wiring portion.
【００２１】また、本発明者らは、従来の素子構造につ
いて詳細に検討した結果、歩留まり低下の最大要因は、
ゲート電極とドレーン電極間でのショートあるいはリー
クにあることをつきとめた。これを図５に示す従来型素
子の模式図で説明する。Further, as a result of detailed examination of the conventional element structure, the present inventors found that the largest factor of the yield reduction is
It was found that there was a short circuit or a leak between the gate electrode and the drain electrode. This will be described with reference to the schematic view of the conventional device shown in FIG.
【００２２】ガラス基板１上には、透明ＩＴＯからなる
ソース・ドレーン電極２と画素電極１１が形成され、こ
れらに跨ってａ−Ｓｉ：Ｈの半導体層３、ゲート絶縁層
４及びゲート電極５が形成されている。A source / drain electrode 2 made of transparent ITO and a pixel electrode 11 are formed on a glass substrate 1, and an a-Si: H semiconductor layer 3, a gate insulating layer 4 and a gate electrode 5 are provided over the source / drain electrode 2 and the pixel electrode 11. Has been formed.
【００２３】ショートあるいはリークの原因の一つは、
透明ＩＴＯからなるソース・ドレーン電極２上に積層さ
れたａ−Ｓｉ：Ｈの半導体層３とゲート絶縁層４の端面
に沿った経路（図中ａ）によるもの、もう一つはソース
・ドレーン電極２端面の段さ部上に積層された半導体層
３、ゲート絶縁層４の膜厚の低い部分を通過するもの
（図中ｂ）であった。前者の原因に対しては、半導体層
３、ゲート絶縁層４のパターンに対し、ゲート電極５を
後退させておくことが有効である。これを実現するに
は、ゲート電極５のパターンを半導体層３，ゲート絶縁
層４のパターンより小さくすればよい。One of the causes of short circuit or leakage is
By a path (a in the figure) along the end faces of the semiconductor layer 3 of a-Si: H and the gate insulating layer 4 laminated on the source / drain electrode 2 made of transparent ITO, the other is the source / drain electrode The semiconductor layer 3 and the gate insulating layer 4 laminated on the stepped portion of the two end faces pass through the low-thickness portions (b in the figure). Regarding the former cause, it is effective to retract the gate electrode 5 with respect to the patterns of the semiconductor layer 3 and the gate insulating layer 4. To achieve this, the pattern of the gate electrode 5 may be made smaller than the pattern of the semiconductor layer 3 and the gate insulating layer 4.
【００２４】しかし、ホトリソグラフィー及びエッチン
グで幅の小さなゲート電極パターンを形成する方法では
工程数が増加してしまい、工程簡略化という目的に反す
る。そこで、半導体層３、ゲート絶縁層４及びゲート電
極５の積層部をパターニングする際、ゲート電極５を後
退エッチする方法が考えられる。しかし、その後退量を
検討した結果、ゲート電極５を単に後退するだけでな
く、後退量を０.２μｍ以上にする必要があることが分
かった。また、後退量を５μｍよりも大きくすると電極
幅が狭くなり過ぎ、技術的にも困難である。However, the number of steps is increased in the method of forming a gate electrode pattern having a small width by photolithography and etching, which is against the purpose of simplifying the steps. Therefore, when patterning the stacked portion of the semiconductor layer 3, the gate insulating layer 4, and the gate electrode 5, a method of receding the gate electrode 5 may be considered. However, as a result of examining the amount of recession, it was found that not only the gate electrode 5 should be recessed, but also the amount of recession should be 0.2 μm or more. Further, if the receding amount is larger than 5 μm, the electrode width becomes too narrow, which is technically difficult.
【００２５】また、ゲート電極５の材料をＡｌまたはＴ
ａを主体とする金属材料で構成し、電極層表面及び端面
をＡｌ2Ｏ3またはＴａ2Ｏ5膜を陽極酸化法で形成するこ
とによって対策できる。The material of the gate electrode 5 is Al or T.
The countermeasure can be taken by using a metal material mainly composed of a and forming an Al 2 O 3 or Ta 2 O 5 film on the surface and end face of the electrode layer by an anodic oxidation method.
【００２６】一方、後者の問題は、膜厚が４００ｎｍ以
上と厚いＩＴＯ膜をソース・ドレーン電極２として用い
た場合に顕著に生じるが、これに対する解決策は、ソー
ス・ドレーン電極２の端面に順テーパを形成することが
効果的であった。このようにするとソース・ドレーン電
極２の端面の段差部上に積層された半導体層３，ゲート
絶縁層４のカバレージが向上して、その部分の膜質が改
善される。なお、好ましくはソース・ドレーン電極端面
の順テーパのテーパ角は３０°以下がよいことが分かっ
た。On the other hand, the latter problem remarkably occurs when an ITO film having a thickness of 400 nm or more is used as the source / drain electrode 2, but a solution to this problem is applied to the end face of the source / drain electrode 2. Forming a taper was effective. By doing so, the coverage of the semiconductor layer 3 and the gate insulating layer 4 laminated on the stepped portion of the end face of the source / drain electrode 2 is improved, and the film quality of that portion is improved. It has been found that the taper angle of the forward taper of the end face of the source / drain electrode is preferably 30 ° or less.
【００２７】上記により、工程数をほとんど増すことな
く、ゲート電極５とソース・ドレーン電極間のショート
あるいはリークを抑制することができ、結果的に素子の
歩留まりを向上することができる。With the above, it is possible to suppress a short circuit or a leak between the gate electrode 5 and the source / drain electrode with almost no increase in the number of steps, and as a result, it is possible to improve the device yield.
【００２８】製造工程を簡略化する目的に対して、本発
明では次の手段を採用している。すなわち、前記絶縁基
板を被覆する保護性絶縁膜は、透明画素電極上に透明画
素電極の寸法より小さい貫通孔を有し、該貫通孔の平面
パターンは、前記ドレーン配線及び薄膜トランジスタを
構成するドレーン電極及びソース電極と前記透明画素電
極との膜厚段差部の平面パターンとほぼ一致するように
形成する。For the purpose of simplifying the manufacturing process, the present invention employs the following means. That is, the protective insulating film that covers the insulating substrate has a through hole that is smaller than the size of the transparent pixel electrode on the transparent pixel electrode, and the planar pattern of the through hole is a drain electrode that forms the drain wiring and the thin film transistor. And the source electrode and the transparent pixel electrode are formed so as to substantially coincide with the plane pattern of the film thickness step portion.
【００２９】これによって、透明電極ＩＴＯのドレーン
配線及びソース・ドレーン電極部分に対して画素電極部
分の膜厚を薄くするための専用マスクパターンによるホ
トリソグラフィ工程が不要となり、保護性絶縁膜に貫通
孔を形成するのと同一のマスクパターンを用いるホトリ
ソグラフィ工程でＩＴＯの加工が可能となる。This eliminates the need for a photolithography process using a dedicated mask pattern for reducing the film thickness of the pixel electrode portion with respect to the drain wiring and the source / drain electrode portion of the transparent electrode ITO, and the through hole is formed in the protective insulating film. The ITO can be processed in the photolithography process using the same mask pattern as that for forming the ITO.
【００３０】[0030]
【実施例】本発明を実施例に基づき具体的に説明する。EXAMPLES The present invention will be specifically described based on examples.
【００３１】〔実施例 １〕作製したＴＦＴ素子の断面
模式図を図１に示す。この図を用い本発明のＴＦＴ素子
の作製方法を説明する。Example 1 FIG. 1 is a schematic sectional view of the manufactured TFT element. A method for manufacturing the TFT device of the present invention will be described with reference to this drawing.
【００３２】よく洗浄したガラス基板１上にマグネトロ
ンスパッタリング法を用いて基板温度３００℃で膜厚４
００ｎｍのＩＴＯ膜２を形成した。該ＩＴＯ膜のシート
抵抗は５Ω／□であることを確認した。On a glass substrate 1 that has been thoroughly washed, a film thickness of 4 is obtained at a substrate temperature of 300 ° C. by using a magnetron sputtering method.
The ITO film 2 having a thickness of 00 nm was formed. It was confirmed that the sheet resistance of the ITO film was 5Ω / □.
【００３３】このＩＴＯ膜２をホトエッチング法によっ
てソース・ドレーン配線及び電極に加工した。エッチン
グレジストにはポジ型ホトレジストを用い、エッチング
液としてＨＢｒ（またはＦｅＣｌ3でもよい）にＨＣｌ
を適量添加した水溶液を用い、５０〜６０℃でエッチン
グした。得られたＩＴＯ膜の端部の順テーパ角は１０°
であった。This ITO film 2 was processed into a source / drain wiring and an electrode by a photoetching method. A positive photoresist is used as an etching resist, and HBr (or FeCl 3 may be used) as an etching solution is added to HCl.
Etching was performed at 50 to 60 ° C. using an aqueous solution to which an appropriate amount of was added. The forward taper angle of the edge of the obtained ITO film was 10 °
Met.
【００３４】次に、上記の基板をＲＦプラズマＣＶＤ装
置に設置し、まずＩＴＯ電極とのコンタクトをとるため
ＰＨ3プラズマ処理を加えた後、半導体層のａ−Ｓｉ：
Ｈ膜３を形成した。基板温度は２５０℃とし、ＳｉＨ4
及びＨ2の混合ガスを原料ガスとして用い膜厚１８ｎｍ
のものが得られた。次いで、同一チャンバ内でこの上に
ゲート絶縁膜４のＳｉＮ層を形成した。基板温度は活性
層と同じ２５０℃としＳｉＨ4、ＮＨ3及びＮ2の混合ガ
スを原料ガスとし、３００ｎｍの膜厚に作製した。Next, the above substrate is placed in an RF plasma CVD apparatus, and PH 3 plasma treatment is first performed to make contact with the ITO electrode, and then a-Si of the semiconductor layer:
The H film 3 was formed. Substrate temperature is 250 ° C. and SiH 4
And a mixed gas of H 2 are used as a source gas, and the film thickness is 18 nm.
I got that. Then, the SiN layer of the gate insulating film 4 was formed on this in the same chamber. The substrate temperature was set to 250 ° C., which was the same as that of the active layer, and a mixed gas of SiH 4 , NH 3 and N 2 was used as a raw material gas to form a film having a thickness of 300 nm.
【００３５】次に、ゲート電極５としてマグネトロンス
パッタリング法で、基板温度１００℃、膜厚２５０ｎｍ
のＡｌ膜を形成した。この後、ホトリソグラフィーによ
ってゲート電極、活性層及びゲート絶縁膜をパターニン
グした。その際、最初にＡｌ電極をリン酸，酢酸及び硝
酸の混合水溶液を用いてオーバエッチングによりレジス
トパターン端部より後退させ、次いで、ドライエッチン
グ法によって活性層及びゲート絶縁膜をパターニングし
た。Next, the gate electrode 5 is formed by a magnetron sputtering method at a substrate temperature of 100 ° C. and a film thickness of 250 nm.
Al film was formed. After that, the gate electrode, the active layer and the gate insulating film were patterned by photolithography. At that time, the Al electrode was first set back from the end of the resist pattern by over-etching using a mixed aqueous solution of phosphoric acid, acetic acid and nitric acid, and then the active layer and the gate insulating film were patterned by the dry etching method.
【００３６】上記をＳＥＭで測定した結果、ゲート電極
Ａｌの活性層及びゲート絶縁膜のパターン幅に対する後
退量は片側約１.５μｍであった。この上に保護膜６を
ＲＦプラズマＣＶＤ法によって形成後、画素電極パター
ン上に貫通孔を形成し、引き続いて同一マスクパターン
を用いてＩＴＯ膜２をエッチングした。As a result of measuring the above with SEM, the amount of recession of the gate electrode Al with respect to the pattern width of the active layer and the gate insulating film was about 1.5 μm on each side. After forming the protective film 6 on this by the RF plasma CVD method, a through hole was formed on the pixel electrode pattern, and subsequently, the ITO film 2 was etched using the same mask pattern.
【００３７】本実施例では画素電極部分の膜厚を約１５
０ｎｍに調節した。これによって、ほぼ９０％の透過率
を確保できることが分かった。作製した素子の平面パタ
ーンの部分模式図を図２に示す。７はドレーン線、８は
ソース電極、９はＳｉＮ／ａ−Ｓｉ：Ｈ積層部、１０は
ゲート線、及び破線で囲まれた斜線部分１１は画素電極
すなわち保護膜貫通孔である。In this embodiment, the film thickness of the pixel electrode portion is about 15
It was adjusted to 0 nm. It has been found that this makes it possible to secure a transmittance of approximately 90%. FIG. 2 shows a partial schematic view of a plane pattern of the manufactured device. Reference numeral 7 is a drain line, 8 is a source electrode, 9 is a SiN / a-Si: H laminated portion, 10 is a gate line, and a shaded portion 11 surrounded by a broken line is a pixel electrode, that is, a protective film through hole.
【００３８】〔実施例 ２〕図３に本実施例で作製した
ＴＦＴ素子の断面模式図を示す。これと図１との相違点
は、図１におけるゲート電極５のＡｌ表面及び端面に表
面酸化膜１２としてＡｌ2Ｏ3が形成されている点であ
る。このＡｌ2Ｏ3膜は以下に説明する陽極化成法で作製
した。[Embodiment 2] FIG. 3 shows a schematic cross-sectional view of a TFT element manufactured in this embodiment. The difference between this and FIG. 1 is that Al 2 O 3 is formed as the surface oxide film 12 on the Al surface and the end surface of the gate electrode 5 in FIG. This Al 2 O 3 film was produced by the anodization method described below.
【００３９】実施例１と同じ方法で作製した素子のゲー
ト電極をつなぎ合わせて化成端子として取り出し、それ
を陽極とした。対向電極（陰極）にはＰｔ製電極を用い
た。陽極化成液には、酒石酸水溶液をエチレングリコー
ルで希釈しアンモニアでｐＨ調整したものを用いた。所
定の化成電圧を印加して陽極化成し、１５０ｎｍのＡｌ
2Ｏ3膜を形成した。The gate electrode of the device manufactured by the same method as in Example 1 was connected and taken out as a chemical conversion terminal, which was used as an anode. A Pt electrode was used as the counter electrode (cathode). The anodizing solution used was an aqueous tartaric acid solution diluted with ethylene glycol and adjusted in pH with ammonia. A predetermined formation voltage is applied and anodization is performed.
A 2 O 3 film was formed.
【００４０】〔実施例 ３〕図４に本実施例で作製した
ＴＦＴ素子の平面パターンの部分模式図を示す。この図
と図２に示す実施例１の平面パターンとの相違点は、ド
レーン配線７の上に一部を残してＳｉＮ／ａ−Ｓｉ：Ｈ
積層部９’、Ａｌ膜（ゲート線と同層）１０’が形成さ
れていること、Ａｌ膜表面及び端部には陽極化成による
Ａｌ2Ｏ3膜が形成されており、この部分及びＳｉＮ／ａ
−Ｓｉ：Ｈ積層部９、ゲート線１０以外の部分のＩＴＯ
電極の膜厚が薄くなっている点にある。すなわち、この
場合にはＩＴＯ膜の段差は、保護膜の貫通孔に対応させ
たものでなく、ＳｉＮ／ａ−Ｓｉ：Ｈ積層部パターンに
ほぼ一致している。[Embodiment 3] FIG. 4 shows a partial schematic view of a plane pattern of a TFT device manufactured in this embodiment. The difference between this figure and the plane pattern of the first embodiment shown in FIG. 2 is that SiN / a-Si: H is left on the drain wiring 7 partially.
The laminated portion 9 ', the Al film (the same layer as the gate line) 10' are formed, and the Al 2 O 3 film by anodization is formed on the surface and the end portion of the Al film. a
-Si: H laminated portion 9 and ITO other than the gate line 10
The point is that the film thickness of the electrode is thin. That is, in this case, the step of the ITO film does not correspond to the through hole of the protective film, but substantially corresponds to the SiN / a-Si: H laminated portion pattern.
【００４１】本実施例では保護膜には有機樹脂膜を用い
貫通孔は設けなかった。これによっても製造工程の簡略
化と云う目的も達成することができる。In this example, an organic resin film was used as the protective film and no through hole was provided. This also makes it possible to achieve the purpose of simplifying the manufacturing process.
【００４２】以上の実施例で作製したＴＦＴ素子の特性
を、多数の素子で評価した結果、全て１２.５インチ対
角のＸＧＡ（１０２４×７６８）クラスに適用可能な書
き込み特性を示し、ゲート・ドレーン間のリークがない
ことを確認した。As a result of evaluating the characteristics of the TFT element manufactured in the above-mentioned examples with a large number of elements, all show the writing characteristics applicable to the 12.5 inch diagonal XGA (1024 × 768) class, and the gate. It was confirmed that there was no leak between drains.
【００４３】[0043]
【発明の効果】本発明によれば、作製工程が簡略で、ド
レーン配線抵抗を低減できると共にゲート・ドレーン間
のリークを抑制できる。従って、ＴＦＴ−ＬＣＤの低コ
スト化及び高性能化を実現することができる。According to the present invention, the manufacturing process can be simplified, the drain wiring resistance can be reduced, and the leakage between the gate and the drain can be suppressed. Therefore, cost reduction and high performance of the TFT-LCD can be realized.
【図１】実施例１によるアクティブマトリクス型液晶表
示装置のＴＦＴ素子の断面模式図である。FIG. 1 is a schematic sectional view of a TFT element of an active matrix liquid crystal display device according to a first embodiment.
【図２】実施例１によるアクティブマトリクス型液晶表
示装置のＴＦＴ素子の平面パターンの部分模式図であ
る。2 is a partial schematic view of a plane pattern of a TFT element of the active matrix type liquid crystal display device according to Example 1. FIG.
【図３】実施例２によるアクティブマトリクス型液晶表
示装置のＴＦＴ素子の断面模式図である。FIG. 3 is a schematic sectional view of a TFT element of an active matrix liquid crystal display device according to a second embodiment.
【図４】実施例３よるアクティブマトリクス型液晶表示
装置のＴＦＴ素子の平面パターンの部分模式図である。FIG. 4 is a partial schematic diagram of a plane pattern of a TFT element of an active matrix type liquid crystal display device according to a third embodiment.
【図５】従来技術によるＴＦＴ素子の断面模式図であ
る。FIG. 5 is a schematic cross-sectional view of a TFT element according to a conventional technique.
１…ガラス基板、２…ＩＴＯ膜、３…ａ−Ｓｉ：Ｈ膜の
半導体層、４…ゲート絶縁膜、５…ゲート電極、６…保
護膜、７…ドレーン線、８…ソース電極、９…ＳｉＮ／
ａ−Ｓｉ：Ｈ積層部、９’…ドレーン線上のＳｉＮ／ａ
−Ｓｉ：Ｈ積層部、１０…ゲート線、１０’…ドレーン
線上のＡｌ膜（ゲート線と同層）、１１…画素電極、１
２…表面酸化膜。1 ... Glass substrate, 2 ... ITO film, 3 ... Semiconductor layer of a-Si: H film, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Protective film, 7 ... Drain line, 8 ... Source electrode, 9 ... SiN /
a-Si: H laminated portion, 9 '... SiN / a on the drain line
-Si: H laminated portion, 10 ... Gate line, 10 '... Al film on drain line (same layer as gate line), 11 ... Pixel electrode, 1
2 ... Surface oxide film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 太田 益幸 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 金子 寿輝 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 峯村 哲郎 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masuyuki Ota 7-1, 1-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Toshiki Kaneko 7-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 in Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Tetsuro Minemura 7-1-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.
Claims (9)
ト配線及びドレーン配線が複数配設され、前記ゲート配
線とドレーン配線の交差部は互いに電気的に絶縁されて
おり、前記各交差部の近傍には薄膜トランジスタがそれ
ぞれ配置され、各薄膜トランジスタのソース電極はその
近傍に設けられた各透明画素電極に、ドレーン電極は前
記ドレーン配線にそれぞれ接続され、また、前記各薄膜
トランジスタのゲート電極は前記ゲート配線にそれぞれ
接続されており、これらは前記絶縁基板も含めて配向膜
または保護性絶縁膜及び配向膜で被覆されており、該絶
縁基板と対向して配置されたもう一方の透明絶縁基板上
には前記透明画素電極に対向して設けられた透明電極と
配向膜とを有し、前記２枚の絶縁基板間には液晶が挾持
されており、前記ゲート配線，ドレーン配線及び対向す
る透明絶縁基板上の透明電極は外部の液晶駆動回路に接
続されているアクティブマトリクス型液晶表示装置にお
いて、 前記ドレーン配線及び前記薄膜トランジスタのドレーン
電極及びソース電極は前記透明画素電極と同一材料で形
成されており、前記透明画素電極の膜厚をドレーン配線
部分より薄く構成したことを特徴とするアクティブマト
リクス型液晶表示装置。1. A plurality of gate wirings and drain wirings that are orthogonal to each other are arranged on one insulating substrate, and intersections of the gate wirings and drain wirings are electrically insulated from each other, and the vicinity of each of the intersections. Thin film transistors are respectively arranged, the source electrode of each thin film transistor is connected to each transparent pixel electrode provided in the vicinity thereof, the drain electrode is connected to the drain wiring, and the gate electrode of each thin film transistor is connected to the gate wiring. They are connected to each other, and these are covered with an alignment film or a protective insulating film and an alignment film including the insulating substrate, and on the other transparent insulating substrate arranged facing the insulating substrate, It has a transparent electrode provided facing the transparent pixel electrode and an alignment film, and a liquid crystal is sandwiched between the two insulating substrates. In the active matrix type liquid crystal display device, the gate wiring, the drain wiring, and the transparent electrodes on the opposing transparent insulating substrate are connected to an external liquid crystal driving circuit, wherein the drain wiring and the drain electrode and the source electrode of the thin film transistor are the transparent electrodes. An active matrix type liquid crystal display device, which is formed of the same material as a pixel electrode, wherein the transparent pixel electrode is thinner than a drain wiring portion.
タのドレーン電極及びソース電極、並びに前記透明画素
電極は順テーパ端面を有し、かつ、そのテーパ角は３０
°以下である請求項１に記載のアクティブマトリクス型
液晶表示装置。2. The drain wiring, the drain electrode and the source electrode of the thin film transistor, and the transparent pixel electrode have forward tapered end faces, and the taper angle thereof is 30.
The active matrix liquid crystal display device according to claim 1, wherein the liquid crystal display device has an angle of not more than °.
びソース電極上に跨って形成された半導体層，ゲート絶
縁層，ゲート電極から構成され、前記半導体層とゲート
絶縁層の積層部のパターンと前記ゲート電極パターンと
は同一中心線上あり、かつ、中心線の左右のパターンが
対称となるように形成されている請求項１または２に記
載のアクティブマトリクス型液晶表示装置。3. The thin film transistor comprises a semiconductor layer, a gate insulating layer, and a gate electrode formed over a drain electrode and a source electrode, and a pattern of a laminated portion of the semiconductor layer and the gate insulating layer and the gate electrode pattern. 3. The active matrix type liquid crystal display device according to claim 1 or 2, wherein is formed on the same center line, and the patterns on the left and right of the center line are symmetrical.
パターン幅はゲート電極層が半導体層のパターン幅より
大きく、その両者の差は０.２〜５μｍである請求項
１，２または３に記載のアクティブマトリクス型液晶表
示装置。4. The pattern width of the laminated portion of the semiconductor layer and the gate insulating layer is larger than the pattern width of the semiconductor layer of the gate electrode layer, and the difference between them is 0.2 to 5 μm. The active matrix liquid crystal display device according to item 1.
は、前記透明画素電極上に該透明画素電極の寸法よりも
大きくない寸法の貫通孔を有し、該貫通孔の平面パター
ンは、前記ドレーン配線，前記薄膜トランジスタを構成
するドレーン電極及びソース電極と前記透明画素電極と
の膜厚段差部の平面パターンとほぼ一致するよう形成さ
れている請求項１〜４のいずれかに記載のアクティブマ
トリクス型液晶表示装置。5. The protective insulating film covering the insulating substrate has a through hole on the transparent pixel electrode, the through hole having a size not larger than the size of the transparent pixel electrode, and the plane pattern of the through hole is 5. The active matrix type according to claim 1, wherein the drain wiring, the drain electrode and the source electrode forming the thin film transistor, and the transparent pixel electrode are formed so as to substantially coincide with a plane pattern of a film thickness step portion. Liquid crystal display device.
タのドレーン電極及びソース電極と、前記透明画素電極
との膜厚段差部の平面パターンは、前記薄膜トランジス
タの半導体層とゲート絶縁層との積層部の平面パターン
とほぼ一致するよう形成されている請求項１〜４のいず
れかに記載のアクティブマトリクス型液晶表示装置。6. The plane pattern of a film thickness step portion between the drain wiring, the drain electrode and source electrode of the thin film transistor, and the transparent pixel electrode is a plane pattern of a laminated portion of a semiconductor layer and a gate insulating layer of the thin film transistor. 5. The active matrix type liquid crystal display device according to claim 1, which is formed so as to substantially coincide with the above.
する透明導電膜のシート抵抗が５Ω／□以下である請求
項１〜６のいずれかに記載のアクティブマトリクス型液
晶表示装置。7. The active matrix liquid crystal display device according to claim 1, wherein the transparent conductive film forming the gate wiring and the drain wiring has a sheet resistance of 5 Ω / □ or less.
ｎｍの照射光に対して８５％以上である請求項１〜７の
いずれかに記載のアクティブマトリクス型液晶表示装
置。8. The transmittance of the transparent pixel electrode has a wavelength of 550.
The active matrix type liquid crystal display device according to any one of claims 1 to 7, which has an irradiating light of 85% or more.
とする金属材料からなり、該電極の表面と端面は該電極
材料の陽極酸化膜で被覆されている請求項１〜８のいず
れかに記載のアクティブマトリクス型液晶表示装置。9. The method according to claim 1, wherein the gate electrode is made of a metal material having Al or Ta as a main component, and the surface and the end surface of the electrode are covered with an anodic oxide film of the electrode material. Active matrix liquid crystal display device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22187393A JPH0772510A (en) | 1993-09-07 | 1993-09-07 | Active matrix liquid crystal display |
| US08/301,202 US5552909A (en) | 1993-09-07 | 1994-09-06 | Active matrix liquid-crystal display device having ITO signal lines and either a symmetric TFT structure or electrode and signal line edges with taper angles ≦30° |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22187393A JPH0772510A (en) | 1993-09-07 | 1993-09-07 | Active matrix liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0772510A true JPH0772510A (en) | 1995-03-17 |
Family
ID=16773524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22187393A Pending JPH0772510A (en) | 1993-09-07 | 1993-09-07 | Active matrix liquid crystal display |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5552909A (en) |
| JP (1) | JPH0772510A (en) |
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| US6356328B1 (en) | 1997-12-03 | 2002-03-12 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display |
| JP2006093652A (en) * | 2004-09-20 | 2006-04-06 | Samsung Sdi Co Ltd | Organic thin film transistor and plate indicating device equipped therewith |
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Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2533072B1 (en) * | 1982-09-14 | 1986-07-18 | Coissard Pierre | METHOD FOR MANUFACTURING ELECTRONIC CIRCUITS BASED ON THIN FILM TRANSISTORS AND CAPACITORS |
| JPS6280626A (en) * | 1985-10-04 | 1987-04-14 | Hosiden Electronics Co Ltd | Liquid crystal display element |
| GB2212659A (en) * | 1987-11-20 | 1989-07-26 | Philips Electronic Associated | Multi-level circuit cross-overs |
| US5245452A (en) * | 1988-06-24 | 1993-09-14 | Matsushita Electronics Corporation | Active matric drive liquid crystal display device using polycrystalline silicon pixel electrodes |
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| JPH07109829B2 (en) * | 1989-11-20 | 1995-11-22 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| JP2921028B2 (en) * | 1990-05-18 | 1999-07-19 | 富士通株式会社 | Connector mounting structure between chassis |
| EP0499979A3 (en) * | 1991-02-16 | 1993-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| JP3526058B2 (en) * | 1992-08-19 | 2004-05-10 | セイコーインスツルメンツ株式会社 | Semiconductor device for light valve |
| US5293261A (en) * | 1992-12-31 | 1994-03-08 | The United States Of America As Represented By The Secretary Of The Navy | Device for low electric-field induced switching of Langmuir-Blodgett ferroelecric liquid crystal polymer films |
-
1993
- 1993-09-07 JP JP22187393A patent/JPH0772510A/en active Pending
-
1994
- 1994-09-06 US US08/301,202 patent/US5552909A/en not_active Expired - Fee Related
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| JPH0990427A (en) * | 1995-09-26 | 1997-04-04 | Nec Corp | Thin-film transistor and production of thin-film transistor |
| US6356328B1 (en) | 1997-12-03 | 2002-03-12 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display |
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| WO2014020892A1 (en) * | 2012-08-01 | 2014-02-06 | パナソニック液晶ディスプレイ株式会社 | Thin film transistor and method for manufacturing same |
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Also Published As
| Publication number | Publication date |
|---|---|
| US5552909A (en) | 1996-09-03 |
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