JPH0766178A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent overetching of the underlying layer for an interlayer insulation film by making the opening of an anti-etching mask at a thick part of interlayer insulation film wider than that at a thin part thereof. CONSTITUTION:An interlayer insulation film 26 is etched based on a resist mask 27. In this regard, the opening 27b-27d of resist mask 27 are made wider on the lower wiring layers 23b-23 where the interlayer insulation film 26 is formed thick than on the lead-out electrode 23a. Consequently, the etching rate at the openings 27b-27d is increased as compared with that at the narrower opening 27a through microloading effect. This method etches the thick interlayer insulation film 26 at high rate and etches the thin interlayer insulation film at low rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to an SOG film formed by a coating method on a substrate on which projections such as wiring layers and extraction electrodes are roughly and densely distributed. The present invention relates to a method for manufacturing a semiconductor device, which comprises forming an interlayer insulating film containing a metal oxide and forming a via hole by patterning the interlayer insulating film on the convex portion.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, in general, in order to efficiently connect elements by internal leads and electrically connect to external leads, projections such as wiring layers and lead electrodes are rough on a semiconductor substrate. -There may be dense distribution. A wiring layer on the substrate having the silicon oxide film 2 formed on the silicon substrate 1 as shown in FIG. 5A, the lead-out electrodes 3a to 3d, and the like are first covered and first planarized. SOG film 4 is formed by a coating method for
When the silicon oxide film 5 is formed on the film 4 by the CVD method, as shown in FIG. 5B, the SOG film 4 is formed thicker in a portion where the wiring layers 3a to 3d are denser than in a rough portion. . For this reason, as shown in FIG.
When forming via holes in the interlayer insulating films 4 and 5 above 3d to 3d, all the via holes 7a to 7a are formed as shown in FIG.
It is difficult to open d in the same etching time.
Therefore, in order to open all the via holes 7a to 7d, the etching time is determined according to the thick portion.

[0003]

However, the interlayer insulating film 4
Since the wiring layers 3a to 3d in the thin portions 5 and 5 are excessively exposed to the etching gas, the wiring layers 3a to 3d are etched and the film thickness is reduced. In particular, when the widths of the wiring layers 3a to 3d and the like become narrower or the film thickness becomes thinner due to miniaturization, the film reduction causes an increase in resistance,
It becomes a problem. Moreover, there is a risk that the underlying layers 3a to 3d such as the wiring layers may be damaged by being exposed to the plasma.

The present invention was created in view of the problems of the conventional example, and even if the film thickness of the interlayer insulating film is not uniform, the interlayer insulating film is etched without excess or deficiency, and An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing excessive etching of a base.

[0005]

The above problems include a SOG film formed by coating a plurality of conductor layers on a substrate and formed at least by a coating method, and a film thickness on the conductor layer is A method of manufacturing a semiconductor device, wherein different interlayer insulating films are simultaneously etched on the basis of an etching resistant mask to form an opening on a conductor layer, wherein the etching resistant mask has a thick portion of the interlayer insulating film. The opening width of the opening is larger than the opening width of the opening of the etching resistant mask in the thin portion of the interlayer insulating film.

[0006]

[Operation] FIGS. 3 (a), 3 (b) and 4 are explanatory views of the principle of the present invention, and FIGS. 3 (a) and 3 (b) are sectional views for explaining the microloading effect. FIG. 4 is a diagram showing the dependence of the etching depth of the object to be processed on the opening width of the opening to be formed in the object to be processed. A silicon oxide film is used as the object to be processed and CHF is used as an etching gas.
A mixed gas of ₃ + CF ₄ or a mixed gas of Ar + CHF ₃ + CF ₄ is used.

As shown in FIG. 4, when the opening width of the opening to be formed by etching the object to be processed becomes half micron or less, the microloading effect becomes remarkable. This is because, as shown in FIGS. 3A and 3B, when the object 2 to be processed is etched based on the resist mask 3, for example, the opening width of the opening 2b to be formed in the object 2 to be processed. The smaller the value, the harder the etchant reaches the bottom, so that the etching becomes slower and it takes longer to form the opening 2b than the opening 2a having a large opening width.

In the method of manufacturing a semiconductor device according to the present invention, the SOG film formed by the coating method on the substrate and covering the wiring layer is the interlayer insulating film having a film thickness of the interlayer insulating film on the wiring layer. It is easy to mix thick and thin areas.
In particular, when the rough and dense convex portions are covered, the thickness and thinness of the interlayer insulating film on the convex portions become remarkable. An opening of the etching resistant mask having an opening width larger than that of the thin portion of the interlayer insulating film is formed in the thick portion of the interlayer insulating film.

Therefore, due to the above microloading effect, the etching rate of the thick interlayer insulating film is higher than that of the thin interlayer insulating film. Therefore, by appropriately adjusting the opening width in relation to the film thickness of the interlayer insulating film, it is possible to complete the etching of all the interlayer insulating films in the same etching time and form the openings. . As a result, excessive etching of the base of the interlayer insulating film can be prevented.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a) to 1 (c) and FIG. 2, according to an embodiment of the present invention, an interlayer insulating film including an SOG film is formed on a semiconductor substrate in which projections such as a wiring layer are roughly and densely distributed,
FIG. 6 is a cross-sectional view illustrating a method of forming an opening in an interlayer insulating film on the wiring layer.

First, as shown in FIG. 1A, a silicon oxide film 22 having a thickness of 400 nm is formed on a silicon substrate 21 by thermal oxidation. Subsequently, an aluminum film having a film thickness of 400 nm is formed on the silicon oxide film 22, and then patterned to form the extraction electrode 23a and the lower wiring layers 23b to 23d. In this case, the extraction electrodes 23a are roughly distributed, and the lower wiring layers 23b-23d are densely distributed.

Next, as shown in FIG. 1 (b), after applying SOG, heat treatment is performed to cure the SOG and to remove SO.
The G film 24 is formed. At this time, the SOG film 24 is formed thick on the lower wiring layers 23b to 23d which are densely distributed, and thin on the extraction electrode 23a which is roughly distributed. Then, the silicon oxide film 2 is formed on the SOG film 24 by the CVD method.
5 is formed. The SOG film 24 and the silicon oxide film 25 form an interlayer insulating film 26.

Next, as shown in FIG. 1C, a resist mask (etching resistant mask) 27 is formed. At this time, the openings 27a formed in the resist mask 27
27d has a larger opening width on the lower wiring layers 23b to 23d in which the interlayer insulating film 26 is formed thicker than on the extraction electrode 23a. Next, as shown in FIG. 2, a mixed gas of CHF ₃ + CF ₄ or Ar + CHF is used as an etching gas.
_The interlayer insulating film 26 is etched based on the resist mask 27 using a mixed gas of ₃ + CF ₄ . At this time, the openings 27a to 27d of the resist mask 27 are formed in the interlayer insulating film 2
On the lower wiring layers 23b to 23d formed to have a large film thickness of 6, the opening width is larger than that on the extraction electrode 23a. Therefore, due to the microloading effect, the openings 27b to 27d having a large opening width are formed. The etching rate is higher than the etching rate in the opening 27a having a small opening width. Therefore, the etching of the thick interlayer insulating film 26 is fast, and the etching of the thin interlayer insulating film 26 is slow. Therefore, all the interlayer insulating films 26 are completely etched in the same etching time, and the via holes 28a to 28d are formed. As a result, the lower wiring layer 23 under the interlayer insulating film 26 is
Excessive etching of b to 23d can be prevented.

As described above, according to the method of forming a via hole of the embodiment of the present invention, a portion of the substrate where the thickness of the interlayer insulating film 26 is thicker than a portion where the thickness of the interlayer insulating film 26 is thinner than that of the substrate. Openings 27b to 27d of the resist mask 27 having a large opening width are formed. Therefore, due to the above-described microloading effect, the etching rate of the thick interlayer insulating film 26 is higher than that of the thin interlayer insulating film 26. Therefore, by appropriately adjusting the opening width according to the film thickness of the interlayer insulating film, etching of all the interlayer insulating films 26 is completed in the same etching time, and the openings 28a to 28d are formed. As a result, the interlayer insulating film 2
It is possible to prevent excessive etching of the underlying lower wiring layers 23a to 23d of FIG.

Strictly speaking, the opening widths of the opening portions 27a to 27d of the resist mask 27 are individually determined according to the film thickness of the interlayer insulating film 26 to be formed on the lower wiring layers 23a to 23d. The lower wiring layers 23a-23 are practically used.
According to the degree of coarseness / denseness of the convex portion such as d, the opening portions 27a to 27d of the resist mask 27 may be divided into two or three types according to the degree of coarseness / denseness, and the opening width of two to three types may be set accordingly. Good.

[0016]

As described above, in the method of manufacturing a semiconductor device of the present invention, the opening on the substrate where the thickness of the interlayer insulating film is large is larger than that where the thickness of the interlayer insulating film is thin. An opening having a width is formed. Therefore,
Due to the microloading effect described above, the etching rate of the thick interlayer insulating film is higher than that of the thin interlayer insulating film. Therefore, by appropriately adjusting the opening width according to the film thickness of the interlayer insulating film, etching of all the interlayer insulating films is completed in the same etching time, and the openings are formed. As a result, excessive etching of the base of the interlayer insulating film can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) for explaining a via hole forming method according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) for explaining a via hole forming method according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram (1) of the microloading effect according to the present invention.

FIG. 4 is an explanatory view (No. 2) of the microloading effect according to the present invention.

FIG. 5 is a sectional view (No. 1) for explaining a method of forming a via hole according to a conventional example.

FIG. 6 is a sectional view (No. 2) for explaining a method of forming a via hole according to a conventional example.

[Explanation of symbols]

11,21 Silicon substrate, 12,22,25 Silicon oxide film, 12a, 12b, 13a, 13b, 27a to 27d Opening, 13,27 Resist mask (etching resistant mask), 23a Lead electrode, 23b to 23d Lower wiring Layer, 24 SOG film, 26 interlayer insulating film, 28a to 28d via hole.

Claims (1)

[Claims] 1. An interlayer insulating film, which is formed by coating a plurality of conductor layers on a substrate and includes at least an SOG film formed by a coating method, and which has different film thicknesses on the conductor layers, is resistant to etching. A method of manufacturing a semiconductor device in which an opening is formed on the conductor layer by simultaneously etching based on a mask, wherein the opening width of the opening of the etching-resistant mask in the thick portion of the interlayer insulating film is A method for manufacturing a semiconductor device, wherein the opening width of the opening of the etching resistant mask in the thin portion of the interlayer insulating film is larger.