JPH0758918B2 - Differential processing PCM encoding / decoding circuit for multiplex processing - Google Patents

Description

DETAILED DESCRIPTION [Outline] In a differential pulse code modulation system such as adaptive differential pulse code modulation (ADPCM) that performs multiplex processing on multiple channels in a time division manner, a circuit portion common to an encoder and a decoder. , And inputting an encoding / decoding process designation signal synchronized with the input data makes it possible to arbitrarily designate the process as an encoder or decoder for any channel in the multiplex process. A processing differential PCM encoding / decoding circuit is disclosed.

[Industrial application field]

The present invention relates to an adaptive differential pulse code modulation system, which is one field of high-efficiency speech coding systems, for example, and in particular, a differential PCM for multiple processing for performing multiplex coding and decoding processing on input data in a time division multiplex manner. The present invention relates to an encoding / decoding circuit.

[Conventional technology and problems]

For audio signal processing, the ADPCM method, which is capable of highly efficient data compression with a relatively simple configuration, is often used.
In addition, an encoding circuit or a decoding circuit for multiplex processing corresponding to multiple channels is used.

However, in the conventional multiple processing circuit, the constituent part of the processing circuit for encoding and the constituent part of the processing circuit for decoding are provided as completely different processing circuits. Therefore, in a device that requires both encoding processing and decoding processing, there is a problem that the circuit scale or the processing scale increases.

Further, a synchronous processing method in which the encoding processing and the decoding processing are alternately performed has been considered, but it is adaptive such that the encoding processing or the decoding processing is arbitrarily specified for the data input of each channel. There is a problem that it cannot deal with it.

[Means for solving problems]

The present invention is configured as shown in FIG. 1 in order to solve the above-mentioned problems and to make it possible to arbitrarily select either encoding processing or decoding processing for each channel.

FIG. 1 shows a schematic configuration of the present invention, and FIG. 2 shows a diagram for explaining a data input / output arrangement and an encoding / decoding processing designation signal.

In FIG. 1, reference numerals 1-1 to 1-4 are delay circuits for holding an encoding / decoding processing designation signal in synchronization with input data, and 2 is processing for encoding processing and decoding processing separately. A non-common circuit section for performing the above, 3 is a first selector for selecting either data relating to encoding or data relating to decoding, 4
Is an encoding / decoding common circuit unit composed of parts shared in the encoding process and the decoding process, 5 is a random access memory (RAM), 6 is a non-common circuit unit for encoding / decoding, Reference numeral 7 represents a second selector for selecting either data regarding encoding or data regarding decoding. The detailed configuration of the present invention will be described later with reference to FIG.

[Action]

For example, when the bit width of the code to be encoded is 8 bits, the data input sequence of each channel is as shown in FIG. The encoding / decoding process designation signal is given in synchronization with the timing of the input data, and represents the decoding process designation when it is at the H level and represents the encoding process designation when it is at the L level. Therefore, in the example shown in FIG. 2A, the channel ch1 and the channel ch2 are the targets of the decoding process, and the channel ch3 is the target of the encoding process.

When the input shown in FIG. 2 (a) is applied to the circuit shown in FIG. 1, the data output is arranged as shown in FIG. 2 (b). For channel ch1 and channel ch2,
The decoded data is output, and the 4-bit encoded data is output to channel ch3.

The processing designation signal is supplied to the delay circuit 1-1 shown in FIG. 1 and is sequentially sent to the delay circuit of the next stage for each processing cycle. The non-common circuit unit 2 performs individual processing of encoding and decoding on the input shown in FIG. This output is given to each selector 3, and the selector 3
Selects either data relating to encoding or data relating to decoding for each channel by the output of the delay circuit 1-2.

The selected data is commonly processed by the encoding / decoding common circuit unit 4, and the RAM 5 holds the delay coefficient generated in each channel process. Encoding / decoding common circuit unit 4
Further, the non-common circuit section 6 further performs post-processing such as output timing synchronization processing, and the selector 7 selects encoded or decoded output data.

With the configuration as described above, it is possible to specify the encoding process or the decoding process by the process specifying signal for each channel and execute both processes in a time-divisional manner with one circuit.

〔Example〕

FIG. 3 shows a block diagram of a more detailed embodiment.

In the figure, reference numerals 1-1 to 1-4 and 3,4,7 correspond to those shown in FIG. 1, and 10-1 to 10-4 are delay circuits, 11
Is a μ / L converter that performs non-linear / linear conversion for converting an 8-bit μ-law PCM signal into a 14-bit linear PCM signal, 12 is an adder, 13 is a quantizer, and 14 is dequantizer , 15 is a predictor, 16 is an adder, 17 is RAM, 18 is a step size updating unit, 19
Is a RAM, and 20 is an L / μ converter that performs linear / non-linear conversion for converting a 16-bit linear PCM signal into an 8-bit μ-law PCM signal.

The circuit shown in Fig. 3 is an 8-bit μ-law PC for encoding.
M signal is input and 4-bit ADPCM signal is output. On the other hand, in the case of decoding, 4-bit ADPCM signal is input and
8-bit μ-law PCM signal is output.

As shown by period P1 to period P4 in FIG. 3, the entire process is divided into four periods due to the time division multiplexing process. A data processing state corresponding to each channel is assigned to each period. The dequantizer 14, the predictor 15, the adder 16, the step size updating unit 18, and the RAMs 17 and 19 in the encoding / decoding common circuit unit 4 are commonly used in the encoding process and the decoding process.

The input data is supplied to the μ / L conversion unit 11 and the delay circuit 10-1 of the period P1. In μ / L converter 11, 8-bit PC
The M code is converted into a 14-bit linear code SL, and the adder 12 subtracts the predicted value SE from the linear code SL. This subtraction information becomes the error signal D, and the quantizer 13
Is quantized into a 4-bit quantized code I. Then, it is input to the selector 3. On the other hand, the halved input data is delayed by 2 periods by the delay circuit 10-1 and the delay circuit 10-2, and is input to the selector 3.

On the other hand, the encoding / decoding process designating signal also receives a delay of 2 periods and is input to the selector 3 to control the selector 3. When the signal is “H”, it means that the decoding process is designated. The selected input data is selected, and when it is "L", the quantization processing I is selected because the encoding processing is designated.

The signal that has passed through the selector 3 has a step size updating unit 18
The step size Y used in the next process corresponding to the channel is obtained. The result is R
It is stored in AM19.

Further, the inverse quantizer 14 outputs the reproduction error signal DQ,
In addition to being sent to the predictor 15, it is also sent to the adder 16
At 16, the reproduction error signal DQ and the predicted value SE are added. The addition result is sent to the predictor 15 and the L / μ converter 20 as the reproduction signal SR.

The predictor 15 outputs a prediction value SE for the input of the reproduction error signal DQ and the reproduction signal SR, and stores the result in the RAM 17.
The RAM 17 is a memory that stores the predicted value SE corresponding to each channel to be multiplexed. Since the adder 12 is in the period P1 and the adder 16 is in the period P3, if the predicted value SE output from the RAM 17 to the adder 12 is for the i-th channel, the predicted value output to the adder 16 SE becomes that of the (i-2) th channel. In the L / μ conversion unit 20, the 16-bit reproduction signal SR is limited to 14 bits which is the full scale of μ-law companding law, and then converted into an 8-bit PCM code.

In the selector 7, the quantization code output from the selector 3
I, that is, the signal delayed by 2 periods of ADPCM code and L / μ
The PCM code signal SP that is the output of the conversion unit 20 is selected by the signal that has been delayed by 4 periods of the encoding / decoding processing designation signal. That is, when the processing designation signal is "L",
Since it is an encoding process, the ADPCM code (I) is selected,
When it is "H", it means decoding process, so PCM code (S
P) is selectively output.

The signals necessary for processing in each of the periods P1 to P4 shown in FIG. 3 are given as the processing result in the preceding period or the output from the RAMs 17, 19. The processing result in each period P1 to P4 is input to the next period or RAM17,19. Each period P1 to P4 has an equal time interval (for example, encoding /
The input signal for decoding is divided by the time it takes for one channel to be input).

The operation of the circuit shown in FIG. 3 will be described below separately for the case of encoding and the case of decoding.

[In the case of encoding] Period P1: The 8-bit PCM code S to be encoded is input to the μ / L conversion unit 11 and converted into a 14-bit linear code SL, and then added with the predicted value SE by the adder 12. The difference is taken,
The error signal D is output.

Period P2: The error signal D is quantized by the quantizer 13 into a 4-bit quantized code I, and the delay circuit 10-3 and the encoding / decoding common circuit unit 4 are passed through the selector 3.
Sent to.

Period P3: The quantized code I, that is, the 4-bit ADPCM code, passes through the selector 3 and is held in the delay circuit 10-3. Further, this signal is input to the step size updating unit 18, where the step size Y used in the next process corresponding to the channel is obtained and stored in the RAM 19.
At the same time, the dequantizer 14 dequantizes and outputs the reproduction error signal DQ, which is sent to the predictor 15 and the adder 16
The predicted value SE is added by the adder 16 and is sent to the predictor 15 as a reproduction signal SR.

Period P4: The signal held by the delay circuit 10-3 is transferred to the delay circuit 10-4 and output from the selector 7 as a 4-bit ADPCM code. Further, the predictor 15 outputs the predicted value SE to be used next time in response to the input of the reproduction error signal DQ and the reproduction signal SR, and stores the result in the RAM 17. The results stored in the RAM 17 are read when the next signal corresponding to this channel reaches the periods P1 and P3, respectively.

[For Decoding] Period P1: A 4-bit ADPCM code (quantization code I) to be decoded is input and held in the delay circuit 10-1.

Period P2: The signal held by the delay circuit 10-1 is transferred to the delay circuit 10-2. This signal is sent to the encoding / decoding common circuit unit 4 via the selector 3.

Period P3: In the encoding / decoding common circuit unit 4, the dequantizer 14 and the adder 16 respectively reproduce the reproduction error signal DQ from the 4-bit ADPCM code as in the case of encoding.
The reproduction signal SR is required.

Period P4: For the input of the reproduction error signal DQ and the reproduction signal SR, the predictor 15 obtains the predicted value SE to be used next time, and stores the result in the RAM 17. The result stored in RAM17 is
When the next signal corresponding to this channel reaches the period P3, it is read and output to the adder 16. The reproduction signal SR is 16 bits, and after being limited to 14 bits which is the full case of the μ-law companding rule in the L / μ conversion unit 20, it is converted into an 8-bit PCM code signal SP and the selector 7 Is output via.

Although the present invention has been described above by taking the example of the ADPCM encoder / decoder, the present invention can be similarly applied to a simple differential PCM system.

〔The invention's effect〕

As described above, according to the present invention, the encoding process and the decoding process can be realized with one type of processing circuit, and the scale of the entire processing configuration can be reduced. In addition, since it is possible to arbitrarily specify the encoding or decoding process for the input data for each channel and to design various input interfaces according to the purpose, the versatility is significantly improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration of the present invention, FIG. 2 is a diagram for explaining a data input / output arrangement and an encoding / decoding processing designation signal, and FIG. 3 is a block diagram of an embodiment of the present invention. In the figure, 1-1 to 1-4 are delay circuits, 2 is a non-common circuit section, 3
Is a first selector, 4 is an encoding / decoding common circuit section, and 5 is RA
M and 6 are non-common circuit parts, and 7 is a second selector.

Claims (1)

[Claims] 1. A data including a time-division-multiplexed PCM signal to be encoded or a differential PCM to be decoded or an adaptive differential PCM signal is input, and a PCM signal and a differential P corresponding to each channel are input.
Multiplexing that performs coding / decoding conversion with a CM or adaptive differential PCM signal, and outputs data that includes the time-division-multiplexed decoded differential PCM or adaptive differential PCM signal or encoded PCM signal. A differential PCM encoding / decoding circuit for processing, which is a non-linear / linear conversion unit (11) for converting input data of a PCM signal to be encoded into a linear code according to a predetermined companding rule.
And an adder (12) for generating an error signal using a predicted value from the linear code converted by the non-linear / linear conversion section (11), and a quantizer for quantizing the output of the adder (12) (13)
And an input signal of an encoding / decoding processing designation signal for designating whether to encode or decode input data for each channel, by using the nonlinear / linear conversion unit (11) and the adder. (12) and a first delay unit (1-1, 1-2) that delays the processing time of the quantizer (13), and a signal of input data to the nonlinear / linear conversion unit (11) and Second delay units (10-1, 10-2) for delaying the processing time of the adder (12) and the quantizer (13), and the first delay units (1-1, 1-2) ), The data delayed by the second delay unit (10-1, 10-2) and quantized by the quantizer (13) based on the encoding / decoding process designation signal delayed by First to select one of the data
Selector (3), at least an inverse quantizer (14) that creates a reproduction error signal from a quantized code, a predictor (15) that creates a reproduction error signal and a prediction value from the reproduction signal, a reproduction error signal and a prediction value And an encoding / decoding common circuit section (4) having a means for producing a reproduction signal from the above and a means for outputting the predicted value to the adder (12), and the encoding / decoding common circuit section (4). A linear / non-linear conversion unit (20) for inputting the generated reproduction signal and performing compression conversion according to the predetermined companding rule, and encoding delayed by the first delay unit (1-1, 1-2). / A third delay unit (1-3,1-4) that delays the decoding process designation signal by the processing time of the encoding / decoding common circuit unit (4) and the linear / non-linear conversion unit (20). ) And the output of the first selector (3) to the encoding / decoding common circuit section ( ) And the fourth delay section for delaying the processing time of a linear / non-linear conversion unit (20) (10-3, 10-4)
And the fourth delay unit (10-3, 10-4) based on the encoding / decoding process designation signal delayed by the third delay unit (1-3, 1-4). An output and a second selector (7) for selecting one of the outputs of the linear / non-linear conversion section (20), and the output of the second selector (7) is encoded or decoded in time division A differential PCM encoding / decoding circuit for multiplex processing, wherein output data is obtained by multiplexing.