JPH0758608A - Digital signal transfer circuit - Google Patents

Abstract

PURPOSE:To quickly detect the signal change by detecting the rise of an input digital signal based on a first threshold lower than the median of the signal amplitude and detecting the fall based on a second threshold higher than the median. CONSTITUTION:The data signal input from a data bus 10 has the waveform shaped and is latched in an input circuit 12 synchronously with a clock signal CK. At this time, the waveform shaped output is selected and latched based on a second threshold VthH higher than the median of the signal amplitude with respect to the fall of a data input signal Din, and the waveform shaped output is selected and latched based on a first threshold VthL lower than the median with respect to the rise of the input Din. Thus, the change of the input Din is quickly detected, and the delay time is shortened from the leading edge of the signal CK to that of latch data at the time of fall and rise of the input Din to increase the speed of the signal CK. Consequently, the data transfer speed is increased even when a load capacitance of a bus 10 and the wiring resistance are large and rise and fall times are long.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transfer circuit used in a digital circuit system, and more particularly to a digital signal for transferring digital data or a clock signal via a signal wire such as a data bus or a clock wire. Regarding the transfer circuit.

[0002]

2. Description of the Related Art For example, a one-chip microcomputer,
2. Description of the Related Art A digital signal transfer circuit is used for transferring data or a clock signal inside a LSI such as a microprocessor or a digital signal processor or between LSIs via a signal bus such as a data bus or a clock wiring.

FIG. 9 shows an example of a conventional data bus transfer circuit. 10 is a data bus, and its load capacity is C,
The wiring resistance is represented by R. A large number of input circuits and a large number of output circuits are connected to the data bus 10. Here, for simplification of description, an output circuit 91 and an input circuit 92 for one bit corresponding to one bit of the parallel data transferred by the data bus 10 are taken out and shown.

The output circuit 91 has a latch circuit 93 for latching internal data in synchronization with the clock signal CK, and a tri-state type output buffer circuit 94 for outputting the latched data of this latch circuit to the data bus 10. .

The input circuit 92 includes an input buffer circuit 95 that receives data input from the data bus 10 and shapes the waveform, and a latch circuit 96 that latches output data of the input buffer circuit in synchronization with a clock signal CK. Have.

FIG. 10 shows a data bus transfer circuit of FIG. 9 in which one output circuit 91 to a plurality of input circuits 9 are provided.
2 shows an example of operation waveforms when data is transferred. As can be seen from this operation waveform, the data Dout output from the output circuit 91 to the data bus 10 is the data bus 1
The signal waveform is blunted due to the load capacitance C of 0 and the wiring resistance R, and the rise time tr and the fall time tf of the signal Din near the input node of the input circuit 92 are delayed, that is,
There is a delay in data transfer from the output circuit 91 to the input circuit 92.

This signal waveform is shaped by the input buffer circuit 95 and then latched in synchronization with the clock signal CK. In this case, the threshold Vth of the input buffer circuit 95
Is set to a constant value in the center of the input waveform amplitude,
From the leading edge of the clock signal CK to the input buffer circuit 95
If the delay times td and tup to the leading edge of the output data are large, the increase in the speed of the clock signal CK is limited, which impedes the speeding up of data transfer.

Similarly to the above, also in a digital signal transfer circuit for transferring a clock signal via a clock signal line, when the load capacitance or wiring resistance of the clock signal line is large, the clock signal is transferred via the clock signal line. The rise time and fall time of a signal during transfer are long, which is a major factor limiting the system speed.

Moreover, with the miniaturization of LSIs, the system scale tends to increase, and the load capacitance and wiring resistance of signal wiring tends to increase, and the deterioration of system speed due to these tends to become apparent. However, the demand for high-speed signal transfer is ever increasing, and the problems described above are becoming more serious.

[0010]

As described above, in the conventional digital signal transfer circuit, when the load capacitance and the wiring resistance of the signal wiring are large, the digital data and the clock signal are transferred through the signal wiring. There is a problem that the rise time and fall time of the signal become long, which becomes a major factor limiting the system speed.

The present invention has been made to solve the above-mentioned problems, and the load capacitance and wiring resistance of the signal wiring are so large that the rise time and fall time of the signal at the time of transferring the digital data or the clock signal are long. Even so, it is an object of the present invention to provide a digital signal transfer circuit that can achieve high-speed data transfer and can alleviate the system speed limitation.

[0012]

A digital signal transfer circuit of the present invention includes a signal wiring used in a digital circuit system, an output circuit for outputting a digital signal to the signal wiring, and a signal wiring connected to the signal wiring. With respect to the digital signal input from the signal wiring, the rising edge is based on the first threshold value lower than the median value of the digital signal amplitude, and the falling edge is based on the second threshold value higher than the median value of the digital signal amplitude. And an input circuit for shaping the waveform.

[0013]

[Operation] For digital signals input from the signal wiring,
Since the rising edge is detected with the first threshold value lower than the median value of the digital signal amplitude as the reference and the falling edge is detected with the second threshold value higher than the median value of the digital signal amplitude as the reference, It becomes possible to detect a signal change faster than when detecting a fixed value as a reference. This makes it possible to achieve high-speed digital signal transfer and alleviate the system speed limitation.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a data transfer circuit according to a first embodiment of the digital signal transfer circuit of the present invention.

In this data transfer circuit, 10 is an LS
The data bus is formed inside I or between LSIs, and its load capacitance is represented by C and its wiring resistance is represented by R. A large number of input circuits and a large number of output circuits are connected to the data bus 10. Here, for simplification of description, one bit corresponding to one bit of parallel data transferred by the data bus 10 is used. The minute output circuit 11 and the input circuit 12 are extracted and shown.

The output circuit 11 has a latch circuit 13 for latching internal data in synchronization with the clock signal CK, and a tri-state type output buffer circuit 14 for outputting the latched data of this latch circuit to the data bus 10. .

The input circuit 12 is the data bus 10 described above.
Data signal input Di from the data bus 10
For n, the rising edge is waveform-shaped with reference to the first threshold value (low level input threshold value) VthL lower than the median value of the data signal amplitude, and its falling edge is the second threshold value higher than the median value of the data signal amplitude. It has an input buffer circuit 15 for waveform shaping with (high level input threshold) VthH as a reference, and a latch circuit 16 for latching output data of the input buffer circuit 15 in synchronization with a clock signal CK.

In the microprocessor, for example, each bit stage of a register circuit such as an address register can be used as the latch circuit 16.
FIG. 2 shows a specific example of the input circuit 12 shown in FIG.

This input circuit has a first input buffer circuit 21 for waveform shaping the rising edge of the data signal input Din from the data bus 10 with the first threshold VthL as a reference, and the falling edge of the data signal input for the second input signal. A second input buffer circuit 22 that shapes the waveform with reference to the threshold value VthH of the above, and a selection circuit 23 that selects the output of the first input buffer circuit 21 or the output of the second input buffer circuit 22.
The latch circuit 16 latches the logic level of the output signal of the selection circuit 23 in synchronization with the clock signal CK, and controls the next selection operation of the selection circuit 23 according to the latched logic level.

When the latch data of the latch circuit 16 (corresponding to the past data on the data bus) is at "H" level, the data signal input Di from the data bus 10 is input.
By controlling the output of the second input buffer circuit 22 (corresponding to the current data on the data bus) for shaping the falling edge of n with the high level input threshold VthH as a reference, the data signal is controlled. It is possible to detect the falling edge of the input Din quickly.

On the other hand, the latch data is "L".
In the case of the level, by controlling the rising of the data signal input Din from the data bus 10 to select the output of the first input buffer circuit 21 which shapes the waveform with the low level input threshold VthL as a reference, the data signal Input Di
It is possible to detect the rising edge of n quickly.

FIG. 3 shows an example of operation waveforms when data is transferred from a certain output circuit to a plurality of input circuits in the data bus transfer circuit of FIG. As can be seen from this operation waveform, the data Dout output from the output circuit 11 to the data bus 10 has a blunted signal waveform due to the load capacitance C and the wiring resistance R of the data bus 10, and the vicinity of the input node of the input circuit 12. The rise time tr and the fall time tf of the signal Din are delayed, that is, the output circuit 1
There is a delay in data transfer from 1 to the input circuit 12.

The input circuit 12 waveform-shapes the data signal input from the data bus 10 and then latches it in synchronization with the clock signal CK. In this case, for the falling edge of the data signal input Din, the waveform shaped output is selected and latched with the second threshold value VthH higher than the median value of the signal amplitude as a reference, and for the rising edge of the data signal input Din. The waveform shaped output is selected and latched with the first threshold value VthL lower than the median value of the signal amplitude as a reference.

As a result, it becomes possible to detect a change in the data signal input Din quickly, and the data signal input Di can be detected.
The delay time td from the leading edge of the clock signal CK to the leading edge of the latch data at the falling edge of n and the delay time tup from the leading edge of the clock signal CK to the leading edge of the latch data at the rising edge of the data signal input Din are Shorten,
It is possible to increase the speed of the clock signal CK.

Therefore, even if the load capacitance C and the wiring resistance R of the data bus 10 are large and the rise time and the fall time of the signal at the time of data transfer are long, the high speed data transfer can be achieved and the system speed can be improved. It is possible to achieve speeding up of data transfer that can relax the limit and relax the limit of the system speed.

FIG. 4 shows another specific example of the input circuit 12 in FIG. This input circuit is one threshold variable type input buffer circuit 41 that shapes the waveform of the data signal input Din from the data bus 10 with a predetermined threshold as a reference, and a clock for the logical level of the output signal of this input buffer circuit 41. It is latched in synchronization with the signal φ, and the threshold value of the input buffer circuit 41 is set to the first threshold value Vth according to the latched logic level.
L or a latch circuit 16 for controlling the second threshold VthH.

The threshold variable type input buffer circuit 41.
Are the first to third PMOS transistors P1 to P3 between the power supply potential (Vcc) node and the ground potential (Vss) node.
And the first to third NMOS transistors N1 to N3 are connected in series, the fourth PMOS transistor P4 is connected in parallel to the first PMOS transistor P1, and the fourth NMOS transistor N3 is connected to the fourth NMOS transistor N3. The NMOS transistor N4 is connected in parallel. First P above
MOS transistor P1, second PMOS transistor P2, second NMOS transistor N2 and third N
The gates of the MOS transistors N3 are collectively connected to the data bus 10.

Then, the third PMOS transistor P3
And complementary clock signals φ and / φ are applied to the respective gates of the first NMOS transistor N1 and
Latch data is given from the latch circuit 16 to the respective gates of the PMOS transistor P4 and the fourth NMOS transistor N4, and an inverted signal of the data signal input Din from the data bus 10 is supplied to the third PMOS transistor P3 and the first PMOS transistor P3. It is output from the drain interconnection point of the NMOS transistor N1, and this output is the latch circuit 1.
Enter in 6.

When the latch data of the latch circuit 16 is at "L" level (when the past data on the data bus is at "H" level), the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are Correspondingly, it is turned on / off and the threshold value of the input buffer circuit 41 is set and controlled to the second threshold value (high level input threshold value) VthH higher than the median value of the data signal amplitude. Can be detected quickly.

When the latch data of the latch circuit 16 is at "H" level (when the past data on the data bus is at "H" level), the fourth PMOS transistor P4 and the fourth NMOS transistor P4 are provided. N4 is turned off / on correspondingly, and the threshold value of the input buffer circuit 41 is set and controlled to the first threshold value (low level input threshold value) VthL lower than the median value of the data signal amplitude. It becomes possible to detect the rising edge quickly.

FIG. 5 shows still another specific example of the input circuit 12 in FIG. This input circuit shows an example in which the input circuit as shown in FIG. 2 is applied to the input circuit with a selector connected to the data bus 10 in the microprocessor, for example, 51 is a selector, and the others are shown in FIG. The same symbols as in the inside are attached.

FIG. 6 shows a modification of the data transfer circuit of FIG. This data transfer circuit shows an example in which the input circuit as shown in FIG. 2 is added to the input side of the logic circuit 61 connected to the data bus 10. The same parts as those in FIG. The description is omitted.

FIG. 7 shows a clock signal transfer circuit according to a second embodiment of the digital signal transfer circuit of the present invention.
In this clock signal transfer circuit, 70 is a clock signal line formed inside the LSI, and its load capacity is represented by C and its wiring resistance is represented by R. To this clock signal line 70, one clock signal output circuit 71 and a plurality of clock signal input circuits 72 (only one is shown as a representative) are connected.

The clock signal input circuit 72 raises the rising edge of the clock signal CKin input from the clock signal line 70 to a first threshold value Vth lower than the median value of the clock signal amplitude.
First input buffer circuit 7 that shapes the waveform based on L
3, a second input buffer circuit 74 for shaping the falling edge of the clock signal CKin input from the clock signal line 70 with the second threshold value VthH higher than the median value of the clock signal amplitude as a reference, and the first input buffer circuit 74. Input buffer circuit 7
3 is input to the set input terminal S, and the output of the second input buffer circuit 74 is input to the reset input terminal R. The flip-flop circuit 75 includes a flip-flop circuit 75. The signal is output.

FIG. 8 shows an example of operation waveforms when data is transferred from the clock signal output circuit 71 to the lock signal input circuit 72 in the clock signal transfer circuit of FIG. As can be seen from this operation waveform, the clock signal CKout output from the clock signal output circuit 71 to the clock signal line 70 has a blunted signal waveform due to the load capacitance C and the wiring resistance R of the clock signal line 70. The rise time tr and the fall time tf of the signal near the input node of the input circuit 72 are delayed.

The clock signal input circuit 72 waveform-shapes the clock signal input CKin from the clock signal line 70 and then holds it in the flip-flop circuit 75. In this case, with respect to the fall of the clock signal input CKin, the flip-flop circuit 75 is reset by the output whose waveform is shaped with the second threshold value VthH higher than the median value of the signal amplitude as a reference, and the rise of the clock signal input CKin. As a result, the flip-flop circuit 75 is set by the waveform shaped output with the first threshold value VthL lower than the median value of the signal amplitude as a reference. As a result, it becomes possible to detect a change in the clock signal input CKin quickly, and it is possible to speed up the clock signal transfer.

[0037]

As described above, according to the present invention, the data transfer is performed even when the load capacitance and the wiring resistance of the signal wiring are large and the rise and fall times of the signal at the time of transferring the digital data or the clock signal are long. It is possible to realize a digital signal transfer circuit that can achieve higher speed and relax the system speed limitation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a data transfer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an input circuit in FIG.

3 is a timing waveform chart showing an example of a data transfer operation in the data bus transfer circuit of FIG.

FIG. 4 is a circuit diagram showing another specific example of the input circuit in FIG.

5 is a circuit diagram showing still another specific example of the input circuit in FIG.

6 is a circuit diagram showing a modified example of the data transfer circuit of FIG.

FIG. 7 is a circuit diagram showing a clock signal transfer circuit according to a second embodiment of the present invention.

8 is a timing waveform chart showing an example of a data transfer operation in the clock signal transfer circuit of FIG.

FIG. 9 is a circuit diagram showing an example of a conventional data bus transfer circuit.

10 is a timing waveform chart showing an example of a data transfer operation in the data bus transfer circuit of FIG.

[Explanation of symbols]

10 ... Data bus, 11 ... Output circuit, 12 ... Input circuit,
13 ... Latch circuit, 14 ... Output buffer circuit, 15 ... Input buffer circuit, 16 ... Latch circuit, 21 ... First input buffer circuit, 22 ... Second input buffer circuit, 23 ...
Selection circuit, 41 ... Threshold variable input buffer circuit, 51
... selector, 61 ... logic circuit, 70 ... clock signal line,
71 ... Clock signal output circuit, 72 ... Clock signal input circuit, 73 ... First input buffer circuit, 74 ... Second input buffer circuit, 75 ... Flip-flop circuit.

Claims (6)

[Claims] 1. A signal wiring used in a digital circuit system, an output circuit for outputting a digital signal to the signal wiring, and a rising edge of a digital signal connected to the signal wiring and inputted from the signal wiring. And an input circuit for waveform-shaping the trailing edge thereof with a first threshold value lower than the median value of the digital signal amplitude as a reference and a second threshold value higher than the median value of the digital signal amplitude as a reference. And a digital signal transfer circuit. 2. The digital signal transfer circuit according to claim 1, wherein the signal wiring is a data bus for transferring data, and the input circuit has a rising edge of a data signal input from the signal wiring as a first threshold value. A first input buffer circuit that shapes a waveform with reference to a second input buffer circuit, and a second input buffer circuit that shapes a waveform of a falling edge of a data signal input from the signal wiring with a second threshold as a reference; A selection circuit for selecting an output of the circuit or an output of the second input buffer circuit, and a logic level of an output signal of the selection circuit is latched in synchronization with a clock signal, and the selection circuit of the selection circuit is latched according to the latched logic level. A digital signal transfer circuit, comprising: a latch circuit for controlling a next selection operation. 3. The digital signal transfer circuit according to claim 1, wherein the signal wiring is a data bus for transferring data, and the input circuit uses a data signal input from the signal wiring with a predetermined threshold as a reference. One threshold-variable input buffer circuit for waveform shaping, a logic level of an output signal of the input buffer circuit is latched in synchronization with a clock signal, and the threshold value of the input buffer circuit is set according to the latched logic level. A digital signal transfer circuit comprising: a first threshold value or a latch circuit for controlling the threshold value to the second threshold value. 4. The digital signal transfer circuit according to claim 2, wherein the digital signal transfer circuit is inserted between the selection circuit and the latch circuit and selects an output of the selection circuit and data separately given based on a control signal. A digital signal transfer circuit, further comprising: 5. The digital signal transfer circuit according to claim 1, wherein the latch circuit is a 1-bit register in a data register that holds parallel data of a plurality of bits. Digital signal transfer circuit. 6. The digital signal transfer circuit according to claim 1, wherein the signal wiring is a clock signal line that transfers a clock signal, and the input circuit first rises a clock signal input from the signal wiring.
A first input buffer circuit that shapes the waveform with reference to the threshold value of, and a second falling edge of the digital signal input from the signal wiring.
A second input buffer circuit for shaping the waveform with reference to the threshold value of, and a flip-flop circuit in which the output of the first input buffer circuit is input to the set input terminal and the output of the second input buffer circuit is input to the reset input terminal. And a digital signal transfer circuit.