JPH0756693A - Disk array device and disk writing controller - Google Patents

Abstract

PURPOSE:To attain the efficiency and high speed of the write access of data whose size is especially small by transferring write data to a preliminary disk drive, and storing the data in it before executing a write back processing at the time of the write access. CONSTITUTION:The write cache of storing the write data from a host computer 2 in a cache memory 6 is executed. Afterwards, the write back processing of transferring the write data from the cache memory 6 to each disk drive DD0-DDN is executed. Before the write back processing is executed, the write data are transferred to and stored in a preliminary disk driver DDS by a preliminary disk DMA controller 11S. Also, at the time of the write back processing, when the transfer of the write data from memory 6 to each disk driver DD 0-DDN is imppossible, the write data stored in the preliminary disk drive DDS are read and used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device having a plurality of disk drives and storing data from a host computer in a distributed manner in the respective disk drives.

[0002]

2. Description of the Related Art Conventionally, RAID (Redundant) has been used as an external storage device used in a computer system.
Arrays of Inexpensive Di
Disk array devices, also called sks), are well known. The disk array device has a plurality of disk drives (hard disk devices) and stores the data transferred from the host computer in a distributed manner among the disk drives. Therefore, the host computer looks as if it accesses one hard disk device.

The disk array device has levels 1 to 5
Different schemes have been developed in five stages. For example, in the level 3 method, data is distributed and stored in each disk drive by bit-unit interleaving. The level 4 system is a system provided with a dedicated disk drive for storing parity data for error correction as well as distributing data from the host computer.

Further, in the level 5 system, like the level 4, the data is interleaved in sector units,
It is distributed and stored in each disk drive. The difference between level 5 and level 4 is that level 4 has a dedicated disk drive for parity data, whereas level 5 has
Is that the parity data is distributed and stored in each disk drive.

That is, in the level 5 system, as shown in FIG. 8, data is distributed and stored in logical sector addresses 0 to 11 in a plurality of disk drives DD0 to DD3, and parity data PD1 to PD4 are also distributed. To store.

Here, 1 sector (logical sector address)
In general, 512 bytes of data are stored in. In the disk drives DD0 to DD3, the same physical sector N
4 logical address sectors belonging to (N = 0 to 3) are 1
Configure one parity group. That is, each of the parity data PD1 to PD4 is written at the same byte position as that of each data of each logical address sector forming the parity group. For example, the parity data PD1 constitutes a parity group with the logical address sectors 0 to 2.

In such a level 5 system, even if one disk drive (eg, DD0) fails, the data and parity data PD1 of the remaining three disk drives (DD1 to DD2) are used. The data of a failed disk drive (for example, DD0) can be restored. Therefore, it is possible to ensure high reliability as compared with a single hard disk device.

However, if two or more disk drives fail, the above method cannot restore the data. Therefore, as shown in FIG. 8, a spare disk drive DDs is prepared, and when the failure of the first disk drive occurs, the data is restored by the above method, and the restored data is used as the spare disk drive DDs. The method of copying to is being developed. In this system, the spare disk drives DDs are naturally not accessed until a failure occurs in the first disk drive.

On the other hand, the level 5 system is more effective in accessing data of a smaller size than data having a large transfer data amount (data size) such as image data, as compared with the level 3 system. In the level 3 system, it is necessary to access all of the plurality of disk drives when accessing data for one sector. For this reason, the data transfer speed becomes high, which is convenient for large-size data transfer, but the efficiency decreases in small-unit data access.

However, even in the level 5, when the small size data is write-accessed, it is necessary to rewrite the parity data, so that the performance is deteriorated. Therefore, a device employing a write cache system that uses a cache memory is being developed, especially at the time of write access. That is, for example, in write access for one sector,
The data before rewriting (old user data) and the corresponding parity data (old parity data) are read-accessed. New parity data (new parity data) is generated from these old user data, old parity data, and new write data (new user data). Therefore, for write access for one sector, 2
A total of four accesses are required: read access, new user data write access, and new parity data write access.

In order to solve such a drawback, there is a device which adopts the above write cache system in level 5. In this method, when write data (new user data) is received from the host computer, it is stored in the cache memory and the write command is terminated. After this, when the disk drive is idle (not accessed), write-back processing for writing the write data and the new parity data to each designated sector is executed.

[0012]

In the conventional level 5 disk array device, by adopting the write cache method, it becomes possible to perform write access of small size data at high speed and efficiently. However, this method requires write back processing for transferring data from the cache memory to the disk drive. Before the completion of this write-back process, a failure may occur in the cache memory, or the power supply to the cache memory may stop and the data stored in the cache memory may be destroyed or erased. There is. If such a situation occurs, the write back process becomes impossible. For this reason, the method simply employing the write cache has a problem that the data protection is incomplete and the reliability of the device is low.

In order to improve the reliability, it is conceivable to duplicate the cache memory or the disk array controller, or to use a non-volatile memory or an uninterruptible power supply for the cache memory. However, if such a method is adopted, there are drawbacks that the cost of the entire apparatus increases and the system configuration becomes complicated.

It is an object of the present invention to speed up and improve the efficiency of write access to data of a particularly small size in a disk array device adopting the write cache system, and to increase cost and complicate the system configuration. Without fail, to reliably protect the data and realize the high reliability of the device.

[0015]

According to the present invention, for example, in a level 5 disk array device, a plurality of disk drives including spare disk drives, cache memory means for storing write data, and write back processing at the time of write access are provided. It is a device having a spare disk control means for transferring and storing write data to a spare disk drive before execution.

Further, according to the present invention, during write back processing,
It is a device having a backup control means for reading and using the write data stored in the spare disk drive when the write data cannot be transferred from the cache memory means to each disk drive.

[0017]

According to the present invention, the write cache for storing the write data from the host computer in the cache memory means is executed. After this, a write-back process of transferring write data from the cache memory means to each disk drive is executed. Before executing this write-back process, the spare disk control means transfers the write data to the spare disk drive and stores it.

Further, in the present invention, the backup control means reads and uses the write data stored in the spare disk drive when the write data cannot be transferred from the cache memory means to each disk drive during the write back processing. To do.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a disk array device (R
2 to 4 and 7 are flowcharts for explaining the operation of the embodiment, and FIGS. 5 and 6 show the contents stored in the spare disk drive according to the embodiment. It is a conceptual diagram for explaining.

As shown in FIG. 1, the present apparatus includes a plurality of disk drives DD0 to DDN, one spare disk drive DDs, and a disk array controller (hereinafter simply referred to as controller) 1 for controlling each disk drive. Have. The controller 1 controls the disk drives DD0 to DDN according to the level 5 method. That is, the controller 1 stores the write data transferred from the host computer 2 in a distributed manner in each of the disk drives DD0 to DDN by interleaving in sector units. Further, the controller 1 generates parity data corresponding to the write data and stores it in a distributed manner in each of the disk drives DD0 to DDN. Here, read data or write data transferred to and from the host computer 2 is referred to as user data when distinguished from parity data.

The controller 1 has a microprocessor (CPU) 3, a read only memory (ROM) 4, a read / write memory (RAM) 5, a cache memory 6, a parity generation circuit 7 and an internal bus 8. CPU3
Read / write control of each disk drive DD0 to DDN by a program stored in advance in the ROM 4,
Write back processing and backup processing according to the present invention are executed. The RAM 5 is used as a work memory for the CPU 3. The cache memory 6 is a high speed buffer memory for temporarily storing read / write data. The parity generation circuit 7 is a circuit for generating parity data corresponding to the write data from the host computer 2.

Further, the controller 1 is a host DMA.
Controller (host DMAC) 9, interface 10, disk DMA controller (disk DMA
C) 110-11N, interfaces 120-12
N, spare disk DMA controller (spare DMAC)
11s and interface 12s. The host DMAC 9 controls data transfer between the host bus 13 and the internal bus 8 and writes write data from the host bus 13 to the cache memory 6 at the time of write access related to the present invention.
Transfer to. The interface 10 is connected to the host bus 13 and exchanges data with the host computer 2.

The disk DMACs 110 to 11N control data transfer between the disk drives DD0 to DDN and the internal bus 8 via the respective interfaces 120 to 12N. The spare DMAC 11s controls data transfer between the spare disk drive DDs and the internal bus 8 via the interface 12s.

Next, the operation of the embodiment will be described. (Basic operation) First, referring to the flowchart of FIG.
The basic operation of the level 5 disk array device will be described. When a read / write (R / W) command is transferred from the host computer (host CPU) 2 via the host bus 13, the host DMAC 9 transfers the R / W command to the RAM 5 via the internal bus 8 (step S1,
S2). The CPU 3 decodes the R / W command from the host CPU 2 and converts it into a disk command (step S3). Disc command is for each disc drive DD
This is a command for executing read / write control of 0 to DDN.

The CPU 3 converts the converted disk command into R
Store in AM5. Disc DMAC110-11N
Transfers a disk command instructing a read / write operation from the RAM 5 to each of the disk drives DD0 to DDN. (Read access) If the disk command is a read command (YES in step S4), the disk DMAC
110 to 11N transfer the read command to each of the disk drives DD0 to DDN (step S6). Each of the disk drives DD0 to DDN executes a read access for reading the data of the designated logical sector address (step S7). The disks DMAC110 to 11N transfer the read read data to the cache memory 6 (step S8).

The host DMAC 9 transfers the read data stored in the cache memory 6 to the host CPU 2 via the interface 10 while checking the transfer order (step S9). Here, if the data read operation is impossible due to, for example, a defect on the disk of the disk drive DD0 or data destruction, the CPU 3 executes a data restoration process (step S10). No, S11). That is, CPU3
Reads the user data and the parity data belonging to the same parity group of the unreadable data via the disk DMAC 110, restores the original data based on the parity calculation, and stores it in the cache memory 6. The host DMAC 9 transfers the data restored from the cache memory 6 to the host CPU 2 as read data. C
When the read command ends normally, the PU 3 sends a normal end status to the host CPU 2.

As described above, for example, when a failure occurs in the disk drive DD0, the CPU 3 executes a defect replacement process or substitutes the spare disk drive DDs for the failed disk drive DD0. In this alternative process, the failed disk drive DD
All data stored in 0 are restored and stored in the spare disk drive DDs. After that, the CPU 3 uses the spare disk drive DDs as the regular disk drive DD0.

If the command from the host CPU 2 is a write command (NO in step S4), the CPU 3 executes write access to each of the disk drives DD0 to DDN (step S5). In this embodiment, the host DMAC 9 executes write cache for storing the write data from the host CPU 2 in the cache memory 6.

The write access operation according to this embodiment will be described below with reference to the flowchart of FIG. In the embodiment, the CPU 3 determines the size of write data,
If the write data has a relatively large size, a normal write access operation is executed. If the write data has a relatively small size, the write access operation according to the present invention is executed.

That is, the CPU 3 recognizes the transfer data amount of the write data by the write command transferred by the host DMAC 9, and determines the size of the write data (step S12). At this time, the CPU 3 also detects the usable storage capacity of the cache memory 6. (Large Size Write Access) If the write data is large size data such as image data (NO in step S13), the host DMAC 9 transfers the write data from the host CPU 2 to the cache memory 6 (step S14). ). The CPU 3 uses the parity generation circuit 7 to generate parity data corresponding to the write data and stores it in the cache memory 6 (step S15). That is, the CPU 3 reads the old user data and the old parity data, which are rewrite targets of the write data, and generates new parity data based on these old data. In this case, the cache memory 6 is simply used as a buffer memory.

The disk DMACs 110 to 11N transfer write data and new parity data from the cache memory 6 to the disk drives DD0 to DDN. Each of the disk drives DD0 to DDN stores the write data and the new parity data in the logical sector address designated by the disk command (step S17). C
When all the disk drives DD0 to DDN have normally completed the write command, the PU 3 sends a normal end status to the host CPU 2.

Even during such a write access,
When a failure occurs in the disk drives DD0 to DDN,
Similar to the case of the read access described above, the CPU 3 executes the defect replacement process or substitutes the spare disk drive DDs for the failed disk drive. In this alternative process, all data stored in the failed disk drive DD0 is restored and stored in the spare disk drive DDs. After that, the CPU 3 uses the spare disk drive DDs as a regular disk drive. (Small size write access) If the write data is small size data (YE in step S13)
S), the host DMAC 9 transfers the write data from the host CPU 2 to the cache memory 6 (step S).
18). Next, in the present invention, the spare DMAC 11s transfers the write data stored in the cache memory 6 to the spare disk drive DDs via the interface 12s (step S19). As a result, the spare disk drive DDs stores the write data and backs it up (step S20). At this time, the spare DMAC 11s may directly transfer the write data transferred by the host DMAC 9 to the spare disk drive DDs.

After that, the CPU 3 transfers the write data stored in the cache memory 6 to each of the disk drives DD0 to DD by a background job when the disk drives DD0 to DDN are idle (non-access).
Execute write back processing to be stored in N (step S
21).

In the write-back process, as shown in FIG. 4, the CPU 3 uses the parity generation circuit 7 to generate parity data corresponding to the write data and store it in the cache memory 6 (step S22). Disk D
The MACs 110 to 11N send write data and new parity data from the cache memory 6 to each disk drive D.
The data is transferred to D0 to DDN (step S23). Each of the disk drives DD0 to DDN stores the write data and the new parity data at the logical sector address designated by the disk command (step S24).

The CPU 3 controls the disk drives DD0 to DD0.
When all DDNs have normally completed the write command, the host CPU 2 transmits a normal end status (YES in step S25). The write data is backed up in the spare disk drive DDs until such a write back process ends normally.

Here, before the write-back processing ends normally, a failure occurs in the cache memory 6, or the power supply to the cache memory 6 is stopped, and the data stored in the cache memory 6 is destroyed or destroyed. It is assumed that a situation such as erasing occurs (NO in step S25).
The spare DMAC 11s reads the backup write data to the spare disk drive DDs according to the instruction from the CPU 3 (step S26). Disk DM
The ACs 110 to 11N write back the write data read from the spare disk drive DDs to the designated logical sector address (step S27). At this time, the CPU 3 uses the parity generation circuit 7 to newly generate parity data corresponding to the write data.

In this way, when writing small size write data, it is stored in the cache memory 6 and backed up in the spare disk drive DDs. By this write cache and backup process,
The write command ends. After this, the host CPU2
Read / write access from each disk drive DD0-DDN is idle, the cache memory 6
Write-back processing of write data is executed for each of the disk drives DD0 to DDN.

The write data backed up in the spare disk drive DDs is stored until the write back process is completed. Before the write-back processing is completed, when the cache memory 6 fails or the power supply is stopped and the write-back processing becomes impossible, the write data backed up in the spare disk drive DDs is used. To be done. Therefore, as a result, the write data is always reliably protected, and the reliability of the device can be improved.

By the way, the disk drives DD0 to DD
When a failure occurs in N, data recovery processing is executed using the spare disk drive DDs, as in the case of accessing the large-sized write data. At this time, first, all write data stored in the cache memory 6 is written back. After this, all the data stored in the failed disk drive is restored and stored in the spare disk drive DDs. After that, the write cache is prohibited, the cache memory 6 is used as a simple buffer memory, and the CPU 3 uses the spare disk drive DDs as a regular disk drive. (Operation of Spare Disk Drive DDs) Next, the operation of the spare disk drive DDs according to the present invention will be specifically described with reference to FIGS.

First, the CPU 3 uses the spare disk drive D.
When performing write access to Ds, a sequential write command is output. That is, as shown in FIG. 5, the sector address to be accessed sequentially increases from the initial value (address 0), and block data in sector units are sequentially stored at each address. In this embodiment, when all the write data stored in the cache memory 6 is written back to the respective disk drives DD0 to DDN, the sector address of the spare disk drive DDs returns to the initial value. In addition, by one write command,
The number of blocks that can be written is large enough to ignore the overhead of command and status exchanges.

As shown in the flow chart of FIG.
U3 outputs the sequential write command,
The write data to be backed up is controlled to be written in the spare disk drive DDs (step S3).
0). Here, in the case of the write access of the write data of the large size, since there is no write data to be backed up, the CPU 3 generates a null block (dummy data) in the RAM 5 (NO in step S31, S
32). The spare DMAC 11s transfers the null block generated by the CPU 3, and stores the null block in the sector address 0, for example, as shown in FIG. 5 (step S33).

On the other hand, when write data of a small size to be backed up is transferred from the host CPU 2, the write data is stored in the cache memory 6 and the write back process is executed as described above (step S31).
YES, S34). CPU3 produces | generates the header block of 1 block length in RAM5 (step S35).
The spare DMAC 11s transfers the header block from the RAM 5 to the spare disk drive DDs, and stores it, for example, in the sector address 2 (step S36). Subsequently, the spare DMAC 11s transfers the write data (user data) from the cache memory 6 to the spare disk drive DDs and stores it in, for example, the sector addresses 3 to 6 (step S37).

Here, the spare DMAC 11s continuously transfers the null block and the header block so that the standby state of the disk rotation of the spare disk drive DDs does not occur when the write data is transferred. The CPU 3 transfers the null block after transferring the write data, and shifts to the write back process (YES in steps S38 and S39).
That is, the write data stored in the cache memory 6 is written back to each of the disk drives DD0 to DDN (step S40). When the write data is written back, the CPU 3 generates a complete block (C block) in the RAM 5 (step S41). The spare DMAC 11s transfers the complete block from the RAM 5 to the spare disk drive DDs and stores it in the sector address 8 (step S42).

Here, each of the null block, the header block and the C block is 512 as shown in FIG.
Consists of a data length of bytes. The null block has a 1-byte null code (for example, 00h) and a 1-byte backup ID code (hereinafter simply referred to as ID). The remaining bytes consist of invalid data. The null code is a code indicating that user data does not exist in the block (sector).

The header block has a 1-byte header code (for example, 01h), a 1-byte ID, a 1-byte command tag, and a write command transferred from the host CPU 2. The header code is a code indicating that it is the beginning of the user data. The C block has a 1-byte complete code (for example, 02h), a 1-byte ID, and a 1-byte command tag. The user data (write data) that could not be written back when the ID and command tag cannot be written back.
Used to search for. As for ID, sequential write is executed to the spare disk drive DDs,
It is incremented by "1" when the address returns to the initial value. When retrieving the user data that has not been written back, the sector address (from the initial value) of the spare disk drive DDs is read sequentially and is different from the ID of the content of the initial value address (null block or header block). Lead until you find the ID. During this read period, the C block corresponding to the header block is checked, and if there is a header block in which the corresponding C block is not found, it is a write command that was not written back. Then, since user data is written from the block next to the header block, this user data is read out and transferred to each of the disk drives DD0 to DDN to perform data restoration processing.

In this way, when the small size write data is transferred to each of the disk drives DD0 to DDN, the spare disk drive DDs is used for data backup. Spare disk drive DDs
Then, the header block is stored at the beginning of the write data (user data), and the C block is stored after the end of the write back process. Even when there is no write data, C
PU3 sends a write command to the spare disk drive DDs.
Is output to. In this case, the spare DMAC 11s
Repeatedly transfers the null block generated by the CPU 3.

When the write data to be backed up is transferred from the host CPU 2 and stored in the cache memory 6, the CPU 3 generates a header block and the spare D
Transfer to the spare disk drive DDs via the MAC 11s. After that, the write data stored in the cache memory 6 is transferred to the spare disk drive DDs, and the process returns to the transfer of the null block. Then, when the write-back processing is completed, the CPU 3 generates the C block, and the spare disk drive DDs is generated via the spare DMAC 11s.
Transfer to.

In the system using the spare disk drive DDs as described above, since the backup process using the spare disk drive DDs is the sequential write access, the seek time of the head of the drive DDs and the disk rotation waiting time. Is almost zero.
If the backup method using the spare disk drive DDs and the write cache method are used together, a high-speed access by the write cache method and a data protection function by the backup method can be realized. Therefore, as a result, to obtain the same performance and reliability as the disk array device with the uninterruptible power supply unit with dual write cache, and at the same cost as the device without the uninterruptible power supply unit without duplicated write cache. You can

When a failure occurs in the spare disk drive DDs, the other disk drives DD0-D0
As with the DN failure, the controller 1 is the host CPU
2 or alarm is issued to the operator.
At this time, the CPU 3 writes back all the contents of the cache memory 6, and stops the write cache operation using the cache memory 6 until the repair or replacement of the spare disk drive DDs is completed.

Before the write back process is completed,
In case the power of the device is turned off, the CPU 3 may perform the header block and C block check of the spare disk drive DDs immediately after the power is turned on. However, it is considered that the probability that both the cache memory 6 and the spare disk drive DDs fail at the same time before the write-back process is completed is almost zero.

[0051]

As described above in detail, according to the present invention, in the disk array device adopting the write cache system, the spare disk drive is used for backup of the write data, so that the cache memory and the disk array are -Achieve high-speed write access and reliable data protection for small data without adopting a dual controller or using a non-volatile memory or uninterruptible power supply for cache memory. You can Therefore, without increasing the cost or complicating the system configuration, it is possible to achieve high-speed and efficient write access of particularly small-sized data, and to reliably protect the data and realize the high reliability of the device. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a disk array device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

FIG. 4 is a flowchart for explaining the operation of the embodiment.

FIG. 5 is a conceptual diagram for explaining stored contents of a spare disk drive according to the embodiment.

FIG. 6 is a conceptual diagram for explaining stored contents of a spare disk drive according to the embodiment.

FIG. 7 is a flowchart for explaining the operation of the embodiment.

FIG. 8 is a conceptual diagram for explaining the configuration of a conventional level 5 disk array device.

[Explanation of symbols]

1 ... Disk array controller, 2 ... Host computer, 3 ... CPU, 6 ... Cache memory, 7 ... Parity generation circuit, 9 ... Host DMA controller, DD
0-DDN ... Disk drive, 110-11N ... Disk DMA controller, DDs ... Spare disk drive, 11s ... Spare disk DMA controller.

Claims (4)

[Claims] 1. A plurality of disk drives including a spare disk drive, a cache memory means for storing write data transferred from the outside, and the write data for each disk drive except the spare disk drive from the cache memory means. And a spare disk control means for transferring the write data to the spare disk drive and storing the write data before executing the write-back process for transferring the write data. 2. A plurality of disk drives including a spare disk drive, a cache memory means for storing write data transferred from the outside, and the write data in each of the disk drives except the spare disk drive from the cache memory means. A write-back process for transferring the write data to the spare disk drive and storing the write data in the spare disk control unit, and during the write-back process, the cache memory unit transfers the write data to each of the disk drives. A disk array device comprising: backup control means for reading and using the write data stored in the spare disk drive when the write data cannot be transferred. 3. A plurality of disk drives including a spare disk drive, a cache memory means for storing write data transferred from the outside, and a size of the write data relative to each other based on a transfer data amount of the write data. Mode determination means for determining a mode in which the spare disk drive is used as a backup when it is small, and writeback for transferring the write data from the cache memory means to each of the disk drives other than the spare disk drive in the mode. A disk array device comprising a spare disk control means for transferring and storing the write data to the spare disk drive before executing the processing. 4. In a disk system having a plurality of disk drives including a spare disk drive, cache memory means for storing write data transferred from the outside, and the write data stored in the cache memory means as the spare. Each of the identification information of the write data, the invalid data substituting for the write data, and the instruction information for instructing that the write data is stored in each of the disk drives other than the spare disk drive during backup control for storing in the disk drive Data generating means for generating the invalid data, the identification information at consecutive addresses of the spare disk drive during the backup control,
A disk write control device comprising: a data write control means for sequentially writing the write data and the instruction information.