JPH0756555B2 - Film feeder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film feeding device, and more particularly to a film feeding device for automatically performing shutter release and film winding of a camera.

In the conventional film feeding device equipped with a mechanical film counter, "S ...
It was supposed to display such as. But,
The conventional film feeding device equipped with an electric film counter is not provided with means for positively indicating that the film is being fed, and whether or not the user is feeding the film. There was an inconvenience that I could not confirm.

In view of the above-mentioned point, an object of the present invention is to provide a film feeding apparatus provided with an electric display means for displaying that the film is being fed in the air.

In the present invention, in order to electrically indicate that the film is being fed, based on the instruction means for outputting the idling start signal to instruct the start of the film idling, and the idling start signal. Jump feed executing means for performing film jump, a plurality of display elements formed to indicate the feeding state at the time of film jump, and a plurality of display elements are driven at the start of film jump In addition, the number of display elements to be driven is gradually reduced, and the film feeding device is provided with display element driving means for stopping the driving of all the display elements at the end of the idling. Can be notified to the user, and the user can be given a sense of security.

Hereinafter, the present invention will be described based on an embodiment shown in the drawings.

1A and 1B show an electric circuit of a motor drive device which is a film feeding device showing an embodiment of the present invention. This motor drive device has a release switch for starting the shutter release of the camera.
S ₁ is provided, and this release switch S ₁ is made of a normally open switch, and when a release button (not shown) provided on the motor drive device is pressed, the release switch S ₁ is held for the same time. S ₁ is closing. One end of this switch S ₁ is grounded, and the other end is connected to a power source (see FIG. 8) which takes a potential −V _EE2 via a diode D ₁ and a resistor R ₄ in series. The other end of the switch S ₁ is connected to a connection contact J ₅ that connects the motor drive device and the power supply device. The connection point between the diode D ₁ and the resistor R ₄ is connected to the input terminal of the inverter N4, the output terminal of the inverter N4 is connected to the other input terminal of the NAND gate A7, and the NAND gate A3. It is also connected to the other input terminal. One input end of the NAND gate A3 is
The output terminal of the NAND gate A3 is connected to the output terminal of the NAND gate A6, and the output terminal of the NAND gate A3 is connected to the input terminal and the NAND gate of the inverter N5.
It is connected to the other input terminal of A5 and the other input terminal of the NAND gate A6, respectively.

The output terminal of the inverter N5 is connected to each reset signal input terminal of a plurality of flip-flop circuits which are cascaded to form a binary counter BC1. The binary counter BC1 after closing of the release Sui Tutsi S _1, until the release signal camera is crocodile transmitted, i.e.,
The drive motor M1 starts to rotate and the motor drive device counts a predetermined time (for example, 60 ms) to hold the shutter release signal in the camera until the camera release mechanism is activated through the mechanical connection mechanism. The pulse signal of frequency f ₃ is input from the frequency dividing circuit 60 to the input terminal of the flip-flop circuit in the first stage. The output terminal of the final flip-flop circuit of the binary counter BC1 is connected to the NAND gate via the inverter N6.
It is connected to one input terminal of A4. The output terminal of the NAND gate A4 is connected to one input terminal of the NAND gate A5,
The output terminal of the NAND gate A5 is connected to the other input terminal of the NAND gate A4, and both the NAND gates A4 and A5 form an RS flip-flop circuit. Further, the output terminal of the NAND gate A5 is connected to one input terminal of the NAND gate A6, and the output terminal of the NAND gate A6 is the three input terminals of one input terminal of the NAND gate A41. The second input terminal of the NAND gate A11, one input terminal of the NAND gate A7, and one input terminal of the NAND gate A3 are respectively connected.

The inverter N4 to N6, a NAND gate A3~A6 and binary counter BC1, depending on the closure of the release Sui Tutsi S _1,
Regardless of the length of the closing time, a shutter release signal holding circuit that outputs a signal of'L 'level for a predetermined time is formed, and this shutter release signal holding circuit and the NAND gate A7 are According to the closing of the release switch S ₁ , when the closing time is shorter than the predetermined time, a signal of'H 'level is output for a predetermined time, and when the closing time is longer than the predetermined time. It forms a circuit that outputs an'H 'level signal during the closing time. That is, as shown in FIG. 2A, when the closing time of the release switch S ₁ is shorter than the predetermined time, the inverter
The outputs of N4 to N6, the NAND gates A3 to A5 and the binary counter BC1 change as shown in FIGS. 2 (b) to (h), and the outputs of the NAND gates A6 and A7 are shown in FIGS. 2 (i) and (i). The output as shown in j) is obtained. Further, as shown in FIG. 3 (a), when the closing time of the release switch S ₁ is longer than the predetermined time, the outputs of the inverters N4 to N6, the NAND gates A3 to A5 and the binary counter BC1 are the third output.
Change as shown in Figures (b) to (h), and the NAND gate A6
Outputs shown in FIGS. 3 (i) and 3 (j) are obtained at the output terminals of A7 and A7.

The output terminal of the NAND gate A7 is connected to the input terminal of the inverter N7 and the second input of the 3-input NAND gate A1 is connected.
Is connected to the input end of. The first of this NAND gate A1
The input end of is connected to the down terminal dw of the camera switch S ₂ provided with the camera on the armature through an inverter N1 and a connection contact (not shown). This camera switch S ₂
The movable contact piece is formed by a switching switch that switches between the up terminal up and the down terminal dw according to the elevation of the movable reflecting mirror of the camera, and the up terminal up is connected to a motor drive device via a connection contact not shown. Grounded with a rope. Further, between the up terminal up and the down terminal dw, a resistor R ₁ in which the motor drive device is arranged in the arm is connected through a connection contact (not shown). In addition, the camera switch
The movable contact terminal of S ₂ has a potential of − through a resistor R ₂ (R ₂ << R ₁ ).
Inverter N2 is connected to the power supply that takes V _EE2
Is connected to the input end of. The output terminal of the inverter N2 is
It is connected to the third input terminal of the NAND gate A1 and is also connected to one input terminal of the NAND gate A2.
The other input end of the NAND gate A2 is connected to the output end of the inverter N1. The output terminal of the NAND gate A1, the resistance R ₃
Is connected to the base of PNP type transistor T ₁ through, and the emitter of transistor T ₁ is PNP type transistor T ₂
At the base of the, the collector is connected to the collector of the transistor T ₂ , respectively, and the collector is connected to the connection contact J ₄ connecting the motor drive device and the power supply device.
The output terminal of the NAND gate A2 is connected to the first input terminal of the 5-input NAND gate A15 and the first input terminal of the 6-input NAND gate A16 via the inverter N3.

The output terminal of the inverter N2 is also connected to the input terminal of the inverter N12, the other input terminal of the NAND gate A22, and the other input terminal of the NAND gate A19, respectively. The output terminals of the inverter N12 are connected in cascade to form a binary counter B.
It is connected to each reset signal input terminal of the four flip-flop circuits forming C2. Binary counter
The input end of the flip-flop circuit in the first stage of BC2 is connected to the output end of the inverter N11, and the input end of the inverter N11 is connected to the oscillation circuit composed of the inverters N8, N9, the capacitor C ₁ and the resistor R ₅ . . The oscillator circuit, the output terminal of the inverter N8 is connected to the input end of the one end and the inverter N9 resistor R ₅ through a capacitor C _1, the other end and output end input terminal of the inverter N8 inverter N9 resistor R ₅ The output terminal of the inverter N8 serves as the output terminal of the oscillation circuit. The output terminal of the inverter 11 is also connected to the input terminal of the frequency _dividing circuit 60, and the output terminal of the frequency _dividing circuit 60 has frequencies f _{1 to} f _n (n Is an arbitrary positive integer) pulse signal can be obtained. These pulse signals (f _{1 to} f _n )
Are used as input pulse signals of various circuits in the motor drive device. The output terminal of the flip-flop circuit at the final stage of the binary counter BC2 is connected to one input terminal of the NAND gate A18 and the input terminal of the flip-flop circuit F1 via an inverter N16. The reset signal input terminal of the flip-flop circuit F1 is connected to the output terminal of the inverter N12, and the output terminal is connected to one input terminal of the NAND gate A21 via the inverter N17. The output terminal of the NAND gate A18 is connected to one input terminal of the NAND gate A19, and the NAND gate A19 is connected.
Of the NAND gate A18 is connected to the other input terminal of the NAND gate A18, and the NAND gates A18 and A19 form an RS flip-flop circuit. The output terminal of the NAND gate A18 is
It is also connected to the first input terminal of the 3-input NAND gate A11 and one input terminal of the NAND gate A23, and the output terminal of the NAND gate A19 is connected to the input terminal of the first stage flip-flop circuit of the binary counter BC3 via the inverter N18. In addition to being connected, it is also connected to one input end of the NAND gate A48 (see FIG. 1 (B)).

The output terminal of the NAND gate A21 is connected to the NAND gate A
22 is connected to one input terminal of the NAND gate A22, and the output terminal of the NAND gate A22 is connected to the other input terminal of the NAND gate A21. The NAND gates A21 and A22 form an RS flip-flop circuit. The output terminal of the NAND gate A22 is connected to the other input terminal of the NAND gate A23, and the output terminal of the NAND gate A23 is connected to one input terminal of the NAND gate A24. The other input end of the NAND gate A24 is connected to the output end of the inverter N28, and the output end of the NAND gate A24 is connected to the D latch circuit DF1 (FIG. 1 (B)).
(See) Clock signal input terminal CK.

The binary counter BC3 is formed by cascade-connecting two flip-flop circuits, and serves to count the number of idle feed frames when the film is idle-fed.
Reset signal input terminal of each flip-flop circuit of the binary counter BC3 is connected to the other end of the lid switch S ₃ after the camera is crocodile disposed via a connection contact (not shown). The rear lid switch S ₃ is for detecting the opening / closing of the rear lid of the camera, and is adapted to be closed when the rear lid is opened. One end of the rear cover switch S ₃ is installed with a motor drive device through a connecting contact (not shown), and the other end is connected to a power supply that takes a potential −V _EE2 through a connecting contact (not shown) and a resistor R ₉ . . A rear lid lock switch S ₁₄ is connected in parallel with the rear lid switch S ₃ .
The rear lid lock switch S ₁₄ is a switch that is closed by opening the rear lid and is for detecting whether or not the rear lid is securely closed. The other end of the rear cover switch S ₃ is connected to one input terminal of the NAND gate A34, the other input terminal of the NAND gate A34 is connected to the other end of the device type detection switch S _15. The type detection switch S ₁₅ is filed in switch which is closed when mounting the camera compatible models to the motor drive device is used to determine the suitability of the motor drive unit and the camera.
Accordance connexion, when equipped with a camera of incompatible type motor drive unit, by type detection switch S ₁₅ is not closed, and summer as functions of the motor drive device is limited. That is, as will be described in detail later, this motor drive device, when equipped with a compatible camera,
It is designed to exhibit various functions such as shutter release and film hoisting function, subtraction counter function, automatic jump feed / reset and its display function, and film rewinding and its display function. When installed, only the shutter release and film winding function and the subtraction counter function can be exerted. Therefore, the camera of the non-conforming model does not mean a camera that cannot be used for this motor drive device at all, but it does not have a corresponding connection contact between the camera and the motor drive device. Is not enough, and it means a camera in which the specific function of the motor drive device is not exhibited. Therefore, it is different from the unusable camera described later.

One end of the model detection switch S ₁₅ is grounded, and the other end is connected to a power supply that takes a potential −V _EE2 through a resistor R ₁₁ and is also connected to a first input end of a 4-input NAND gate A26. . The output terminal of the NAND gate A34 is
It is connected to the other input end of the NAND gate A27 and the second input end of the three-input NAND gate A28, respectively, and is also connected to the input end of the inverter N24. The output terminal of the inverter N24 is connected to the other input terminal of the NAND gate A36 via the inverter N26, and is connected to each reset signal input terminal of the three flip-flop circuits which are cascaded to form the binary counter BC4. It is connected.

The output terminal of the flip-flop circuit at the first stage forming the binary counter BC3 has a decoder 30 through an inverter N19.
(See FIG. 1 (B)), the output terminal of the flip-flop circuit of the latter stage forming the binary counter BC3 is connected to the 4-input NAND gate A via the inverter N21.
It is connected to the third input terminal of 26 and the input terminal of the decoder 30, respectively. The second input of NAND gate A26
It is connected to the output terminal of the inverter N54 (see FIG. 1 (B)). The output terminal of the NAND gate A26 is
One input end of the NAND gate A27, one input end of the NAND gate A58 (see FIG. 1B) and the decoder 30 are respectively connected, and the output end of the NAND gate A27 is connected to the NAND gate A27.
It is connected to the fourth input of 26 and the first input of NAND gate A28. The output terminal of the NAND gate A28 is connected to one input terminal of the NAND gate A29.
The output of 29 is connected to the third input of NAND gate A28. The output terminal of the NAND gate A28 is connected to the other input terminal of the NAND gate A29, and is also connected to one input terminal of the NAND gate A42 via the inverter N23.

A pulse signal of frequency f ₄ is applied from the frequency dividing circuit 60 to the input terminal of the flip-flop circuit in the first stage of the binary counter BC4, and the output terminal of the flip-flop circuit in the last stage is NAND gate via the inverter N25. It is connected to one input terminal of A35. The output terminal of the NAND gate A35 is connected to one input terminal of the NAND gate A36, the output terminal of the NAND gate A36 is connected to the other input terminal of the NAND gate A35, and both the NAND gates A35 and A36 are R
S flip-flop circuit is formed. Nand Gate A
The output terminal of the NAND gate A42 is connected to the other input terminal of the NAND gate A38 and the other input terminal of the NAND gate A39, and is also connected to the other input terminal of the NAND gate A42. A
9 and the third input of the NAND gate A8, respectively. The output terminals of the NAND gate A36 are cascaded to form a binary counter BC5,
Each of the three flip-flop circuits is connected to each reset signal input terminal. A pulse signal of frequency f ₅ is applied from the frequency dividing circuit 60 to the input terminal of the first-stage flip-flop circuit of the binary counter BC5, and the output terminal of the last-stage flip-flop circuit is connected to the NAND gate A37 via the inverter N27. Is connected to one input end. The output terminal of the NAND gate A37 is connected to one input terminal of the NAND gate A38, the output terminal of the NAND gate A38 is connected to the other input terminal of the NAND gate A37, and both NAND gates A37 and A38 form an RS flip-flop circuit. ing. The output terminal of the NAND gate A38 is connected to one input terminal of the NAND gate A39, and the output terminal of the NAND gate A39 is connected to the other input terminal of the NAND gate A41.
The output terminal of the NAND gate A41 is connected to the other input terminal of the NAND gate A24 and the other input terminal of the NAND gate A29 via an inverter N28.

A second input terminal of the NAND gate A8 is switching switch continuous shooting and one-frame shooting (hereinafter, referred to as continuous single switching switch the switch) is connected to one frame shooting terminal b of S _7.
The movable contact terminal of the continuous / single switching switch S ₇ is grounded, and the continuous shooting terminal a is an idle terminal. In addition, the one-frame photographing terminal b of the continuous / single switching switch S ₇ is connected to the power source which takes the potential −V _EE2 through the resistor R ₆ , and the motor drive device and the power source device through the diode D ₂ in the reverse direction. It is connected to the connection contact J ₁ which connects with. The output terminal of the NAND gate A8 is connected to the third input terminal of the NAND gate A15. The output terminal of the inverter N7 is connected to one input terminal of the NAND gate A9,
The output terminal of the NAND gate A9 is connected to the second input terminal of the NAND gate A15. In addition, the above NAND gate A1
The output terminal of 1 is connected to one input terminal of the NAND gate A12, and the output terminal of the NAND gate A12 is connected to the third input terminal of the NAND gate A11. The other input end of the NAND gate A12 is connected to the output end of the NAND gate A14, and the output end of the NAND gate A11 is the second end of the NAND gate A16.
Is connected to the input end of.

On the other hand, the motor drive device is provided with a motor switch S ₆ that switches according to the shutter release and film winding. The movable contact terminal of this motor switch S ₆ is grounded, and the hoisting terminal a has a potential -V through the resistor R _7.
EE2 is connected to the power supply and the inverter N14
And is connected to the other input end of the NAND gate A14. Further, the release terminal b of the motor switch S ₆ is connected to a power source which takes a potential −V _EE2 through a resistor R ₈ and also connected to one input end of a NAND gate A 13 through an inverter N 13. The output terminal of the NAND gate A13 is connected to one input terminal of the NAND gate A14, the output terminal of the NAND gate A14 is connected to the other input terminal of the NAND gate A13, and both the NAND gates A13 and A14 form an RS flip-flop circuit. . The output terminal of the NAND gate A14 is connected to the third input terminal of the NAND gate A16, and the fourth end of the NAND gate A15 is connected via the inverter N15.
It is also connected to the input end of.

The camera is provided with an R clutch switch S ₁₇ and a film switch S ₁₈ , respectively, and the motor drive device is provided with an R lever switch S ₁₆ . The film switch S ₁₈ is a switch for detecting whether or not a film is loaded in the camera, and opens when the film is loaded and closes when the film is not loaded. It is becoming like this. One end of this switch S ₁₈ is grounded to the motor drive device through a connection contact (not shown), and the other end is connected to a power supply having a potential −V _EE2 through a connection contact (not shown) and a resistor R _12. There is. Further, the R Kuratsuchisuitsuchi S ₁₇ is filed with switch associated with clutch mechanism for the film of the rewind, and summer as (closed) in the rewinding state. One end of the switch S ₁₇ is grounded to the motor drive device through a connection contact (not shown), and the rear end is connected to a power supply having a potential −V _EE2 through a connection contact (not shown) and a resistor R _13. There is. Furthermore, the R Rebasuitsuchi S ₁₆ is filed with switch interlocked with R lever for rewind provided in the motor drive device (not shown), and summer as to close when rewind. One end of the R lever switch S ₁₆ is grounded, and the other end is connected to the fifth input end of the NAND gate A15 and the fourth input end of the NAND gate A16 via the inverter N29, and the three-input NAND gate A43 is connected. Is connected to the first input end of. The second input terminal of the NAND gate A43 is the other end of R Kuratsuchisuitsuchi S _17, the third input terminal is connected to the other end of the film Sui Tutsi S ₁₈ via the inverter N31. The output terminal of the NAND gate A43 is connected to the input terminal of the inverter N35 and one input terminal of the NAND gate A47, respectively.

The fifth input end of the NAND gate A16 is connected to the output end of the NAND gate A53 (see FIG. 1B), and the sixth input end of the NAND gate A16 is connected to the connection contact J ₁₂
(See FIG. 1 (B)).

The output terminals of the NAND gates A15 and A16 are connected to one and the other input terminals of the NAND gate A17, respectively, and the output terminal of the NAND gate A17 is the input terminal of the inverter N32 and each flip-flop circuit forming the binary counter BC6. They are connected to the reset signal input terminal and the input terminal of the inverter N34, respectively. The output terminal of the inverter N32 is connected to the base of the PNP transistor T ₃ via a resistor R _15, emitter of the transistor T ₃ is grounded, NPN type transistor T ₄ the collector through a resistor R ₁₆
Connected to the base of. The collector of the transistor T ₄ is connected to the base of the PNP type transistor T ₅ through the resistor R ₁₇ , and the emitter of the transistor T ₄ is connected to the base of the NPN type transistor T ₆ . Above transistor T ₅
The emitter is grounded, and the collector is connected to the collectors of the one and the NPN type transistor T ₉ of the driving motor M1. The collector of the transistor T ₆ is
The emitter is connected to the other end of the drive motor M1, and the emitter is connected to a connection contact J ₆ that connects the motor drive device and the power supply device. Further, the collector of the transistor T ₆ is connected to the connection contact J ₆ via the diode D ₃ in the reverse direction, and is also connected to the collector of the PNP type transistor T ₇ . The emitter of the transistor T ₇ is grounded, and the base is connected to the emitter of the PNP type transistor T ₈ . The collector of the transistor T ₈ is connected to the connection contact J ₆ through the resistor R _18, the base is connected to the output terminal of the inverter N36 via a resistor R _19. Inverter N36
The input end of is connected to the output end of the inverter N35. Emitter of the transistor T ₉ is connected to the connection contacts J _6, the base is connected to the collector of the PNP transistor T ₁₁ via a resistor R _20. The emitter of the transistor T ₁₁ is grounded, and the base is connected to the output terminal of the inverter N37 through the resistor R ₂₁ . Inverter N
The input end of 37 is connected to the output end of NAND gate A47. The transistor T ₃ ~T _9, T _11, the diode D ₃ and resistor R ₁₅ to R ₂₁ forms a driving circuit 12 of the motor M1 (see FIG. 8).

The binary counter BC6 is formed by connecting a plurality of flip-flop circuits in cascade, and serves to count a fixed time during which the drive motor M1 is braked. This 2
A pulse signal of frequency f ₄ is input from the frequency dividing circuit 60 to the input terminal of the first stage flip-flop circuit of the binary counter BC6, and the output terminal of the last stage flip-flop circuit is
It is connected to one input terminal of a NAND gate A44 via an inverter N33. The output terminal of the NAND gate A44 is connected to one input terminal of the NAND gate A45,
Is connected to the other input terminal of the NAND gate A44, and both NAND gates A44 and A45 form an RS flip-flop circuit. The other input terminal of the NAND gate A45 is connected to the output terminal of the inverter N34, and the output terminal is connected to one input terminal of the NAND gate A46.
The other input terminal of 46 is connected to the output terminal of the inverter N34. The output terminal of the NAND gate A46 is the NAND gate A47.
Of the NAND gate A47, and the output terminal of the NAND gate A47 is connected to the input terminal of the inverter N37.
The binary counter BC6, the inverters N33, N34, N37 and the NAND gates A44 to A47 form a brake circuit for braking the drive motor M1 for a certain period of time. That is, when the output of the NAND gate A17 is inverted 'L' level, the output of the inverter N32 becomes 'H' level, the transistor T ₃ through T ₆
Are turned off, the power supply to the motor M1 is cut off, and at the same time, the binary counter BC6 is reset and the output of the counter BC6 becomes “L” level, and one input end of the NAND gate A44 becomes “H”. Since the other input terminal of the level and NAND gate A45 becomes'H 'level, the output of the NAND gate A46 becomes'L' level, the output of the inverter N37 becomes'L 'level, and the transistors T ₁₁ and T ₉ are turned on. Then, both ends of the motor M1 are short-circuited, so that the motor M1 is braked. When the output of the binary counter BC6 is inverted to the "H" level after a certain period of time, one input end of the NAND gate A44 becomes the "L" level and one input end of the NAND gate A46 becomes the "L" level. Therefore, the output of the NAND gate A46 is inverted to the “H” level, the output of the inverter N37 becomes the “H” level, the transistors T ₁₁ and T ₉ are turned off, and the control of the motor M1 is released.

Turning to FIG. 1B, the other input end of the NAND gate A48 is connected to the output end of the NAND gate A54, and the output end of the NAND gate A48 is connected to one input end of the NAND gate A49. . The other input end of the NAND gate A49 is connected to the output end of the NAND gate A56, and the output end is connected to one input end of the NAND gate A51. The other input end of the NAND gate A51 is connected to the output end of the NAND gate A52, and the output end thereof is connected to the clock signal input end CK of the BCD (Binaly Coded Decimal) down counter 10 via an inverter N38. BC
The D down counter 10 is a counter that counts down by 1 each time a photo is taken from the set number of film frames, and has seven input terminals A _{I to} G _I and seven output terminals A _{O to} G _O. Each has its own lower 4 bits input end
A _{I to} D _I and output terminals A _{O to} D _O correspond to the first digit of decimal number,
The input terminals E _{I to} G _I and the output terminals E _{O to} D _{O of the} upper 3 bits correspond to the second digit of the decimal number. This BCD down counter 10
Input terminals A _{I to} G _I are respectively connected to output terminals Q _{A to} Q _G of the D latch row 20, and output terminals A _{O to} G _O are input terminals D _{A to} D _{G of the} D latch row 20. Respectively connected to. The output terminals A _{O to} G _O of the BCD down counter 10 are connected to the input terminals of the decoder 30 (see FIGS. 5A and 5B), and the output terminal of the decoder 30 is connected to the driver 40. The driver 40 is connected to the input end, and the output end of the driver 40 is connected to the drive electrodes of a liquid crystal display (LCD) 50 as a display device.

The decoder 30 is constructed by connecting NAND gates A101 to A135 and inverters N101 to N138 as shown in FIGS. 5 (A) and 5 (B). The outputs of the NAND gates A104 and A109 are the liquid crystal display 50 shown in FIG.
The signals for driving the electrodes for displaying the camera rewinding member set and the electrodes for reversing the motor driving device rewinding member are respectively output, and the outputs of the inverters N106 to N111 are the motor driving device rewinding member set, During the film rewinding, it is a signal for driving each electrode for displaying the opening of the rear lid, loading the film, closing the rear lid, and pressing the reset button. In addition, the outputs of the inverters N116 to N125 are liquid crystal displays.
This is a signal for driving the first digit of the electrode for displaying the remaining number of 50 frames, and the outputs of the inverters N134 to N138 are the signals for driving the second digit. In addition, Nand Gate
The outputs of A126 to A128 serve as signals for driving the respective electrodes of the liquid crystal display 50 for dot display.

Further, of the output terminal A _O ~G _O of the BCD down counter 10, the output terminal A _O and the output terminal G _O of the most significant bit of the least significant bit is the one input terminal and the other input terminal of the NAND gate A54 Each is connected. Further, the output terminals A _{O to} G _O of the BCD down counter 10 are connected to the input terminals of a 7-input NAND gate A55 via inverters N41 to N47, respectively. The output terminal of the NAND gate A55 is a D latch circuit D
It is connected to the input terminal D of F1 and the output terminal Q of the D latch circuit DF1 is connected to one input terminal of the NAND gate A52 and one input terminal of the NAND gate A53 via the inverter N48. The other input end of the NAND gate A52 is connected to the output end of the inverter N49, and the other input end of the NAND gate A53 is a switch for detecting whether or not the long film back is attached to the camera (hereinafter,
This switch is called a long detection switch) and is connected to the other ends of S ₁₃ a and S ₁₃ b.

The long detection switches S ₁₃ a and S ₁₃ b are formed of normally closed double switches provided in the motor drive device, and when the long film back is attached to the camera, as shown in FIG. As shown in A), it is designed to open in conjunction with this. One end of one of the long detection switches S ₁₃ a and S ₁₃ b, S ₁₃ a, is grounded via a connection contact J ₁₁ that connects the motor drive device and the long film back to S ₁₃ a. -V is the other end potential through the resistor R _{23 EE2}
Is connected to a power source. Also, the other switch S
One end of ₁₃ b is connected to a connection contact J ₁₂ that connects the motor drive device and the long film back, and the other end of switch S ₁₃ b is connected to the other end of switch S ₁₃ a.
The connecting contact J ₁₂ is connected to a power source that takes a potential −V _EE2 through a resistor R ₂₄ and also the NAND gate A 16
It is connected to the sixth input terminal (see FIG. 1 (A)). In addition, the connection contacts J ₁₁ and J _{12 of} the long film back
A long frame number counter switch S ₁₂ is connected between the switches, and this switch S ₁₂ is a switch that works in conjunction with a mechanical subtraction type film counter provided in the long film back. When the count becomes zero, it is opened as shown in FIG. 4 (B).

Also, the long detection switch S ₁₃ a, the S ₁₃ b and the other end is connected to the other input terminal and the input terminal of the decoder 30 of the NAND gate A57. One input terminal of the NAND gate A57 is connected to the other end of Risetsutosuitsuchi S ₅ through the inverter N53. This reset switch S ₅
Is the BCD of the number of set film frames stored in the D latch row 20.
A normally-open switch for resetting the down counter 10 is designed to be closed only when a reset button (not shown) corresponding to the switch S ₅ is pressed.
One end of this reset switch S ₅ is grounded and the other end is a resistor.
It is connected to a power supply that has a potential of −V _EE2 through R ₂₅ .

The output terminal of the NAND gate A57 is connected to the other input terminal of the NAND gate A58 and the NAND gate A58 via the inverter N54.
26 (see FIG. 1 (A)), respectively. The output end of the NAND gate A58 is connected to the other input end of the NAND gate A59, and one input end of the NAND gate A59 is connected to the output end of the inverter N49. The output terminal of the NAND gate A59 is connected to the set terminal of the BCD down counter 10 via the inverter N55.
Connected to SET. Yotsutte, BCD down counter 10
Is reset by inputting the number of set film frames stored in the D latch row 20 based on the signal input to the set terminal SET through the inverter N55.

The motor drive device is further provided with a set switch S ₄ . The set switch S ₄ is a normally open switch for setting the number of film frames in the D latch row 20, and is closed only when a set button (not shown) corresponding to the switch S ₄ is pressed. It is becoming like this. One end of the set switch S ₄ is grounded, and the other end is connected to a power source which takes a potential −V _EE2 through a resistor R _{22 and} an input end D of a D latch circuit DF 2 for preventing chattering. At the clock signal input terminal CK of the D latch circuit DF2, the frequency f ₂ from the frequency divider circuit 60 (see FIG. 1A) is input.
Pulse signal is applied to the output terminal Q of the same circuit DF2.
Are connected to the input terminal of the inverter N49 and the other input terminal of the NAND gate A56, respectively. Above inverter
The output terminal of N49 is connected to the other input terminal of the NAND gate A52, and is also connected to each reset signal input terminal of the five flip-flop circuits which are cascaded to form a binary counter BC7. A pulse signal of frequency f ₁ is applied from the frequency dividing circuit 60 (see FIG. 1A) to the input terminal of the first stage flip-flop circuit of the binary counter BC7, and the flip-flop circuit of the latter stage of the binary counter BC7 is applied. The output end of the circuit is connected to one input end of a NAND gate A56 via an inverter N51. The output end of the NAND gate A56 is connected to the other input end of the NAND gate A49, and is also connected to the clock signal input end CK of the D latch train 20 via the inverter N52. Therefore, the D latch train 20 is adapted to change the value of the set film frame number to be stored, based on the pulse signal inputted through the inverter N52. That is, FIG. 7 (a)
When the set switch S ₄ is closed as shown in, the frequency f ₁
Frequency f ₁ obtained by dividing the pulse signal (see FIG. 7 (b))
A pulse signal of / 32 is output from the binary counter BC7, and this is passed through the inverter N51, NAND gates A56, A49, A51 and the inverter N38 (Figs. 7 (f), (g), (l),
(See (m) and (n)), and applied to the clock signal input terminal CK of the BCD down counter 10. By the way, the counter 10
Subtraction is performed according to this pulse signal. At the same time,
The pulse signal output from the binary counter BC7 is also applied to the clock signal input terminal CK of the D latch train 20 through the inverter N51, the NAND gate A56, and the inverter N52 (see FIGS. 7 (f) to (h)). . Therefore, the D latch row 20 is
Every time a pulse signal is input, the BCD down counter 10
The content of is transferred and stored, and the number of set film frames is updated. Therefore, the contents of the BCD down counter 10 are the contents of the decoder 3
Since it is displayed on the liquid crystal display 50 via the driver 0 and the driver 40, if the set switch S ₄ is closed when the displayed number of frames reaches a desired value, the number of film frames in the D latch row 20 is changed. Settings are made. At this time, it goes without saying that the content of the BCD down counter 10 has reached the set number of film frames.

When the period from the short Katsuta of the output pulse signal of the closing time of the Setsutosuitsuchi S ₄ are binary counter BC7 Since the BCD down counter 10 not only enter one pulse, the counter 10 is 1 countdown, Setsutosuitsuchi S _{When 4} is closed for a long time, pulse signals are continuously input to the BCD down counter 10, so that the counter 10 is sequentially counted down. BCD down counter 10
When the pulse signal is input again after the content of is zero, the content of count 10 returns to the maximum value that can be input,
The subtraction can be performed again.

Returning to FIG. 1 (A), not only the power supply E ₁ but also the above-mentioned drive motor is used as the power supply device connected to the motor drive device.
A control circuit 13 for M1 (see FIG. 8) is also incorporated. The control circuit 13 is connected to the circuit of the motor drive device through connecting contacts J ₁ , J _{3 to} J ₆ . Of these connecting contacts, the connecting contact J ₅ is connected to the base of the NPN transistor T ₂₂ through the resistor R ₃₁ and the transistor T ₂₂
The emitter of is connected to connection contact J ₆ . The collector of the transistor T ₂₂ is connected to the emitter of the NPN transistor T ₂₁ , and the base of the transistor T ₂₁ is connected to the connection contact J ₄ via the resistor R ₃₂ . The collector of the transistor T ₂₁ is connected via a resistor R _33.
It is connected to J ₃ as well as to one end of capacitor C ₁₁ . The other end of the capacitor C ₁₁ is connected to the connection contact J ₅ through a resistor R ₃₄ and also the diode D ₁₂
Is connected in the forward direction to the base of the NPN transistor T ₂₄ and the resistor R _{37 to} the cathode of the diode D ₁₁ . The anode of diode D ₁₁ is for continuous shooting
It is connected to a connection contact J ₆ via a switch (hereinafter, this switch is referred to as a continuous single switching switch) S ₉ for switching one frame shooting. When the continuous single switching switch S ₉ is opened, the continuous shooting mode is obtained, and when it is closed, the single frame shooting mode is obtained.

The emitter of the transistor T ₂₄ is connected to the connection contact J ₆ and also to the emitter of the NPN transistor T ₂₅ . The collector of the transistor T ₂₄ is connected to the emitter of the NPN transistor T ₂₃ , and the base of the transistor T ₂₃ is connected to the connection contact J ₄ via the resistor R ₃₅ . The collector of the transistor T ₂₃ is connected to the connection contact J ₅ through the resistor R _{36 and} the base of the transistor T ₂₅ . The collector of the transistor T ₂₅ is connected to the connecting contact J ₅ via the relay Y ₁ and the diode D ₁₃ in parallel. The relay Y ₁ is interlocked with the switching switch S ₁₁ , and when the relay Y ₁ is not energized, the switching switch S ₁₁ causes the movable contact piece to contact the braking terminal j.
When the relay Y ₁ is energized, the changeover switch S
_{The 11} movable contacts are switched to the power supply connection terminal i.

Furthermore, the connection contacts J ₅ is connected to one end of the normally-open of the operation switch S _8, the other end of the operation switch S ₈ is connected contact J _3, the power supply E ₁ positive and switching switch S ₁₁ Braking terminal j
Respectively connected to. The negative electrode of the power supply E ₁ is connected via the power switch S ₁₀ to the connection contact J ₆ and the switching switch S ₁₁
Of the power supply connection terminals i. The movable contact terminal of the switching switch S ₁₁ is connected to the connection contact J ₁ . The connection contacts J ₃ is grounded in the motor drive device, when closed accordance connexion, a power switch S ₁₀ is connected contact J ₆ are potential by electromotive voltage of the power source E ₁ -
It is taking _VEE1 .

FIG. 8 shows a power supply circuit system in the motor drive device. The power supply E ₁ is a large-capacity power supply for driving a motor arranged in the power supply device, and the power supply E ₂ is a small-capacity power supply for a motor control / display circuit provided in the motor drive device. The positive electrode of the power supply E ₂ is grounded and the negative electrode is connected to the emitter of the NPN transistor T ₃₁ . The base of the transistor T ₃₁ is grounded through the resistor R ₄₁ , and is connected to the anode of the zener diode ZD ₁ through the diode D ₂₁ in the forward direction. The collector of the transistor T ₃₁ is grounded via the capacitor C ₂₁ and is also connected to the emitter of the PNP transistor T ₃₂ . The emitter of the transistor T ₃₂ is also connected to the other end of the motor control / display circuit 11, and one end of the motor control / display circuit 11 is grounded. The base of the transistor T ₃₂ is connected to the emitter of the PNP type transistor T ₃₃ , the collector is connected to the collector of the transistor T ₃₃ through the resistor R ₄₂ , and the connecting contact J ₆
It is connected to the. The base of the transistor T ₃₃ is
It is connected to the anode of the Zener diode ZD _{1 and also to} the connection contact J ₆ through a resistor R ₄₃ .
The Zener diode ZD ₁ is the motor control / display circuit 1
It serves to generate a constant voltage to be supplied to 1, the cathode of which is grounded. Motor control above
The output end of the display circuit 11 is connected to the input end of the motor drive circuit 12, one end of the motor drive circuit 12 is grounded, and the other end is connected to the connection contact J ₆ . Further, both ends of the drive motor M1 are connected to the motor drive circuit 12.

On the other hand, one end of the motor control circuit 13 provided in the power supply device is grounded to the motor drive device through the connection contact J ₃ , and the other end is connected to the connection contact J ₆ and the power switch S It is connected via ₁₀ to the negative pole of the power supply E ₁ . The positive electrode of the electrode E ₁ is grounded through the connection contact J ₃ . The motor control circuit 13 is connected to the motor control circuit 11 through a connection contact.

In the power supply circuit system of such a motor drive device,
When the power switch S ₁₀ is closed, power is supplied from the power source E ₁ to the motor control circuit 13 and the motor drive circuit 12 at the voltage V _EE1 , and a constant voltage circuit composed of the transistors T ₃₂ , T ₃₃ and the zener diode ZD ₁ is opened. _Power is supplied to the motor control / display circuit 11 via the voltage V _EE2 via the motor control / display circuit 11. Since the power switch S ₁₀ is on, the transistor T ₃₁ is off and the power of the power source E ₂ is not consumed. Further, when the power switch S ₁₀ is off, power is not supplied to the motor control circuit 13 and the motor drive circuit 12, but since the base potential of the transistor T ₃₁ becomes the'H 'level,
The transistor T ₃₁ turns on, and the motor control / display circuit 11
The power is supplied from the power source E ₂ only to.

As described above, the motor drive device of this embodiment is configured.

Next, the operation of this motor drive device will be described.

First, in the initial state, as long as the power source battery (power source E ₁ ) is loaded in the motor drive device, power is being supplied to the motor control / display circuit 11 (see FIG. 8). Each circuit element has an output state as shown in (a) to (z) and (α) of FIGS. 9A and 9B, for example. That is, in this initial state, since the release switch S ₁ is opened, the NAND gate A 6
Output is at'H 'level (Fig. 9 (A) (a)
Since the movable reflecting mirror is in the lowered position, the output of the inverter N3 is at the'H 'level. Further, since the release terminal b of the motor switch S ₆ is switched to the alligator, the output of the NAND gate A14 is at the'L 'level. Further, if at least one output of the BCD down counter 10 is at the'H 'level, the NAND gate A55
The output of the D latch circuit DF1 is at the "H" level.

The inverter N3, which is the input to the NAND gate A15
Output is'H 'level, output of NAND gate A9 is'L' level, output of NAND gate A8 is'L 'level, inverter N1
Since the output of 5 is'H 'level and the output of the inverter N29 is'H' level, the output of the NAND gate A15 is'H 'level (see FIG. 9 (B) (y)). The output of the inverter N3, which is the input of the NAND gate A16, is the “H” level, the output of the NAND gate A11 is the “L” level, the output of the NAND gate A14 is the “L” level, the output of the inverter N29 is the “H” level, the output of the NAND gate A53. Since the output is'H 'level and the potential of the connecting contact J ₁₂ is'H' level, the output of the NAND gate A16 is'H 'level (Fig. 9 (B)).
(See (j)). Therefore, the output of NAND gate A17 is'L '.
Level (see FIG. 9 (B) (α)), the inverter
The output of N32 is at'H 'level, and the transistor T ₃
~ T ₆ is off and motor M1 is not rotating. Incidentally, in the case of mounting the camera compatible models to the motor drive remains type detection switch S ₁₅ is on (FIG. 9 (A) (e) refer), if equipped with a camera incompatible model the type detection switch S ₁₅ is turned off. Hereinafter, unless otherwise specified, it is assumed that a compatible camera model is installed.

When the rear lid of the camera is opened to load the film from such an initial state, the rear lid switch S ₃ and the rear lid lock switch S ₁₄ are turned on (see FIGS. 9 (A), (c) and (d)). The reset signal of'H 'level is applied to each reset signal input terminal of each flip-flop circuit forming the binary counter BC3. Therefore, the output of each flip-flop circuit is at the'L 'level (see FIG. 9 (A) (g)), and the output of the NAND gate A26 is at the'L' level (see FIG. 9 (A) (i)). The output of A27 becomes the'H 'level (see FIG. 9 (A) (j)). Also, the output of the inverter N24 becomes "H" level (Fig. 9 (A)).
(O)), the reset signal of'H 'level is applied to the reset signal end of each flip-flop circuit forming the binary counter BC4, and the binary counter BC4 is reset.

After loading the film into the camera and closing the rear lid, the rear lid switch S ₃ is opened (see FIGS. 9 (A) and (c)).
Together, this rear lid lock switch S ₁₄ slight delay is opened (Figure 9 (A) (d) refer). Then the inverter
The output of N24 returns to the'L 'level (see FIG. 9 (A) (o)), and the binary counter BC4 starts counting the pulse signal of frequency f ₄ . Then, when a predetermined time elapses and the output of the binary counter BC4 is inverted to the “H” level, the inputs of the NAND gate A39 are both set to the “H” level.
Output becomes'L 'level (see FIG. 9 (B) (u)). Therefore, the output of the NAND gate A41 becomes'H 'level (see FIG. 9 (B) (v)), the output of the inverter N28 becomes'L' level (see FIG. 9 (B) (w)), and the NAND gate A29 becomes Are reset (see FIG. 9 (A) (l)). Then, the output of the NAND gate A28 is'L 'level (see FIGS. 9 (A) (k)), the output of the inverter N23 is'H' level (see FIGS. 9 (A) (m)), and the NAND gate is
Since the output of A35 is also at the'H 'level (see FIG. 9 (B) (q)), the output of the NAND gate A42 is at the'L' level (see
(See FIGS. (B) and (x)). The output of the NAND gate A42 is input to the NAND gate A15 via the NAND gates A9 and A8, and the output of the gate A15 becomes the'L 'level (see FIG. 9 (B) (y)). Yottte, Nand Gate A17
Output 'H' level (Figure 9 (B) (alpha) refer), the output of the inverter N32 becomes 'L' level, the transistor T ₃ through T ₆ is turned on, current is conducted to the driving motor M1 Is
The motor M1 starts the rotation for film idling.
After the output of the NAND gate A36 is inverted, the binary counter BC5
Counts the pulse signal of frequency f ₅ and when a predetermined time elapses, the output of the counter BC 5 is inverted and the NAND gate A
39 output is'H 'level, NAND gate A41 output is'L'
Since the level (see FIGS. 9B, (u), and (v)) is reached, the initial state is restored.

Drive motor M1 is rotated, the release is performed, the movable reflecting mirror is increased, Kamerasuitsuchi S ₂ is up-pin up
Since it is switched to a ring, the output of the inverter N3 is inverted to the'L 'level. Therefore, the outputs of the NAND gates A15 and A16 are both at the'H 'level (Fig. 9 (B) (y),
(See (z)), and the output of the NAND gate A17 becomes the'L 'level (see FIG. 7 (B) (α)). Therefore, the inverter
The output of the N32 becomes 'H' level, the transistor T ₃ is turned off, the transistor T _4, T ₅ and T ₆ is turned off, respectively, energization of the motor M1 is cut off. At the same time, the brake circuit is activated by the'L 'level output of the NAND gate A17, and the output of the inverter N37 is'L' for a certain period of time.
Since it becomes the level, the transistors T ₁₁ and T ₉ are turned on, both ends of the motor M1 are short-circuited, and the motor M1 is braked. Therefore, the motor M1 suddenly stops. Further, almost at the same time as when the movable reflecting mirror is raised, the motor switch S ₆ switches the hoisting terminal a to a ring.

When the movable reflecting mirror is raised and the shutter is actuated to complete the exposure, the movable reflecting mirror is moved back and forth this time, and the camera switch S ₂ is switched to the down terminal dw. At this time, the motor switch S ₆ has already switched the hoisting terminal a, so that the output of the NAND gate A14 becomes'H 'level, the output of the inverter N3 becomes'H' level, and the output of the NAND gate A16 becomes'H 'level. It becomes L'level (Fig. 9 (B))
(See (z)). Therefore, the output of NAND gate A17 is'H '.
The level (see FIG. 9 (B) (α)) and the output of the inverter N32 become the “L” level, so that the transistors T _{3 to} T ₆ are turned on, the motor M1 starts rotating again, and the film winding. Do the top.

By the way, the output of the NAND gate A19 is'L 'level in the initial state, but when the movable reflecting mirror rises, the output of the inverter N2 becomes'L' level.
The output of A19 becomes'H 'level. When the movable reflecting mirror descends, the output of the inverter N2 becomes the "H" level, and the output of the binary counter BC2 becomes the "H" level after a slight delay of the chattering time. Therefore, the output of the NAND gate A19 becomes'L 'level. Therefore, one pulse is input to the input terminal of the binary counter BC3 every time the movable reflecting mirror moves up and down once.

At the stage when the first film winding is completed, the output of the NAND gate A28 remains at the “L” level (see FIGS. 9A and 9K), so the outputs of the NAND gates A8 and A9 are “H”. Since the movable reflecting mirror is descending, the output of the inverter N3 is at the'H 'level. Also,
Since Motasuitsuchi S ₆ is One drop-in replacement for the release terminal b Gawani cutting, the output of the inverter N15 is 'H' level.
Therefore, the output of the NAND gate A15 is at the'L 'level (see FIG. 9 (B) (y)), and the output of the NAND gate A17 is at the'H' level (see FIG. 9 (B) (α)).
When the output of N32 becomes the “L” level, the motor M1 continues to rotate, and subsequently, similarly to the case of the first time, the second release and film winding are performed.

When the camera switch S ₂ switches the up terminal up again with the _second rise of the mirror, the output of the binary counter BC3 becomes'H 'level (see FIGS. 9 (A) and (g)). Therefore, the output of NAND gate A27 is L level, NAND gate A27
The output of 28 becomes'H 'level (Fig. 9 (A) (j),
(See (k)). By this output of the NAND gate A28 is 'H' level, the output of NAND gate A9 is a signal from the subsequent release Sui Tutsi S _1, i.e., a state which is determined by the output of the inverter N7. Also, Nand Gate A8
Output is at'L 'level, so NAND gate A1
The output of 5 becomes the'H 'level (see FIG. 9 (B) (y)). Therefore, when the second film winding is completed,
Regardless of whether the release switch S ₁ is opened or closed, the film feed automatically stops.

The above description of the idling operation is the operation when the compatible model camera is attached to the motor drive device.
If you install a camera incompatible models, type detection switch S ₁₅ is turned off, the output of NAND gate A34 is 'H' level, the output of the inverter N24 becomes 'L' level,
The circuit including the binary counters BC4 and BC5 does not work, and the outputs of the NAND gates A35 and A39 remain at the "H" level. Therefore, the output of NAND gate A26 and A28 is always 'H' level, Do maintains its output is 'H' level of the NAND gate A42 connexion, back cover switch S ₃ by opening and closing the rear cover, the rear lid lock switch S ₁₄ Even if it is opened / closed, the reset of the binary counter BC3 is performed, but the output of the NAND gate A42 is in the same state as at the end of the idling. Therefore, in order to feed the film in this state, it is necessary to press the release button to close the release switch S ₄ .
When the release switch S ₄ is closed, the film is fed in the same manner as in the case where the film is fed by the rear lid closing signal.

By the way, when a film of a compatible model is mounted and the film is fed in blank, the liquid crystal display 50 (see FIG. 6) displays a dot display. That is, by opening the rear lid switch S ₃ and the rear lid lock switch S ₁₄ , the output of the NAND gate A26 (see FIGS. 10 (A) and (g)) is'L 'until the second frame is fed.
And the output of each flip-flop circuit that forms a binary counter BC3 with this output (Fig. 10 (A) (c),
(See (d)) and the logical operation in the decoder 30
Until the first frame is completed, dots 2 and 3 are displayed as shown in FIG. 16 (B).
(See FIGS. 10 (A), (n) and (o)) Only the dot 3 is displayed as shown in FIG. 16 (C) until the second frame is fed. (A) and (o)), when the blank feeding is completed, as shown in FIG. 16 (D), all the dots will disappear. If a non-conforming camera is attached, the output of the NAND gate A26 will remain at the'H 'level (see Fig. 10 (B) (g)).
The output of the inverter N129 is'L 'level (Fig. 10 (B))
(See (k)) and the outputs of the NAND gates A124 and A125 are at the'H 'level (see (B) (l) and (m) in FIG. 10).
The potential of the output and connection contact J ₁₂ of the NAND gate A54 is 'H'
Under the condition of being a level, NAND gates A126 to A1
All 28 outputs are at'L 'level (Fig. 10 (B) (n),
(See (o) and (p)), and the dot display is not performed as shown in FIG. 16 (D).

Next, the operation of the motor drive device in the case of single frame photography will be described. One-frame shooting mode, or switches the communication single switching switch S ₇ of the motor drive device I to the one frame of imaging terminal b side, or continuous single switching switch of the power supply S ₉
Obtained when you close the. Here, the case where the continuous single switching switch S ₇ is switched to the terminal b will be described as an example.

In order to shoot a single frame, if the release button is pressed and the release switch S ₁ is closed from the state where the film has been skipped, the outputs of the NAND gates A6 and A7 will be the same as in the case of the jump feed described above. The output of the NAND gate A15 becomes L level (see FIGS. 11 (a) and (b)) and the outputs of the NAND gates A8 and A9 become'H 'level (see FIGS. 11 (h) and (c)). Becomes the'L 'level (11th
(See FIG. (K)). Therefore, the output of the NAND gate A17 becomes the “H” level and the output of the inverter N32 becomes the “L” level (see FIGS. 11 (l) and (m)), and the motor M1 rotates for the shutter release. Start. When the motor M1 rotates, increases the movable reflecting mirror, Kamerasuitsuchi S ₂ is up-switched terminal up Gawani cutting. Then, the output of the inverter N3 goes to the'L 'level (see FIG. 11 (g)), and the output of the NAND gate A15 returns to the'H' level (see FIG. 11 (k)). Therefore, the output of NAND gate A17 is'L 'level,
When the output of the inverter N32 becomes “H” level (see (l) and (m) in FIG. 11), the power supply to the motor M1 is cut off and the brake circuit operates for a certain period of time to rotate the motor M1. Is stopped. Also, substantially simultaneously with rise of the movable reflecting mirror, Motasuitsuchi S ₆ is switched to the winding terminal a, (see FIG. 11 (d)) output of NAND gate A14 is to be 'H' level.

When the shutter is activated and the exposure is finished after the movable reflecting mirror is raised, the camera switch S ₂ is switched to the down terminal dw as the movable reflecting mirror is moved back and down. As a result, the output of the inverter N3 is inverted to the'H 'level (first
(See Fig. 11 (g)). Also, since the output of NAND gate A14 is at the'H 'level, NAND gate A11
Output remains at'H 'level (see FIG. 11 (e)). Therefore, the output of the NAND gate A16 becomes'L 'level (see FIG. 11 (j)). The output of the NAND gate A17 becomes "H" level and the output of the inverter N32 becomes "L" level (see (11) and (m) in FIG. 11), and the motor M1 starts to rotate because the film is wound up this time. To do.

When the winding of the film for one frame which has been photographed is completed, the motor switch S ₆ switches the release terminal b to the ring so that the output of the NAND gate A14 becomes the “L” level (see FIG. 11 (d)). The output of the NAND gate A16 returns to the'H 'level (see FIG. 11 (j)). Yottte, Nand Gate A17
Output is at'L 'level and the output of the inverter N32 is at'H' level (see (11) and (m) in FIG. 11), the power supply to the motor M1 is cut off and the brake circuit is operated for a certain time. The motor M1 is actuated and the rotation of the motor M1 is stopped. At the time when the winding of this film is completed, even if the release switch
Even if S ₁ continues to be closed, the output of NAND gate A 6 is returning to the'H 'level, so the input terminals of NAND gate A 8 are all at the'H' level.
Because the output of A8 is'L 'level, NAND gate A1
The output of 5 always becomes'H 'level. Therefore, there is no possibility that the release operation will be performed again following the winding of the film, and when the photographing of one frame and the winding of the film are performed, the motor drive device surely stops the operation.

In addition, the content of the BCD down counter 10 is decremented by one in association with the above-described one frame shooting. That is, the output of the inverter N2 changes as shown in FIG.
Since the outputs of the binary counter BC2, the inverter N16, and the NAND gate A18 change as shown in FIGS. 12B to 12E, one pulse is output to the output end of the NAND gate A19 (the twelfth pulse).
(See Figure (h)). The output of the NAND gate A56 is H unless closed the Setsutosuitsuchi S ₄ (Fig. 12 (l)
Therefore, the pulse output of the NAND gate A19 is supplied to the BCD through the NAND gates A48, A49, A51 and the inverter N38 (see FIGS. 12 (p), (q), (r)) unless the counter 10 is in the no-count mode. Down counter 10
It is input to the clock signal input terminal CK of. Therefore, the BCD down counter 10 is decremented by one in accordance with one up-down of the movable reflecting mirror. When the content of the counter 10 becomes zero, the output of the D latch circuit DF1 becomes L.
Since the level becomes the level and the pulse signal is not applied to the clock signal input terminal CK of the counter 10 through the inverter N48 and the NAND gates A52 and A51, the counter 10 stops further subtraction.

Next, the operation of the motor drive device in the case of continuous shooting will be described. In the case of this continuous shooting, the continuous single switching switch S ₇ is switched to the continuous shooting terminal a. In addition, the power supply unit also needs to be in the open state for selecting the continuous shooting mode for the continuous single switching switch S ₉ .

When switching the communication single switching switch S ₇ the continuous shooting terminal a side, the potential of the other end of the same switch S ₇ is made to change according to the switching of the power supply of the I switching switch S ₁₁ . That is, the switching switch S ₁₁ is at the “H” level when the braking terminal j is switched to the alligator side, and is at the “L” level when the power supply connection terminal i is switched to the alligator.

The release of the first frame and the film winding are performed in the same manner as in the case of the one-frame shooting described above, but when the film winding is completed, the continuous single switching switch S ₉ of the power supply device is opened. As a result, the switching switch S ₁₁ has the power supply connection terminal i trapped, and therefore the second input terminal of the NAND gate A8 remains at the'L 'level. Yotsutte
As shown in FIG. 13 (h), the output of the NAND gate A8 is at the “H” level, the output of the NAND gate A15 is at the “L” level, the output of the NAND gate A17 is at the “H” level, and the output of the inverter N32 is at the “H” level. At the'H 'level (see FIGS. 13 (k), (l), and (m)), the motor M1 continues to rotate and the second frame is released following the film winding of the first frame. Be done. Then, after the release, the film of the second frame is wound as in the case of the first frame.

If the release switch S ₁ is opened after the second frame is released, as shown in FIG. 13, the transistor T ₂₂ is turned off and the relay Y ₁ is deenergized in the power supply device, so that the switching switch S ₁ is turned off. ₁₁ , the braking terminal j is switched to the alligator. Therefore, since the second input terminal of the NAND gate A8 becomes'H 'level, the output of the gate A8 is inverted to'L' level (see FIG. 13 (h)). Therefore, when the film winding of the second frame is completed and the motor switch S ₆ is switched to the release terminal b, the motor drive device is stopped and the continuous shooting is completed.

It is needless to say that a pulse signal is input to the BCD down counter 10 and the content of the counter 10 is decremented by 1 every time the movable reflecting mirror is up-down even during the continuous shooting.

Then, when the contents of the BCD down counter 10 become zero during continuous shooting, all the output terminals A _{O to} G _{O of} the counter 10 become'L 'level, so the output of the NAND gate A55 becomes'L' level. Becomes 'L' level output of the NAND gate A55 is a D latch DF1 is read in synchronism with the vertical movement of the closing or movable reflecting mirror release Sui Tutsi S _1, and is outputted from the output Q of the circuit DF1. In other words, when the shooting of the preset number of film pieces is completed,
The output of the D latch circuit DF1 is inverted to the'L 'level. When the output of the D latch circuit DF1 becomes'L 'level, the inverter N
48, 4th of Nandgate A16 through Nandgate A53
Since the input terminal of is at the'L 'level, the output of the gate A16 is always at the'H' level, the output of the NAND gate A17 is at the'L 'level, and the output of the inverter N32 is at the'H' level. The rotation of the motor M1 for hoisting is automatically stopped. Also, since the output of NAND gate A52 becomes'L 'level and the output of NAND gate A51 becomes'H' level, the BCD down counter 10 will continue to count even if you manually wind the film and release the shutter. No action is taken.

When the number of remaining frames, which is the count content of the BCD down counter 10, becomes zero, in the decoder 30 (see FIGS. 5A and 5B), the outputs of the inverters N116 and N134 both become "H" level. Therefore, the output of the NAND gate A130 becomes the “L” level, and the output of the NAND gate A101 becomes the “H” level. If the camera is adapted models is mounted remain type detection switch S ₁₅ is on, NAND gate A
Since the signal input to 102 is at the "H" level, the output of the NAND gate A104 becomes the "H" level, and the pictogram of the camera rewinding member set is displayed on the liquid crystal display 50 (see FIG. 6). Next, when the R clutch, which is the camera rewind member, is set, the R clutch switch S ₁₇ is turned on, the output of the inverter N106 becomes the "H" level, and the pictogram of the motor drive device rewind member set is displayed. Be done. If the R lever, which is the motor drive device rewinding member, is set before the R clutch is set,
Output of NAND gate A103 is'L 'level, NAND gate A1
The output of 04 becomes "H" level, and the pictograms on the camera rewinding member set are displayed first. When both the R clutch and the R lever members are set, the film is rewound, as will be described later, and the fact is displayed on the liquid crystal display 50 based on the output of the inverter N107 by pictograms. . Also, if a camera that is mounted is incompatible model, since the model detection switch S ₁₅ is opened, the rear lid lock switch S _14, R Rebasuitsuchi S _16, switching signal such R Kuratsuchisuitsuchi S ₁₇ motor The drive device is not transmitted to the alligator, the output of the inverter N111 becomes the "H" level, and the reset button is pressed.

Further, although the content of the BCD down counter 10 does not become zero during continuous shooting, the film winding is automatically stopped even when the film reaches the end. That is, when the exposure for the last one frame is completed, the movable reflecting mirror descends and the motor M1 rotates to try to wind up the film. However, since the film has reached the end portion, one frame cannot be wound up, and the motor switch S ₆ switches the release terminal b to the ring while the release mechanism is not charged (see FIG. 14 (n)). . Then, the output of the NAND gate A14 becomes'L 'level (see FIG. 14 (g)), and the output of the NAND gate A11 becomes'L' level (first).
See Fig. 4 (f). On the other hand, since the switching switch S ₁₁ of the power supply device is switched to the power supply connection terminal i, the output of the NAND gate A8 is at the'H 'level (see FIG. 14 (j)), and the NAND gate A15. , A17, and the inverter N32 allow the motor M1 to continue rotating for the next release (see FIGS. 14 (p) and (q)). However, since the release mechanism is not Chiyaji, rise of the movable reflecting mirror is not performed, the motor M1 is stopped when the Motasuitsuchi S ₆ is One automatically turn the winding terminals a, thereafter the NAND gate A11 'L' The level output prevents the rotation of the motor M1 from restarting.

When the content of the BCD down counter 10 becomes zero as described above, in order to restore the content of the counter 10 to the set film frame number stored in the D latch row 20, the reset switch is used.
The S ₅ may be closed. Thus, the'L 'level signal is applied to one input terminal of the NAND gate A57 through the inverter N53, and is applied to the set signal input terminal of the BCD down counter 10 through the NAND gate A57, the inverter N54, the NAND gates A58, A59, and the inverter N55. Since the H'level signal is applied, the number of set film frames stored in the D latch row 20 is input to the BCD down counter 10 and set. It should be noted that, at the time of closing of this Risetsutosuitsuchi S _5, an inverter N5
The output of 4 is input to the NAND gate A26, and the output of the gate A26 is forcibly set to the'H 'level so that the film is not fed in advance due to the reset of the number of film frames.

Further, the number of film frames is automatically returned by closing the rear lid switch S ₃ . That is, when opening the lid after the camera for the exchange of the film, the rear cover switch S ₃ is closed, but when closing the switch S _3, since binary counter BC3 is reset, the output of the inverter N21 is' H It becomes'level 'and the output of NAND gate A26 becomes'L' level. Therefore, the output of the NAND gate A58 becomes the "H" level, and the "H" level signal is applied to the set signal input terminal SET of the BCD down counter 10 through the NAND gate A59 and the inverter N55. Therefore, the BCD down counter 10 is
The set film frame number stored in the latch row 20 is set.

On the other hand, when the release switch S ₁ is closed with the rear lid open, the output of the NAND gate A34 is at the “L” level (see FIG. 15 (e)), so the output of the NAND gate A28 is “H”. It remains at the level (see Fig. 15 (g)). Therefore, in the one-frame shooting mode, after the one-frame shooting, all the inputs of the NAND gate A8 become'H 'level, and the output of the gate A8 becomes'L' level (Fig. 15 (h )) Release of the second frame is not performed. Further, in the case of a continuous shooting mode, during which closes the release Sui Tutsi S _1, continuously on the release and film take is performed and to open the release Sui Tutsi S _1, switching power supplies I switch Since the control terminal j is switched to S ₁₁ and the second input terminal of the NAND gate A 8 becomes the “H” level, the subsequent shooting operation is not performed as in the case of the single frame shooting mode.

By the way, the BCD down counter 10 shown in FIG. 1 (B) is a 42-ary counter, and when the content of the counter 10 is "0" to "40", it represents the number of frames of the film, When the content of the counter 10 is "41", the no-count mode is set. That is, when the content of the BCD down counter 10 reaches "41", the output terminals A _O and G _O output "H" level output, and the output of the NAND gate A54 outputs "L".
Since the output of the NAND gate A129 of the level and the decoder 30 (see FIGS. 5A and 5B) becomes the “H” level and the output of the inverter N130 becomes the “L” level, the NAND gates A114 to A123.
And the outputs of A131 to A135 are all at the “H” level, and the outputs of the inverters N116 to N125 and N134 to N138 are all at the “L” level, and the number of frames is not displayed on the liquid crystal display 50. Also, since the'L 'level output of the NAND gate A54 is applied to the other input terminal of the NAND gate A48, the BCD
The count pulse is no longer input to the down counter 10. Further, since the outputs of the NAND gates A126 to A128 are all at the "H" level, dot 1, dot 2 and dot 3 are displayed as shown in FIG. 16 (A).

Further, even when the long film back is attached to the camera, the motor drive device is in the no count mode.
That is, when the long film back is attached to the camera, as described above, unless the content of the mechanical subtraction type film counter built in the long film back is zero, the long film back as shown in FIG. Since the frame number counter switch S ₁₂ is closed, the potential of the connecting contact J ₁₂ becomes the “H” level. Further, the electric potentials at the other ends of the long detection switches S ₁₃ a and S ₁₃ b become the “L” level. Therefore, the output of NAND gate A57 becomes'H 'level, and inverter N54, NAND gate A58,
A signal of'H 'level is input to the set signal input terminal SET of the BCD down counter 10 via A59 and the inverter N55, and the counter 10 is in a set state in which the stored value of the D latch sequence 20 is output. Therefore, the counter 10 does not perform subtraction even if shooting is performed. Also, the potential at the'L 'level at the other ends of the long detection switches S ₁₃ a and S ₁₃ b is the NAND gate of the decoder 30.
Since it is applied to one input terminal of A129 and the output of NAND gate A129 is always at the'H 'level, the liquid crystal display is the same as when the content of BCD down counter 10 becomes 41.
At 50, the number of pieces is not displayed. Therefore, when the long film back is mounted on the camera, the motor drive device enters the no count mode. Further, if the other input end of the NAND gate A53 becomes the "L" level and the number of set film frames of the D latch row 20 is other than zero, the output end Q of the D latch circuit DF1 also becomes the "H" level. The output of A53 becomes'H 'level. Therefore, the potential of the connection contact J ₁₂ and the output of the NAND gate A53, which are input to the NAND gate A16, are both at the “H” level, so that the film can be wound. Also, when a long film back is attached to the motor drive device,
Since the potentials at the other ends of S ₁₃ a and S ₁₃ b are at the “L” level, the outputs of the NAND gates A126 to A128 are all at the “H” level, and dot 1, dot 2 and dot 3 are displayed ( See FIG. 16 (A).

Then, when the content of the mechanical subtraction type film counter built into the long film back becomes zero, the switch S ₁₂
Is released and the potential of the connection contact J ₁₂ is inverted to the'L 'level, so that the output of the NAND gate A16 is always at the'H' level, and subsequent film winding is impossible.

Also, when the motor drive device of the present embodiment is equipped with a camera that cannot be used by mounting the motor drive device, the motor drive device does not perform the release operation or the film winding operation. That is, as shown in FIG. 17, a camera of an unusable model has a diode between the down terminal dw of the camera switch S ₂ and a connection contact (not shown).
Even if D ₂₁ is connected in the forward direction and the down terminal dw of the camera switch S ₂ is switched, the input terminal of the inverter N1 is always at the'H 'level.
The output of A2 becomes'H 'level, the output of the inverter N3 becomes'L' level, and the outputs of the NAND gates A15 and A16 always become'H 'level. Therefore, the motor drive device does not perform the release operation or the film winding operation. The camera can be used to manually release and wind the film.

When both the R clutch and the R lever are set together, the R clutch switch S ₁₇ and the R lever switch S ₁₆ are turned on respectively, so that the output of the inverter N29 becomes the "L" level and the output of the NAND gate A15 becomes the "H" level. As a result, film winding becomes impossible. Further, if the film in the camera is loaded, since the film Sui Tutsi S ₁₈ is open, the output of NAND gate A43 becomes 'L' level, the transistor T ₈ through an inverter N35, N36, T ₇
Is turned on, and the transistors T ₁₁ and T ₉ are turned on through the NAND gate A47 and the inverter N37. Yotsute, the drive motor M1 current flows through the transistor T ₇ and T _9,
The motor M1 rotates in the direction opposite to that at the time of film winding. Therefore, the film is rewound. Further, during the film rewinding, the inverter N107 of the decoder 30 outputs an'H 'level output, and the liquid crystal display 50 displays the pictograms during the film rewinding.

When the film of the rewind is completed, the film Sui Tutsi S ₁₈ is turned on, the output of the inverter N31 becomes 'L' level, the output of NAND gate A43 is 'H' level, the transistor T _8, T ₇ and T ₁₁ and T ₉ are turned off. Therefore, the power supply to the drive motor M1 is cut off,
The rewinding of the film is automatically completed by stopping M1. Further, since the output of the inverter N107 of the decoder 30 is inverted to the'L 'level, the display on the liquid crystal display 50 during film rewinding is erased.

As described above, the film feeding apparatus of the present invention drives a plurality of display elements indicating the film idling state at the start of idling, and gradually reduces the number of driving during idling and at the end of idling. Since I tried to stop all driving,
It is possible to electrically inform the user that the film is being fed in the air and give the user a sense of security.

[Brief description of drawings]

1 (A) and 1 (B) are electric circuit diagrams of a motor drive device showing an embodiment of the present invention, and FIGS. 2 (a) to (j) and FIGS. 3 (a) to (j) are ,
The time charts showing the output states of the respective parts of the shutter release signal holding circuit provided in the motor drive device shown in FIGS. 1 (A) and 1 (B) are shown in FIGS. 4 (A) and 4 (B). Figure 1 (A),
FIG. 5 (A) and FIG. 5 (B) are electric circuit diagrams of the main parts showing the opened / closed state of the switch when the long film back is attached to the motor drive device shown in FIG. FIG. 6 is an electric circuit diagram showing a more detailed structure of the decoder shown in FIG. 6A, FIG. 6 is a front view showing an electrode structure of the liquid crystal display shown in FIG. 1B, and FIG. ˜ (n) are time charts showing the output states at the time of setting the number of frames in the motor drive device shown in FIGS. 1 (A) and 1 (B), and FIG. 8 is shown in FIG. 1 (A), An electric circuit diagram showing a power supply circuit system in the motor drive device shown in (B), Fig. 9 (A) (a) to (o) and Fig. 9 (B) (p).
(Z) and (α) are time charts showing the output states of the motor drive device shown in FIGS. 1 (A) and 1 (B) when the film is fed by the rear lid closing signal, respectively, and FIG. (A) (a)-(p) and FIG. 10 (B) (a)
Outputs for dot display when a compatible model camera and an incompatible model are mounted on the motor drive device shown in FIGS. 1A and 1B. 11 (a) to 11 (n) are time charts showing the respective states, and FIGS. 11 (a) to 11 (n) are time charts showing the output states at the time of single frame photography in the motor drive device shown in FIGS. FIGS. 12 (a) to 12 (r) are time charts respectively showing output states when the counter is subtracted in the motor drive device shown in FIGS. 1 (A) and 1 (B), and FIGS. (O) is a time chart showing the output states during continuous shooting in the motor drive device shown in FIGS. 1 (A) and 1 (B), and FIGS. 14 (a) to 14 (q) are the first charts. Motor drive shown in Figures (A) and (B) 15 (a) to 15 (h) are time charts showing output states at the time of automatic stop due to the end of the film, respectively, in the motor drive device shown in FIGS. 1 (A) and 1 (B). 16A to 16D are time charts showing the output state at the time of idling with the lid open, and FIGS. 16A to 16D show the modes of dot display or dot non-display on the liquid crystal display shown in FIG. 6, respectively. FIG. 17 is a front view of a main part shown in FIG. 17, and FIG. 17 is an electric circuit diagram of a main part showing a case where a camera of an unusable model is attached to the motor drive device shown in FIGS. 1 (A) and 1 (B). 10 ...... BCD down counter 20 ...... D latch array 30 ...... decoder 40 ...... driver 50 ...... liquid crystal display (display means) M1 ...... drive motor (air feed means) S ₁ ...... release Sui Tutsi (empty feed command Means) S ₃ …… Rear lid switch (idle feed command means) S ₁₄ …… Rear lid lock switch S ₁₅ …… Model discrimination switch

Claims (1)

[Claims] 1. A command means for outputting an idle feed start signal for instructing the start of idle feed of the film, and an idle feed execution means for idling the film to a photographable state based on the idle feed start signal. , Formed so as to represent the feeding state when the film is idly fed,
During the idling of the film by the display means composed of a plurality of liquid crystal display elements and the idling execution means, the display amount of the plurality of liquid crystal display elements is changed in accordance with the idling amount of the film, A film feeding apparatus comprising: a display element driving unit that stops the change with completion.