JPH0754346B2 - Memory IC test pattern generator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for testing a memory IC, and more particularly, to a test pattern generator capable of easily generating a complicated pattern. Regarding the device.

[Conventional technology]

A conventional test pattern generator is, for example, Japanese Patent Publication No. 57-5267.
As described in No. 9, a plurality of fixed registers that store initial values and the values stored in any of these fixed registers are selected and fetched, and the operation is performed by the fetched values. It was equipped with a plurality of arithmetic circuits and a plurality of arithmetic registers for selecting and capturing the output of any of the arithmetic circuits, and the test pattern of the memory IC was obtained from these plural output registers. .

[Problems to be solved by the invention]

In the above-mentioned conventional technology, all the test addresses of the memory IC are treated as a unified address, and the address of the test cell of interest, the address of the disturb cell, and the address of the disturb cell are generated one by one when generating the test pattern. There is a problem in that the values must be calculated in the arithmetic registers, and the arithmetic instructions given to these arithmetic registers become unnecessarily complicated.

In the test pattern of the memory IC, the address of the disturb cell is usually defined by the position relative to the address of the test cell of interest. That is,
It is necessary to successively generate the addresses of the disturb cells located at specific relative positions with respect to the address of the test cell of interest. Hereinafter, the address of the test cell will be referred to as a test address, and the address of the disturb cell will be referred to as a disturb address.

FIG. 2 shows a general test pattern generation procedure. First, in step 1, data 0 is written in all addresses, initial writing of test address and disturb address (offset; relative value, that is, displacement of address with respect to test address) are initialized, and then in step 2, Write data 1 to the test address and then read data 1 from the test address. Next, in step 4, data 0 is read from the disturb address, in step 5, data 1 is read from the test address, and the disturb address (offset)
Is updated, the procedure returns to step 4, and steps 4 and 5 are repeated. Exit when all disturb addresses are finished,
Go to step 6, write data 0 to the test address, update the test address, update the disturb address (offset), return to step 2, and return from step 2 to step 6.
repeat. When all the test addresses have been completed, the test is exited and the memory IC test ends.

In such a test pattern generation procedure, when returning from procedure 6 to procedure 2, the disturb address must be initialized and the test address must be updated. At this time, if the disturb address is defined by a relative value to the test address, in the arithmetic register operating the disturb address, it takes a plurality of steps to calculate the initial position of the disturb address for the updated test address, Calculation cannot be performed in one step. In a complicated pattern, a dummy cycle is likely to occur in this part due to insufficient computing capacity.

As a specific example, FIG. 3 schematically shows the operation of the arithmetic register when the test pattern is generated. Here, the operation of the arithmetic register when the test pattern is generated for the test addresses "100" and "101" assuming that two addresses before and after the test address are assumed to be disturb cells are shown. In the figure, ◯ and □ indicate the operation of the register that calculates the test address or the disturb address. The circle indicates the movement of the arithmetic register for the test address "100", and the square indicates the movement of the arithmetic register for the test address "101".

That is, first, the first test cell, address 100
Test address 10 for testing disturb cells
Go to address 98, 2 before 0, then test address 1
Go to address 99, one before 00, then test address
Go to address 101, one after 100, then go to address 102, two after test address 100. Then, similarly,
To test the next test cell, the disturb cell at address 101, go to address 99, which is two addresses before test address 101, then to address 100, which is one address before, and then address 102, which is one address after. To, then to address 103, two behind.

In this way, it is easy to see how the operation of the disturb address becomes more complicated than the operation of the test address. This is because the conventional arithmetic unit configuration is [disturb address = test address + offset (relative value; displacement)].
However, it is necessary to handle all test addresses and disturb addresses in a unified manner, and be sure to calculate the address value itself in one of the calculation registers, which makes the calculation instructions more complicated than necessary. .

It is an object of the present invention to provide an arithmetic unit configuration that focuses on the constituent elements of an address of a test pattern, and to provide a test pattern generation device for a memory IC that enables generation of a complicated pattern more easily.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention comprises a computing means.
First, the first computing means computes the constituent elements of the test pattern to be output, and then the second computing means combines the individual pattern elements computed by the first computing means to obtain the necessary structure. It is achieved by calculating a simple output pattern.

That is, the test pattern generation device of the present invention comprises at least one first register capable of storing an initial value and a counter capable of arbitrarily fetching the initial value and performing a calculation operation. A plurality of first arithmetic means, further comprising a second arithmetic means composed of an arithmetic logic operation circuit to which an arbitrary plurality of outputs of the first arithmetic means are input, The memory IC under test shows the result of the calculation by the second calculation means.
Is output as a test pattern.

Further, the test pattern generating device of the present invention includes at least one first register capable of storing an initial value,
It is composed of an arithmetic unit that can arbitrarily capture the initial value and a second register that captures the output of the arithmetic unit, and the output of the second register is input to the arithmetic unit. A plurality of first arithmetic means, further comprising a second arithmetic means composed of an arithmetic logic operation circuit to which an arbitrary plurality of outputs of the first arithmetic means are inputted, The operation result of the second operation means is the memory IC under test.
Is output as a test pattern.

FIG. 1 is a conceptual diagram showing a basic configuration example of the present invention. In the figure, reference numerals 100, 101 ... Calculate means (first calculation means) for constituent elements of the test pattern, and 200 is combination calculation means (second calculation means) for each constituent element.

In the present invention, the disturb address is not directly generated and generated, but, for example, the test address of interest,
The value of each component of the test pattern, such as the offset value from the test address, the offset value in the X direction from the test address, and so on, is calculated separately and then these values are used to calculate the disturb address easily. Can occur.

In addition, combining the individual constituent elements means that the constituent elements of one or a plurality of the above-mentioned test patterns input to the second calculating means are calculated by the second calculating means and the result is output. It means to do.

[Action]

With the above configuration, the operation of the disturb cell address is performed in the first arithmetic step or the arithmetic means by using the absolute value of the offset (relative value) of the test cell address and the disturb cell address with respect to the test cell address. The calculation is performed, and the second calculation means performs addition and subtraction between the calculation values of the respective constituent elements calculated by the first calculation means. In this way, the address values of the test cells, which are the individual elements that make up the disturb cell address, the offset values, and the operations between them can be specified individually, creating a very simple program. Therefore, it is possible to easily generate a complicated pattern.

Further, in the present invention, since the calculation means has a two-stage configuration,
Since it is possible to reduce the functional load of the arithmetic circuit that requires the feedback path in the first arithmetic means and to make the arithmetic unit having no feedback path in the second arithmetic means highly functional, it is possible to achieve high speed. it can.

〔Example〕

Embodiment 1 FIG. 4 is a block diagram showing a first embodiment of the present invention.

In the present embodiment, a case where the test pattern is generated with two test pattern components will be described as an example. Therefore, as shown in FIG. 4, the test pattern generator of the present embodiment has two arithmetic means (first arithmetic means) 100 and 101 for the constituent elements of the test pattern, and a combination arithmetic operation for each constituent element. Means (second arithmetic means) 200.
It is assumed that 1 and 2 are constant registers and 3 and 4 are counters, and that the counters 3 and 4 can perform UP count and DOWN count, and fetch of constant values. The constant registers 1 and 2 store constant values given to the counters 3 and 4. By means of the constant registers 1 and 2 and the counters 3 and 4, the calculation means 10 of the constituent elements of the test pattern
0 and 101 are configured respectively. 5-1 to 5-n and 6
-1 to 6-n are AND gates, 7-1 to 7-n and 8-
1 to 8-n are exclusive OR gates, 50, 51, 52 and 53 are control signals, 9 and 10 are + 1 / PASS circuits, and 11 is an adder. AN
The D gates 5-1 to 5-n and 6-1 to 6-n mask the outputs of the counters 3 and 4 according to the control signals 50 and 51, respectively.
All bits can be forced to zero. The exclusive OR gates 7-1 to 7-n and 8-1 to 8-n can invert the outputs of the counters 3 and 4 according to the control signals 52 and 53, respectively. The + 1 / PASS circuits 9 and 10 are +1 when the inversion is performed by the exclusive OR gates 7-1 to 7-n and 8-1 to 8-n at the previous stage, and are not changed when the inversion is performed. The value of is output. The adder 11 adds both the inputs of the arithmetic means 100 and 101 of the two pattern constituent elements and outputs the result. Assuming that the output value of the counter 3 is A, the output value of the counter 4 is B, and the output value of the adder 11 is P, in order to set P = A, the control signal 51 is set to "H" (1) and the remaining control is performed. The signals 50, 52 and 53 may all be "L" (0).
Further, in order to set P = AB, the control signals 50, 51 and 52 are set to "L" and the control signal 53 is set to "H". Similarly, set the control signal to “H”
Alternatively, various functions can be realized by setting the value to "L". This is shown in the operation function table of Table 1.

Next, in order to generate the disturb address for the test address "100" described in FIG. 3, the test address is generated by the counter 3 and the offset absolute value of the disturb address from the test address is generated by the counter 4. That is, in this example, the counter 4 is 2,1,1,2; 2,1,
It suffices to repeat 1,2; ... and [2,1,1,2]. The initial value of the counter 4 is set to 2 and can be generated only by the instructions -1, +0 and +1. Further, the output instruction is P = A-B when the disturb address is before the test address, and P = A when it is after the test address.
Only by setting + B, the test pattern shown in FIG. 2 can be generated, which is very simple.

As described above, in the present embodiment, the disturb address can be separated into the test address and the component of the offset, and the operation instruction can be individually given to each of them.
Complex patterns can be generated very easily.

In the above description, the pattern has been described as having two components, but the number of components is not limited to this, and it is obvious that any number may be prepared.

Further, the type of operation is limited to the arithmetic operation in the description, but logical operation is naturally possible. This is particularly effective in generating a data test pattern for the memory IC.

Further, in the above-described embodiment, the constant registers 1 and 2 are formed for each of the counters 3 and 4, respectively, but if a plurality of constant registers are used, a higher function can be achieved.

Furthermore, in the above-described embodiment, the counters 3 and 4 are used as the means for generating the pattern component, but the present invention is not limited to this.
The use of arithmetic units (arithmetic circuits) and arithmetic registers facilitates the generation of more complicated patterns.

This embodiment will be described below.

Second Embodiment FIG. 5 is a block diagram showing a second embodiment of the present invention. In the figure, 12 and 13 are arithmetic units, and 14 and 15 are registers. As shown in FIG. 5, the outputs of the registers 14 and 15 are
The signals are fed back to the arithmetic units 12 and 13 and input to the arithmetic logic operation circuit 200. These calculator 1
2, 13 and registers 14, 15 perform the same function as the counters 3, 4 in the first embodiment shown in FIG.
Other configurations, operations and effects are similar to those of the first embodiment.

〔The invention's effect〕

As described above, according to the present invention, since each element forming a test pattern is calculated, and then these are combined to calculate a desired pattern, a program for generating a test pattern becomes very simple and complicated. It is also possible to generate various patterns extremely easily.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram for explaining the principle of the present invention, FIG. 2 is a diagram showing a pattern calculation procedure, FIG. 3 is a diagram showing an example of generating a disturb address, and FIG. 4 is a first diagram of the present invention. 5 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram showing a second embodiment of the present invention. 1, 2 ... Constant register 3, 4 ... Counter 5-1 to 5-n, 6-1 to 6-n ... AND gate 7-1 to 7-n, 8-1 to 8-n ... Exclusive OR gate 9, 10 …… + 1 / PASS circuit 11 …… Adder 12, 13 …… Calculator 14,15 …… Register 100,101 …… Pattern constituent element calculation means 200 …… Combination of each constituent element Computing means

Claims (2)

[Claims] 1. A first arithmetic operation comprising at least one first register capable of storing an initial value and a counter capable of arbitrarily fetching the initial value and performing a calculation operation. A plurality of means, further comprising a second arithmetic means composed of an arithmetic logic operation circuit to which an arbitrary plurality of outputs of the first arithmetic means are inputted, and an arithmetic operation in the second arithmetic means Memory IC under test
Memory that outputs as a test pattern of
IC test pattern generator. 2. At least one first register capable of storing an initial value, an arithmetic unit capable of arbitrarily capturing the initial value, and a second register capturing an output of the arithmetic unit. And a plurality of first arithmetic means configured to input the output of the second register to the arithmetic unit, and further, an arbitrary plurality of the first arithmetic means. A second operation means composed of an arithmetic logic operation circuit to which the output of
Memory that outputs as a test pattern of
IC test pattern generator.