JPH0750594A - Error correcting method - Google Patents

Abstract

PURPOSE:To correct the errors and to properly carry out the interpolation of data by calculating a deletion position polynomial and acquiring a correction syndrome. CONSTITUTION:An erasing position polynomial deltaepsilon(z) is multiplied by modZ<d>-<1> to produce a correction syndrome polynomial Sepsilon(z) through an erasion register 50, an erasion control circuit 54 and an deletion address control circuit 55. Then the degree of the polynomial Sepsilon(z) is decided by two deciding routines. That is, the polynomial Sepsilon(z) is calculated and the deletion is corrected by an exclusive algorithm when Nr>degS(z) is satisfied between the degree degS of the polynomial Sepsilon(z) and the deletion number Nr to be corrected. Meanwhile a signal showing the incapability of correction is transmitted when Nr<=degSepsilon(z)<(d-1)/2+(Nr/2) is satisfied. When both degSepsilon(z)>=(d-1)/2+(Nr/2) and Nr<=degSepsilon(z) are satisfied, an error position is calculated by the Euclidean algorithm and the error and the deletion are corrected.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an error correction method.

[0002]

2. Description of the Related Art As a conventional error correction method, Japanese Patent Publication No.
There is one described in Japanese Patent Laid-Open No. 2-272727. Figure 1
1 to 14 are block diagrams showing an apparatus used for implementing the conventional example. FIG. 11 shows the overall configuration. In the figure, 1 is a program unit, 2 is an arithmetic operation unit, and 3 is a Galois operation unit. FIG. 12 shows details of the program unit 1. FIG. 13 shows details of the arithmetic operation unit (ALU) 2. 14
Shows details of the Galois computing unit (GLU) 3. In this example, an RS code on GF (2 ⁸ ) with a minimum distance of 17 will be used for description. FIG. 15 is a flowchart of executing Euclidean decoding. 16 and 17 show the RAMs 11 and 12 and the register file 1 of FIGS. 13 and 14.
The time passage of the contents of 4 is (a), (b),
(C) ,. ． ． It is a figure shown as (j).

In FIG. 12, a jump address setting circuit 1a sets a jump destination address. Reference numeral 1b is a program counter which takes an address from 0 to 1023 and can be interrupted by a jump instruction. Reference numeral 1c is a program ROM in which an execution control program is installed. 1d is a latch circuit that stores an instruction.

In FIGS. 13 to 15, reference numerals 5 and 6 are up / down counters that take numerical values from 0 to 31, for example. Latch circuits 7 and 8 are address data latch circuits, and the addresses are indexed, for example. 9, 1
0 is an adder for address and has a 6-bit configuration, for example. Although the sequence controller of the control system is omitted from the figure, its status flag F1 is the general reception flag register, F
2 is a general-purpose output flag register.

RAMs 11 and 12 are both working rams. Reference numeral 13 is an arithmetic operation unit (ALU). 14 is a register file, for example, 5 bits × 6
It has a word capacity and AD1, AD2, and AD3 (FIG. 5) are used as its addresses. Reference numeral 15 is an order latch circuit, which writes data in the register file 14 when a specific flag is set. Reference numeral 16 is a selector file 1
The data line (Ca, A, P, Cb) to be input to 4 is selected. Reference numerals 17 and 18 are registers for selecting and latching the data lines (R, A, P) to be input to the arithmetic operation unit 13. Here, A is the data of the arithmetic operation unit 13, P is the preset data, Ca is the numerical value of the counter 5, and C is
b is the value of the counter 6, R is the register file 1
It is a data line for selecting the numerical value of 4. F3 and F4 are counter status flags, and 19 is a Galois arithmetic unit (GL
In U), 20 is the arithmetic processor for performing Galois field arithmetic X + Z, X / Y, X · Y + Z, X ² · Y + Z and the like. F5 is a status flag from the Galois operation unit 19, F6 and F7 are output flags from the arithmetic operation unit 13,
Reference numeral 21 is an inverse element ROM, which is used for division of Galois field. The inverse ROM 21 has 256 bytes in this example. 22, 2
Registers 3 and 24 are selected from the data lines (P, A, B) input to the Galois arithmetic unit 29 and latched. Here, P is preset data, A and B are RAM
Terminals for selecting 11, 12 and selectors 25, 26 are used for data from the outside, such as syndrome and chain.
en) An input terminal I for inputting data from the search circuit and a terminal V for inputting the calculation result of the Galois calculation unit 19 are provided. A selector 17 is a selector for the output data lines (V, A, B, R) to the bus, (S
t), (Er), and (Ew) are flag registers for requesting reading from the bus and data output to the bus as to whether or not the flag register is in operation.

First, the coefficient data of S (z) is input to the RAM 11, and at the same time, the maximum degree of S (z) is obtained. Clear registers 22, 23 and 24. The syndrome data obtained by the syndrome calculation is sent from the T3 terminal to S
It is input to the register 24 as the coefficient of (z). The Galois arithmetic unit 19 examines the coefficient of S (z). S15,
S14 ,. ． ． "1" is output to the flag F5 except when S0 is 0. The highest degree 1 of Z ¹⁶ is entered in AD2 of the register file 14. Register file 14 A
The first order flag F5 = "1" causes the order latch circuit 15 to operate and the highest order of S (z) is entered in D1. Coefficient S15,
S14 ,. ． ． Latch S0 and input to RAM11. At this time, the value of the counter 5 is stored in AD1 of the register file 14. The counter 5 indicates the address of the RAM 11 and at the same time, the order of S (z) is entered as described below.

For example, S (z) data S15 and S1
4 ,. ． ． , When the first non-zero data is input by the input of S0, the flag F5 becomes "1", and the write inhibit command to the register file 14 is input through the terminal T5 from the order latch circuit 15 and the order data of the syndrome polynomial is the order latch. It is stored in AD1 of the register file 14 until the instruction of the circuit 15 is released. Let me explain this in more detail. The calculation output of the Galois calculation unit 19 is RA
It is stored in M11 or 12. The value of the counter matches the degree of the polynomial output from the Galois arithmetic unit 19. It is assumed that the polynomial operation starts from a high order. When input from the Galois arithmetic unit 19 to the order latch circuit 15, the numerical value of the counter is latched in AD1 of the register file 14 for each arithmetic step. Galois arithmetic unit 1
When 9 first outputs a non-zero numerical value, that is, the coefficient of the maximum degree of the polynomial of the calculation result, the flag F5 changes from "0" to "1".
Change to. Therefore, the coefficient is stored in the register file 14 as the maximum degree of the polynomial. While the flag F1 is "1", the order latch circuit 16 issues a latch prohibition instruction and does not allow the counter value to be latched thereafter. At the end of the calculation, the maximum degree of the polynomial is the register file 14
Stored in. In this way, the order of S (z) is latched and input to the register file 14. At the end of the calculation, the maximum degree of the polynomial output from the Galois arithmetic unit 19 is held at address 1 of the register file 14, so that each coefficient of the syndrome polynomial is held until the instruction of the next degree latch circuit is released.

The algorithm will be described with reference to the flowchart of FIG. 15 and the state diagrams of the RAMs 11 and 12 and the register file 14 of FIGS. 16 and 17. In order to execute the division, the coefficient "1" of the maximum degree of Z ¹⁶ is stored in the register 23. Next, the value of the maximum degree of S (z) (8
Enter the value from 16 to 16) and execute the division.

16 and 17, the RAM 11 is a RAM
11 is the content of RAM 12, and the content of RAM 12 is the content of RF1
Reference numeral 4 indicates the contents of the register file 14. FIG.
(A) has shown the state in the h point of FIG. That is, M2 (z) S (z) is "1" in the U _'1 (z) contains a memory contents 11. Register file 1
Address 1 of 4, ie AD1, contains the order of S (z), and address 2 contains the order of Z ¹⁶ "1". First, Q (z)
Find the order of. The data of address 2 (the degree of Z ¹⁶ ) enters the register 18 and the data of address 1 (the degree of S (z)) enters the register 17, and the arithmetic operation unit 13 performs an operation (contents of the register 18)-(contents of the register 17). ) Is calculated and obtained, and is input to AD4 of the register file 14. Next, Q (z) is calculated and multiplied by S (z) to obtain Z ¹⁶
And the remainder R (z) is obtained.

R (z) = Z ¹⁶ -Q (z) S (z) R (z) is input to the RAM and the order of R (z) is checked at the same time. The order of the obtained calculation result is input to the address 2 of the register file 14. (Replace with Z ¹⁶ ). As shown in FIG. 16, S (z) remains in the RAM 11. FIG. 16B shows the state at point j in FIG. Next, U ₁ (z) is calculated.

U ₁ (z) = Q (z) · U ′ ₁ (z) + U ₂ (z) This is calculated by the Galois arithmetic processor 20 and the order is checked at the same time. Initial value U ₂ (z) = 0, U ′
_{Since 1} (z) = 1, Q (z) only moves to U ₁ (z) at the beginning. Register file 14 as shown in FIG.
Input the degree of R (z) into address 2 of. At the same time, the arithmetic operation unit 13 checks whether the value is less than 8. If it is less than 8, a chain search is performed to get out of the loop and an error position is calculated, and an error value is calculated to correct the error. RAM
Looking at 12 and RAM 11 in reverse, 12 is used as the dividend M ₁ (z) and 12 is used as the divisor M 2 (z) to prepare for the next division.

The state shown in FIG. 16C is obtained. Perform the second division. New U ₁ to the RAM11 seeking new remainder R (z) as shown in FIG. 16 (d) repeating the same thing (z)
Goes in. The contents of RAM 12 do not change. Similarly R
The order of (z) is determined, and if it is less than 8, the loop is exited.
If it is 8 or more, the RAM 11 again indicates the divisor M2 (z), and R
AM12 indicates the dividend M ₁ (z) and the calculation is continued. Thus, as shown in FIG. 17F, the dividend M ₁ (z) is stored in the RAM ₁ in the RAM ₁ in the even-numbered steps.
The dividend M2 (z) is entered in 2, and the divisor M2 (z) is entered in the odd-numbered step, and the dividend M ₁ (z) is entered in the RAM 12, as shown in FIG. 17 (h). U when the calculation is completed
₁ (z) is σ (z), and R (z) is η (z)
Has become. U ₁ (z) = Q (z) U ₁ '(z) + U ₂
Since it is (z), (the order of U ₁ '(z)) + (Q (z)
The order of U1 (z) is calculated from the order of. U ₂ (z) is U
_The order is always lower than ₁ (z), so Q (z) and U ₁ '(z)
The sum of the orders of is the order of U ₁ (z). The calculation of these orders is performed in parallel with the polynomial calculation. Register file 1
Address 3 of 4 contains the highest degree of the position polynomial σ (z). In FIG. 17 (j), the final step is RAM 11 and RAM when the order of R (z) is less than 8 when it is an even step and when it is an odd step.
Replace the contents of 12. That is, η (z) and σ (z) are always stored in the RAM 11 in preparation for the next chain search. The position polynomial σ (z) and the numerical polynomial η (z) thus obtained are as follows: σ (z) = U ₁ (z) = K · σ ₀ (z) η (z) = R (Z) = K · η ₀ (z). Here, σ ₀ (z) and η ₀ (z) are equations in which the highest-order coefficient is normalized to 1. That is, the error position and the error value are directly obtained from the stage before obtaining σ ₀ (z) and η ₀ (z).

Σ (z) = K · σ ₀ (z) = K · Π (Z−α ₁ ) (Z−α ₂ ). ． ． (Z−α _t ) Next, the formal differentiation σ ′ (z) of σ (z) is performed. This is σ
It is composed of the odd-numbered terms of (z).

An error value e _i is obtained from e _i = η (α _i ) / σ ′ (α _i ) and the error position α _i is converted to the position i to correct the error.

As a conventional decoding algorithm for correcting errors and erasures, Yasuo Sugiyama, Masao Kasahara, Shigekazu Hirasawa, Toshihiko Namegawa, "Decoding algorithm for correcting errors and erasures", Itreeplee, Information Theory (Y.SUGIYAM)
A, M.KASAHARA, S.HIRASAWA and T.NAMEKAWA, ”An Erasur
es-and-Errors decoding Algorithm for Goppa Code
s ”, IEEE Trans. on Inform. Theory, pp.238-241, Mar
ch, 1976). I will explain it below.

Consider a code over GF (q) with a Goppa polynomial g (z). When the i-th received signal is lost, 0 is assigned to the i-th r _i of the received word. At that time, ε _i = r _i −a _i = −a _i is called an erasure value. i-th received signal is not lost but GF
If it is an element of (q), it is directly assigned to the i-th r _i of the received word. At that time, if e _i = r _i −a _i ≠ 0, it is said that an i-th error has occurred, and e _i is called an error value. Then the syndrome polynomial is

[Equation 2]

Is given by Position i where the error occurs
Let Ee be the set of positions and Eε be the set of positions where erasure is derived, and the error locator polynomial σe (z) and the error numerical polynomial η
e (z), φe (z), vanishing position polynomial σε (z), vanishing numerical polynomial ηε (z), φε (z) are

[Equation 3]

Is given by From the equation E90, the known polynomials S (z), σε (z) and the unknown polynomials σe (z), ηe
Between (z), φe (z), ηε (z) and φε (z)

[Equation 4]

The following relationship holds. σe (z), ηe
If (z) and ηε (z) are known, the error position i is σe
It is obtained by applying chain search to (z). The disappearance numerical epsilon _i and the error value e _i is given by _{ei = ηe (α i) /} σ e '(α i) εi = ηε (α i) / σε' (α i). Where σe '(z), σε'
(Z) is a polynomial in which the polynomials σe (z) and σε (z) are formally differentiated with respect to z. A decoding method for correcting errors and erasures is given by solving E91. E91 is called a basic equation. Three polynomials σ
(Z), η (z), and φ (z) are defined.

Σ (z) = σe (z) σε (z) η (z) = ηe (z) σε (z) + ηε (z) σe
(Z) φ (z) = φe (z) σε (z) + φε (z) σe
(Z) σ (z) is an error-erasure position polynomial, η (z), φ (z)
Is called an error-erasure numerical polynomial. At this time, the basic equation E9
1 can be written as η (z) = σ (z) S (z) + φ (z) g (z) (E92). Since the vanishing position polynomial σε (z) is known, a polynomial satisfying Sε (z) = σε (z) s (z) −φε (z) G (z) deg Sε (z) <deg g = d−1. Sε (z) and φε (z) can be calculated. This Sε (z) is called a modified syndrome polynomial. Therefore, the equation E92 is expressed as η (z) = σε (z) Sε (z) + [σe (z) φε (z) + φ (z)] g (z) (E93). This E93 is called a modified basic equation in the Euclidean decoding method for correcting erasure and error. The degree of each polynomial is deg σe (z) = Ne ≦ t− (Nr / 2) deg η ≦ ne + Nr-1 <t + Nr / 2 deg (σe · φε + φ) = deg (Sε · σε) −deg g ≦ ne-1 <T−Nr / 2 gcd (σe, σe · φε + φ) = 1 is satisfied. However, the number of Ne errors and Nr are the numbers of erasures.

Theorem 1: A set of polynomials satisfying the modified basic equation E93 {η (z), σe (z), σe (z) · φε
Only (z) + φ (z)} exists.

Theorem 2: Modified syndrome polynomial Sε
The error count is 0 if and only if the order of (z) is less than the erasure count Nr.

Theorem 3: Let pε (z) be the greatest common divisor of g (z) and Sε (z). At that time, the degree of pε (z) satisfies deg pε <t + Nr / 2.

Consider using the decoding result of C ₁ as the erasure for decoding C ₂ .

Consider the example of DAT. C1 is (32, 2
In 8, 5), C2 is (32, 26, 7). Since d = 5, if three or more errors can be detected and a flag indicating erasure is added, two errors are corrected, but the probability of error correction is actually Pm = A ₅ ( 32) ₅ C ₃ (Ps / 255) ³ (1-Ps)
²⁹ where Ps is the symbol error probability of the channel and Ak (n) is the number of codewords with weight k of n symbol codewords.

[Equation 5]

[0026] because becomes _{Pm = 32 C 5 · 255 (} Ps / 255) 3 = 3.0969 × Ps 3 detection probability PD = ₃₂ C ^₃ Ps ₃ true what -Pm detection flag is incorrectly Lighted data Although it is called an erasure, the probability is Pt = (3/32) ( ₃₂ C ₃ Ps ³ −Pm) + (5/32) Pm = (29/32) [( ₃₂ C ₃ ) Ps ³ −Pm] + (27 /32)Pm=466.94×Ps ³ Data that is correct and has a flag is called an empty erasure, but its probability is Pf = (29/32) (4960-30.969) Ps ³ + (27 / 32) ₅ C ₃ × ₃₂ C ₅ × 255 ^-2 Ps ³ = 4493.06 × Ps ³ That is, it is understood that the number of empty erasures is about 10 times larger than that of the true erasures.

Further, since d = 5, up to one error is corrected, two errors are corrected, and then a flag is attached. When three or more errors are detected, the flag is attached as it is.
In this case, four errors are the main probabilities of erroneous correction, so the erroneous correction probability Pm is Pm = A ₅ (32) (Ps / 255) ⁴ (1−Ps) ²⁸ = 0.0607235 × Ps ⁴ Pt = (3 / 32) ( ₃₂ C ₃ -Pm) + (5/32) × ₅ C ₃ × ₃₂ C ₅ × 255 ^-3 Ps ³ = 466.94 × Ps ³ Pf = (30/32) × ₃₂ C ₂ × Ps ² = 465Ps ^2, that is, the empty erasure is proportional to Ps ² , whereas the true erasure is proportional to Ps ^3, and therefore it can be seen that the empty erasure occurs overwhelmingly. Therefore, it is necessary to eliminate such empty erasures as much as possible, and to eliminate the erasures in ascending order of reliability and reliability.

Let's correct the erasures and errors with Euclidean decoding. Consider a (12,8,5) RS (Reed Solomon) code on GF (2 ⁴ ). The primitive polynomial is g (z) = Z ⁴ + Z + 1. The correspondence table between Galois field elements and binary vectors is given in Table 1.

Table 1 α ⁰ 0001 α ¹ 0010 α ² 0100 α ³ 1000 α ⁴ 0011 α ⁵ 0110 α ⁶ 1100 α ⁷ 1011 α ⁸ 0101 α ⁹ 1010 α ¹⁰ 0111 α ¹¹ 1110 α ¹² 1111 α ¹³ 1101 α ¹⁴ 1001 the alpha ¹⁵ 0001 codeword v = a ^{(100α0000α 12 0α 11 α 9)} . Received word = a ^{(100α 9 000000α 11 α 9)} . The Galois field address is (address) = (α ^- 1 ¹ α ^-10
If α ^-9 α ^-8 α ^-7 α ^-6 α ^-5 α ^-4 α ^-3 α ^-2 α ^-1 α ⁰ ), the error occurs at position α ^-8 (the error pattern is α ³ ). , The erasure occurs at the erasure position α ^-3 and the error pattern at α ¹² . The vanishing position polynomial is given by σε (z) = Z + α ⁻³ = Z + α ¹² syndrome S (z) is given by S (z) = α ⁶ Z ³ + α ⁴ Z ² + α ⁷ Z + α ¹² Sε (z) = S (z ) Σε (z) = α ⁷ Z ³ + α ¹⁴ Z ² + α ⁶ Z + α ⁹ given by deg Sε (z) = 3, (d-1) / 2 +
Since Nε / 2 = 2.5, Nr> deg Sε (z)
Is not satisfied, so only the erasure is decrypted (Erasures only decodi
ng) is not applicable.

Since (d-1) / 2 + Nr / 2≤deg Sε (z) is satisfied, the error locator polynomial σe (z) is first obtained by the Euclidean mutual division method. Goppa polynomial Z ^d-1 = Z ⁴
When the Euclidean mutual division method between S and Sε (z) is performed, Z ⁴ = (α ⁸ Z + 1) Sε (z) + α ³ Z + α ^{9 in the} first division, and deg r ₁ = 1 and deg r ₀ = 3 are repeated. Stop at the number of times k = 1. The quotient q ₁ (z) = α ⁸ Z + 1 and the remainder r ₁ = α ³ Z + α ⁹ are obtained.

U ₁ (z) = q ₁ (z) = α ⁸ (Z + α ^-8 )
Therefore, σe (z) = Z + α ^-8 = Z + α ⁷ .

Η (z) = r ₁ = (α ³ Z + α ⁹ ) α ^-8 = α ¹⁰ Z + α The error position is α ^-8 .

Since σ (z) = σeσε = (Z + α ⁷ ) (Z + α ¹² ), σ ′ (z) = α ⁷ + α ¹² = α ^{2 and} e 1 = η (α ⁻⁸ ) / σ ′ (α ^-8 ) = ^{α 3 ε1 = η (α -3} ) / σ '(α -3) = α 12 code word because becomes v is v = r + e + ε = (100α0000α 12 0α 11 α 9) and made with can restore the correct data.

If there are other empty erasures as shown in FIG. 9, the result is as shown in FIG. 9 (b). In the figure, the circle indicates that the data is correct and the disappearance flag is set. In the case of a code of d = 5, the number of disappearances is 4 or more and cannot be corrected. However, it can be corrected by ignoring the errors only decoding, that is, the erasure flag. Therefore, if the erasure flag is ignored, it becomes as shown in FIG. 9C, and only errors can be decoded (Errors Only). That is, the received word r = (1
It is the same as the previous example that an error occurs at positions α ^-3 and α ^-8 at 00α ⁹ 0000α ⁸ 0α ¹¹ α ⁹ ). The syndrome is S (z) = α ⁹ Z ³ + α ¹⁰ Z ² + αZ + 1, and there is no disappearance, so σε (z) = 1, that is, the modified syndrome matches the syndrome.

Sε (z) = S (z) deg Sε (z) = 3 and (d-1) / 2 + Nε / 2 = 2, so that Nr> deg Sε is not satisfied (d-1) / 2 + Nr / 2 ≦ Since deg Sε holds, the error position is obtained by the Euclidean mutual division method. When the Euclidean mutual division method is repeated with Z ⁴ and S ε (z), U ₂ = α ₃ (Z + α ⁷ ) (Z + α ¹² ) is obtained with the number of repetitions of 2 times (k = 2).

Σ (z) = (Z + α ⁷ ) (Z + α ¹² ) η (z) = α ⁻³ (α ⁴ Z + α ⁷ ) = αZ + α ⁴ σ ′ (z) = α ² e ₁ = η (α ⁻³⁾ ) / Σ '(α ^-3 ) = α ⁹ e ₂ = η (α ^-8 ) / α ² = α ³ decoded word v = r + e ₁ + e ₂ = (100α0000α ¹² 0α ¹¹ 0α ⁹ ) and the error is corrected. .

[0037]

However, in the above method, since the form of the syndrome S (z) between the error-only decoding and the erasure / error decoding is obviously different, the method based on the generalized distance decoding ( In Japanese Patent Publication No. 5-8610: Sugiyama, Onishi) and a method of decoding hard decision and soft decision twice or more (Japanese Patent Publication No. Sho 60-218926: Onishi), each decoding must be redone from the beginning. However, there was a problem that the decoding time took about twice or several times.

According to the present invention, the lost symbol of the received word is directly replaced with another dummy symbol such as 0 symbol so that the same S (z) can be used for decoding regardless of whether there is an erasure. By decoding, the S (z) pattern is standardized to speed up the decoding.

Further, when the correction condition is analyzed by the syndrome and the number Nr of disappearances, it becomes as shown in FIG. In the figure, the area B is a triangular area B surrounded by deg Sε (z) ≦ Nr and Nr ≦ d−1. When this condition is satisfied, correct data can be obtained only by erasure decoding. Also, deg
Above Sε = (d-1) / 2 + Nr / 2 and deg
A triangular area A surrounded by Sε (z) ≦ d−1 is an area that can be corrected by erasure / error decoding. The region C which is neither of them is when deg Sε (z) is Nr ≦ deg Sε (z) ≦ (d−1) / 2 + Nr / 2, and correct correction is not guaranteed.

Thus, by classifying the correction conditions according to the value of deg Sε (z), it is possible to accurately judge the error situation and execute the decoding. The algorithm flow of this decoding is summarized in FIGS. In addition, L obtained by L = Nr or L = Nr + j−1 in FIG. 2 gives a moving range (1 to L) of i in the following routine ei = η (α _i ) / σ ′ (α _i ). That is, L represents the number of erasures when there is no error, and the sum of the number of errors and the number of erasures when there is an error.

In addition, an error position which does not exist in the conventional method of finding the root by the chain search circuit from the coefficient of the error locator polynomial σ (z) can be found, or the number of error positions does not match the order of σ (z), so that a malfunction occurs. Therefore, there was a problem that erroneous correction occurred.

[0042]

According to a first aspect of the present invention, an erasure register (50), an erasure control circuit, and an erasure address control circuit are used to calculate an erasure position polynomial σε (z) into a mod Z
Multiply by ^d-1 to create a modified syndrome polynomial Sε (z), and its order is determined by two determination routines, so if it cannot be corrected, it is detected accurately and left to suboptimal measures such as data correction. Can do things

In the invention described in claim 3, in Euclidean decoding, only errors of the same received data are decoded (Errors only).
By making the syndrome S (z) of decoding) common and using the same syndrome coefficient, it is possible to perform decoding after determining which is better for decoding only by the order determination of the modified syndrome.

The invention described in claim 4 is a numerical polynomial η.
Since it has a register file that stores the degree of (z) and the degree of the position polynomial σ (z) and a latch memory that determines the degree, it is possible to detect an uncorrectable error by comparing the degrees with each other. You can

According to a fifth aspect of the present invention, the erasure position polynomial is calculated by the erasure register and the erasure control circuit, and the corrected syndrome polynomial S is calculated by the register file and the order latch.
Since it has a routine for determining the degree of ε (z), it is possible to increase the number of combinations of erasures and errors that can be corrected by changing the erasure position polynomial multiple times and recalculating the modified syndrome.

According to a sixth aspect of the present invention, the memory for accumulating the coefficient of the syndrome polynomial S (z), the erasure position register indicating the erasure position, and the erasure control circuit initially set Sε (z) = S (Z) as an initial value. As a register and RAM
And Galois arithmetic unit sequentially Sε (z) = Sε (z) ×
Since (Z−α _ij ) is calculated, the new modified syndrome Sε (z) can be calculated with a small amount of calculation even if the number of disappearances increases.

According to the seventh aspect of the invention, the range for generating the Galois element in the product-sum circuit is the code length (0, 1, 2, ...).
It has a counter that counts whether or not there is a "0" detection signal for the order of σ (z), and a comparator circuit that compares the numerical data from the latch memory of σ (z). Therefore, it is possible to detect an erroneous position that does not exist and prevent erroneous correction.

Since the invention described in claim 8 has a counter for reducing the number of "0" detection signals of the product-sum circuit and the numerical data from the order latch and a circuit for comparing the two, a defect such as a double root is detected. It is possible to prevent erroneous correction.

The invention according to claim 9 is the disappearance register,
A reliability order register and an erasure control circuit are provided to multiply the syndrome polynomial by the erasure position polynomial at most d-1 times,
The decision circuit decides whether or not the Euclidean mutual division method should be performed for the order of the modified syndrome polynomial at most d times, and corrects errors and erasures.

In this case, in the double coding such as the product code, at the time of the first-stage decoding, the reliability is sorted according to the decoding state, and the information corresponding to the reliability is used as the erasure information as the second information.
It may be used for decryption of.

[0051]

According to the first aspect of the present invention, since the erasure register, the erasure control circuit, and the erasure address control circuit are provided, the erasure position polynomial is calculated and the product is obtained with the syndrome S (z) to obtain the corrected syndrome. If the condition cannot be corrected by checking the order, it has the effect of entrusting it to suboptimal measures such as data interpolation.

In the invention described in claim 3, regardless of whether or not there is disappearance, the value of the syndrome S (z) is made the same and the number of disappearances is sequentially increased, and the same value of S (z) itself is used. There is a function that can be calculated.

According to the fourth aspect of the present invention, the Galois arithmetic unit, the arithmetic arithmetic unit, the memory, the register, and the order latch circuit compare the orders of the numerical polynomial and the position polynomial, and when an uncorrectable error occurs, the error is corrected. It has a detecting function.

The invention according to claim 5 is an erasure register,
Since the erasure control circuit, the Galois arithmetic unit, and the arithmetic arithmetic unit calculate the order of the correction syndrome at least a plurality of times, it has an effect of efficiently correcting errors and erasures.

According to the sixth aspect of the invention, since the memory for storing the coefficient of the modified syndrome polynomial Sε (z) and the erasure position polynomial are multiplied by the Galois arithmetic unit to sequentially obtain, Sε
There is an effect that a new modified syndrome Sε (z) can be obtained by updating the value of (z) in the coefficient data of the RAM one after another.

According to the seventh aspect of the present invention, since the product-sum circuit in the chain search circuit generates only Galois elements corresponding to the code length from 0 to N-1, roots exceeding the range are to be the order data and roots. It has the effect of detecting the number of.

The invention described in claim 8 is the position polynomial σ
Since there is a degree latch that stores the degree of (z), a counter that checks the number of detected "0" s, and a circuit that compares the two, there is an effect of detecting that σ (z) has an irrational root such as a double root.

The invention described in claim 9 is an erasure register,
The reliability order register and the erasure control circuit are provided, the erasures are ordered in ascending order of reliability, and the correction is repeated as erasures in order from the lowest, so that the correction capability is improved.

[0059]

【Example】

Embodiment 1 The overall configuration of the apparatus used for carrying out the correction method of the present invention, the program unit 1, and the Galois operation unit 3 are the same as those in FIGS. The arithmetic operation unit 2 is as shown in FIG.

Below, the GF with the number of disappearances Nr at the minimum distance d
The case where the RS code in (2 ⁸ ) is used will be described.
2 to 4 are flowcharts for executing Euclidean decoding. 5 and 6 show the RA of FIG. 1 and FIG.
M11, 12 and the contents of the register file 14 over time are (a), (b), (c) ,. ． ． It is a figure shown as (j).

In FIG. 1, the same symbols in FIG. 1 indicate the same or corresponding portions as in FIG. In the figure, 49 is a received word register, 50 is an erasure register, 51 is a reliability ordering circuit, 52 is a reliability order register, 53 is an erasure counter, 54 is an erasure control circuit, and 55 is an address control circuit. A Galois field conversion ROM 56 stores a conversion table as shown in Table 1. An erasure and error position register 57 has a capacity of 8 bits × (d−1).

The erasure register 50 is of n bits,
"1" is stored at the location where the data is lost, and the data is output to the loss counter 53 in synchronization with the clock according to a command from the control system. The reliability ordering circuit 51 orders received symbols up to d−1 in order of reliability on the receiving side. The reliability order register 52 is a reliability ordering circuit 5.
The order assigned by 1 is input to the erasure control circuit 54 in synchronization with the erasure register, and the data causes the erasure control circuit 5 to operate.
4 determines whether to treat the information in the erasure register as erasure and when erasure is performed, the erasure number counter 53 is increased and the address control circuit 55 together with the error counter 5 creates the erasure and error address positions. First, the erasure register is input from the erasure register 50, the erasure number counter 53, the address control circuit 55, the erasure and error position register 57, and the Galois field conversion ROM 5
First alpha _i erasure information sequentially input by 6 RAM1
Stored in 2. (The I terminal of the selector 26 is connected to a bus for selecting an input from the outside, and I is activated to input the disappearance information from the outside.) Next, each coefficient of the syndrome S (z) is Sε ( As an initial value of z),
It is stored in the RAM 11 and is multiplied by the coefficient one after another by the GLU 19 to obtain Sε (z) = S (z) (Z−α _ij ) (j = 0 to 0).
Nr) is calculated. The coefficient of Sε (z) is updated one after another. The modified syndrome polynomial Sε is stored in the RAM 12.
The coefficient of (z) is stored. Sε (z) is rewritten a maximum of d−1 times. The iterative calculation of this part performed here is as follows. (Sε = σε (z) S in FIG. 2
(Z) This is a calculation corresponding to modZ ^d-1 and is a calculation of modZ ^d-1 . ) Therefore, Sε (z) = S (z) Π (Z−α _ij ) (j = 1 to
Nr).

Next, the coefficient data of Sε (z) is transferred to the RAM 11
And simultaneously obtain the maximum degree of Sε (z). Clear registers 22, 23 and 24. The syndrome data obtained by the syndrome calculation is sent from the T3 terminal to S
It is input to the register 24 as a coefficient of ε (z). The Galois arithmetic unit 19 examines the coefficient of Sε (z). Sε
_d-2 , Sε _d-3 ,. ． ． Flag F unless S ε ₀ is 0
“1” is output to 5. AD of register file 14
The highest degree 1 of Z ^d-1 enters into 2. Register file 1
In AD1 of 4, the order latch circuit 15 is activated by the first flag F5 = “1” and the highest order of Sε (z) is entered. Coefficients S ε _d-2 , S ε _d-3 ,. ． ． Latch Sε ₀ and RAM1
Input to 1. At this time, AD1 of the register file 14
The value of counter 5 is entered in. Thereafter, FIGS.
Since it is the same as the movement of, it is omitted. When the Euclidean calculation is completed, the state of FIG. Then U
Calculate ₁ (z).

U ₁ (z) = Q (z) · U ′ ₁ (z) + U ₂ (z) The Galois arithmetic processor 20 calculates this and at the same time checks the order. Initial value U ₂ (z) = 0, U ′
_{Since 1} (z) = 1, Q (z) only moves to U ₁ (z) at the beginning. As shown in FIG. 5B, the order of R (z) is input to the address 2 of the register file 14. At the same time, the arithmetic operation unit 13 checks whether the value is less than Dε = (d−1) / 2 + Nr / 2. If it is less than Dε, a chain search is performed to exit the loop and find an error position, and an error value is calculated to correct the error. RAM12 and RAM11
Inversely, 12 is the dividend M ₁ (z) and 12 is the divisor M 2
Prepare for the next division in the same manner as (z).

The state shown in FIG. 5C is obtained. Perform the second division. The same process is repeated to find a new remainder R (z) as shown in FIG. 5D, and a new U1 (z) is entered in the RAM 11. The contents of RAM 12 do not change. Similarly R
The order of (z) is determined, and if it is less than Dε, the loop is exited. If it is Dε or more, the RAM 11 shows the divisor M2 (z) again, and the RAM 12 shows the dividend M ₁ (z), and the operation is continued. Thus, as shown in FIG. 5 (f), the dividend M ₁ (z) is stored in the RAM 11 in the even-numbered step as RA
The dividend M2 (z) is entered in M12, and the divisor M2 (z) is stored in the RAM12 in the odd-numbered step as shown in FIG. 6 (h).
The dividend M ₁ (z) is entered in. U when the calculation is completed
₁ (z) and R (z) are calculated.

Position polynomial σ obtained in this way
(Z), the numerical polynomial η (z) is given by σ (z) = K · U ₁ (z) · σε (z) R (z) = K · η (z) as shown in the following equation.

FIG. 7 shows a chain search circuit C according to the present invention.
S0, CS1, CS2 ,. ． ． CSt is a memory that stores the coefficient of σ (z). However, t is t = [(d-1) / 2] where [] is a Gaussian symbol.

EG1, EG2 ,. ． ． EGt generates an element α ⁱ of the Galois field, EG1 remains unchanged, EG2 is squared ,. ． ． EGt is raised to the power of t to obtain a coefficient σ ₁ ,
σ ₂ ,. ． ． multiply by σ _t

[Equation 6]

This is a Galois element generation circuit for calculating and whether or not the value becomes 0.

The Galois _{element by} which σ ₀ is multiplied is always α ⁰ (= 1)
So I don't need anything there. 62 is a product-sum operation circuit

[Equation 7]

Calculate L = 1, 2 ,. ． ． It is N-1. N is a code length and N ≦ 2 ^m −1. m is the expansion order of the Galois field and m = 8 when GF (2 ⁸ ). WD0 is a "0" detection signal, 63 is a counter, 64 is a σ (z) order data signal line from the order latch, and 65 is between σ (z) order and position 0 to position (N-1). A comparison circuit 66 for comparing the number with the root by the chain search, 66 is the root α ⁱ¹ , α ⁱ² ,. ． ． α
^This is the signal line that outputs ^it .

Its coefficient σ _{0 of} the error locator polynomial σ (z),
σ ₁ ,. ． ． When σ _t is determined, the number of error positions α ⁱ¹ , α
ⁱ² ,. ． ． To obtain α ^it , the root when σ (z) = 0 should be obtained. Galois field elements α ⁰ , α ¹ ,. ． ． α
The root of σ (z) = 0 is obtained by successively substituting ^2m−2 into Z of σ (z) and checking whether the value becomes 0.
The Galois field element α ^L (L = 0,
1 ,. ． ． N−1 ≦ 2 ^m −2) is σ ₀ ,
σ ₁ ,. ． ． It is multiplied by σ _t and is 0, 1 and 2 respectively.
Squared ,. ． ． It is raised to the power t and input to the sum-of-products circuit 62. The product-sum circuit 62 calculates whether or not the expression (E94) is satisfied. That is, the sum σ ₀ + σ ₁ α + σ ₂ α ² +. ． ． + Σ _t α ^t =
If 0 holds, the correction circuit is activated and the error pattern ei is added by mod2 to correct the error.

By the way, the code length of the RS (Reed Solomon) code is n = 2 ⁸ -1 = 255, that is, 255 symbols in the case of GF (2 ⁸ ).
= 120, the symbol addresses are 0 to 119
Since it is an address, for example, α ⁰ , α ¹ ,. ． ． α ¹¹⁹ becomes the address of Galois field representation, and the addresses from α ¹²⁰ to α ²⁵⁴ cannot be found as a solution. Therefore, when the error position obtained by the chain search circuit of FIG. 7 indicates addresses from α ¹²⁰ to α ^254, it is found that an uncorrectable error is included, and therefore an uncorrectable detection signal is output. Leave it to the next best solution such as data interpolation. Also, the coefficients of σ (z) σ ₀ , σ ₁ ,
σ ₂ ,. ． ． σ _t is obtained, and σ is obtained by the order latch circuit.
The order of (z) has been determined. For example, R in FIG.
AM11 contains the coefficients of η (z) and σ (z). At the same time, since the coefficient of σ (z) as the degree of U1 (z) is included in the register file 14 as the degree of η (z) as the degree of R (z), degη (z) <degσ (z) does not hold. Since an error that cannot be corrected is included, an error detection signal is output.

Further, the order of σ (z) may not match the number of solutions obtained by performing the chain search. For example σ
When the order of (z) is 4 and the number of roots obtained by performing the chain search is 3, there are multiple roots included, or outside the range described above (from α 1 ²⁰ to α ^{254 in} the previous example). Since the position) clearly causes an erroneous correction, an uncorrectable detection signal is output.

As hardware for executing this, as shown in FIG. 7, the "0" detection signal WD0 is output and the counter 63 is incremented when the expression A is satisfied in the product-sum circuit 62.

The order of σ (z) is input from the order latch circuit 14 to the comparison circuit 65 through the signal line 64, and the order of σ (z) and the address of the Galois field up to the code length N (α ⁰ ,
α ¹ ,. ． ． The comparison circuit 65 determines whether or not α ^N-1 ) has a predetermined number of roots or does not have a double root. If they do not match, an uncorrectable detection signal is output.

Next, the formal differentiation σ '(z) of σ (z) is performed. It consists of odd-order terms of σ (z).

The error value e _i is obtained from e _i = η (α _i ) / σ ′ (α _i ) and the error position α _i is converted to the position i to correct the error.

The chain search circuit shown in FIG.
It is connected to the circuits 12 and 14 via a bus (not shown).

Embodiment 2 In Embodiment 1 described above, the chain search circuit of FIG.
Although it is assumed that the circuit is configured by hardware different from the circuits of 11, 12, and 14 and is connected to the circuits of FIGS. 1, 11, 12, and 14 by a bus, as another method, the program unit 1 of FIG. A program for realizing the chain search function may be stored and the arithmetic operation unit (ALU) 2 and the Galois operation unit (GLU) 3 may be operated in accordance with the program. In this case, σ ₀ , σ ₁ ,. ． ． register CS0 to store sigma _t, CS1,. ． ． CSt is the R of FIG.
It is configured by a part of AM11 and has multipliers EG1 and EG
2 ,. ． ． ． The Galois computing unit 19 has the function of EGt. The sum of products circuit 62 is also realized by executing an operation based on the program. Furthermore, counter 6
3 is also realized by the program. Alternatively, a general-purpose counter (for example, the counter 6) may be given that role. The ALU is provided with a register that stores the error and its position, and a register that stores the number, and the Galois operation unit (E9
The root can be calculated by serially calculating the data by the equation (4). In this case, the product-sum operation is executed by the GLU, and it is checked by the flag F5 as to whether or not the result is "0",
If it is "0", the program unit 1 increases the register value indicating the error number of the ALU and stores the position data.

The ALU register 18 stores the order of σ (z), and the register 17 stores the number obtained by the chain search. If both are subtracted and it is “0”, σ (z)
The number of roots and the number of roots obtained by the chain search match, so correction is performed. If they do not match, a flag for data correction is output.

Embodiment 3 As described in Japanese Patent Publication No. 60-218926, reliability information of a received symbol is obtained from information at the time of demodulation from a communication channel or by decoding at the first stage of double coding to obtain reliability information in the received symbol. In order (order of lowest reliability), order is performed up to d-1. For example, the code C1 of the first stage (C1 is (N, K, D)
For the decoding of the code), [(D-1) / 2] or less errors are corrected, and the symbol rj of the code C2 in the second stage is output as intermediate information. At this time, if i errors are corrected, the weight wj is set as the weight. When i errors are corrected, wj = i When an error is detected, a value wj such as wj = D / 2 is set, and a flag signal or the like is set. It is stored in a register so that it can be used when C2 is decrypted. The reliability ordering circuit 51 of FIG. 1 orders the low reliability symbols (bad) up to at least d-1 symbols. The ordered symbols are input to the C2 decoder at the same time as the erasure symbol information, the reliability order information, the erasure register, and the reliability order register, and the erasure control circuit changes the number of erasures from 0 to a maximum of d. By inputting up to -1, the decoding can be performed by determining the order of the modified syndrome at most d times instead of repeating the decoding d times based on the flowchart of FIG.
This will be explained below. The received vector is first calculated S (z) and at the same time selected by the reliability ordering circuit 51 up to d-1. The positions of the symbols are β ₁ , β ₂ ,. ． ． β
_{Let d-1} .

[0083]

[Equation 8]

Let (q be a positive integer where q = 2 ^m ) be a Galois field element. First, Nr = 0 is set as no erasure, and the erasure position polynomial σε (z) = 1. At this time, Sε (z)
= S (z), and the discriminant routine Ds compares the degree of Sε (z) with the magnitude of (d-1) / 2 + Nr / 2. If the determination is no, the next determination routine Dr compares the number Nr of erasures with the degree, and if Nr is large, a routine Ers for executing erasures only decoding is executed.

When Nr ≦ deg Sε (z), the Euclidean algorithm is executed to obtain the error-erasure position polynomial η (z). The error-disappearance value can be obtained according to e _i = η (α _i ) / σ ′ (α _i ). When the determination of Ds is YES, the symbol with the next lowest reliability is added as erasure. β _{i + 1} joins the vanishing set {β _i }. The erasure position polynomial σε (z) is recalculated to recalculate Sε (z) and input to the determination circuit Ds. In this way, when the order of the maximum d-1 times corrected syndrome polynomial is judged and the solution is not found, the judgment routine Dx shifts to the correction processing and leaves it to the suboptimal measure. In this way, the empty erasure is effectively eliminated, and the symbols are considered to be error and true erasures, and the decoding algorithm is sequentially executed to perform the correction, so that highly reliable decoding can be performed without waste.

[0086]

The invention according to claim 1 is provided with an erasure register, an erasure control circuit, and an erasure address control circuit, calculates a erasure position polynomial, and obtains a modified syndrome by multiplying it with the syndrome S (z). Since the order is checked and the condition cannot be corrected, it is decided to entrust it to the suboptimal measure such as data interpolation, so that there is an effect that the correction and the data interpolation can be appropriately performed.

Since the modified syndrome Sε (z) is used in common in the invention described in claim 3, there is an effect that it is not necessary to recalculate the syndrome data and the error and erasure can be corrected at high speed by using the same syndrome data.

The invention according to claim 4 compares the orders of the obtained numerical polynomial and position polynomial, and detects that an uncorrectable error has occurred when deg η (z) <deg σ (z) is not satisfied. Then, the data is corrected and the like, which is effective in preventing erroneous correction.

According to the fifth aspect of the present invention, since the Galois computing unit for calculating the erasure position polynomial σε (z) multiple times, the erasure register, the order latch circuit, the register file, and the memory are provided, the modified Sindrone Sε (z) There is an effect that the order is determined and whether or not the error should be corrected is determined and corrected.

According to the sixth aspect of the invention, since the modified syndrome polynomial Sε (z) is sequentially calculated, the register (11) for storing the coefficient of Sε (z) and the next less reliable erasure position (Z-α _ij ) Sε (z) = Sε (z) × (Z−
α _ij ) and the corrected syndrome Sε (z)
Each time the number of disappearances increases, there is an effect that it can be calculated in order at high speed.

In a seventh aspect of the present invention, the product search and sum circuit of the chain search generates Galois elements corresponding to the code length from 0 to N-1, and the root outside the range is a position polynomial σ (z). There is an effect of detecting by comparing with the value of the order latch.

According to an eighth aspect of the present invention, the number of "0" detection signals output from the product search circuit of chain search is counted and σ
This has the effect of confirming whether the number of roots in (z) is appropriate. In the invention described in claim 9, the number of erasures is sequentially increased from 0 to d−1, and it is determined whether or not the correction should be made only by the value of the order of the correction syndrome, and the error and the erasure are corrected. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arithmetic operation unit used for implementing the present invention.

FIG. 2 is a decoding algorithm flowchart of an embodiment of the present invention.

FIG. 3 is a flowchart of a decoding algorithm according to an embodiment of the present invention.

FIG. 4 is a decoding algorithm flowchart according to the embodiment of the present invention.

FIG. 5: R performing the Euclidean algorithm
It is a figure which shows the time passage of the content of the register file which memorize | stores the content of AM, and the degree of a polynomial.

FIG. 6 is an R for executing the Euclidian algorithm
It is a figure which shows the time passage of the content of the register file which memorize | stores the content of AM, and the degree of a polynomial.

FIG. 7 is a block diagram showing a chain search circuit used in an embodiment of the present invention.

FIG. 8 is a flowchart showing a decoding algorithm of another embodiment of the present invention.

FIG. 9 is a diagram for explaining an error in a received word, an erasure flag, and empty erasure.

FIG. 10 is a diagram in which the correction operation of the decoder is classified by the number of erasures Nr and the order of the correction syndrome.

FIG. 11 is a block diagram showing an overall configuration of an apparatus used for implementing the conventional correction method and the correction method of the present invention.

12 is a block diagram showing a program section of FIG. 11. FIG.

13 is a block diagram showing an arithmetic operation section of FIG. 11.

14 is a block diagram showing a Galois computing unit in FIG. 11. FIG.

FIG. 15 is a diagram showing a conventional decoding flowchart.

FIG. 16 is a diagram showing the contents of a conventional RAM and register file.

FIG. 17 is a diagram showing the contents of a conventional RAM and register file.

[Explanation of symbols]

1: Program part 2: Arithmetic operation part 3: Galois operation part 50: Disappearance register 51: Reliability ordering circuit 52: Reliability order register 53: Disappearance counter 54: Disappearance control circuit 55: Disappearance address control circuit 63: Counter 64: Numerical data signal line 65 from the order latch 67: Comparing circuit 67: Correctness / inability detection signal Dr: Sε (z) order and judgment routine Ds: Sε (z) order and (d-1) ) / 2 + Nr / 2 decision routine for magnitude comparison Dx: Jr decision routine for magnitude comparison between Nr and d-1 Ers: Routine for decoding only erasure WD0: "0" detection signal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 29, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 5

[Correction method] Change

[Correction content]

[Equation 1] (However, when j = 0, σε (z) = 1 is calculated) and a determination routine for decoding using Euclidean mutual division method only when deg Sε (z) ≧ (d−1) / 2 + Nr / 2 Error correction method with.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 6

[Correction method] Change

[Correction content]

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

RAMs 11 and 12 are both working rams. Reference numeral 13 is an arithmetic operation unit (ALU). 14 is a register file, for example, 5 bits × 6
It has a word capacity and AD1, AD2, and AD3 (FIG. 5) are used as its addresses. Reference numeral 15 is an order latch circuit, which writes data in the register file 14 when a specific flag is set. Reference numeral 16 is a selector file 1
The data line (Ca, A, P, Cb) to be input to 4 is selected. Reference numerals 17 and 18 are registers for selecting and latching the data lines (R, A, P) to be input to the arithmetic operation unit 13. Here, A is the data of the arithmetic operation unit 13, P is the preset data, Ca is the numerical value of the counter 5, and C is
b is the value of the counter 6, R is the register file 1
It is a data line for selecting the numerical value of 4. F3 and F4 are counter status flags, and 19 is a Galois arithmetic unit (GL
In U), 20 is the arithmetic processor for performing Galois field arithmetic X + Z, X / Y, X · Y + Z, X ² · Y + Z and the like. F5 is a status flag from the Galois operation unit 19, F6 and F7 are output flags from the arithmetic operation unit 13,
Reference numeral 21 is an inverse element ROM, which is used for division of Galois field. The inverse ROM 21 has 256 bytes in this example. 22, 2
Registers 3 and 24 are selected from the data lines (P, A, B) input to the Galois arithmetic unit 19 and latched. Here, P is preset data, A and B are RAM
Terminals for selecting 11, 12 and selectors 25, 26 are used for data from the outside, such as syndrome and chain.
en) An input terminal I for inputting data from the search circuit and a terminal V for inputting the calculation result of the Galois calculation unit 19 are provided. 27 is a selector for the output data line (V, A, B, R) to the bus, (S
t), (Er), and (Ew) are flag registers for requesting reading from the bus and data output to the bus as to whether or not the flag register is in operation.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

Is given by From the equation E90, the known polynomials S (z), σε (z) and the unknown polynomials σe (z), ηe
Between (z), φe (z), ηε (z) and φε (z)

[Equation 4]

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction content]

The invention described in claim 8 has a counter for counting the numerical data from the order latch and the number of "0" detection signals of the sum-of-products circuit and a circuit for comparing the two. Can be detected to prevent erroneous correction.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0061

[Correction method] Change

[Correction content]

In FIG. 1, the same symbols in FIG. 1 indicate the same or corresponding portions as in FIG. In the figure, 49 is a received word register, 50 is an erasure register, 51 is a reliability ordering circuit, 52 is a reliability order register, 53 is an erasure counter, 54 is an erasure control circuit, and 55 is an address control circuit. Further, 56 is a Galois field conversion ROM, which is GF (2 ⁸ )
It records the conversion table for such as Table 1 in. An erasure and error position register 57 has a capacity of 8 bits × (d−1).

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

Its coefficient σ _{0 of} the error locator polynomial σ (z),
σ ₁ ,. ． ． When σ _t is determined, the number of error positions α ⁱ¹ , α
ⁱ² ,. ． ． To obtain α ^it , the root when σ (z) = 0 should be obtained. Galois field elements α ⁰ , α ¹ ,. ． ． of α
The root of σ (z) = 0 is obtained by successively substituting (2 ^m −2) th power into Z of σ (z) and checking whether or not the value becomes 0. The Galois field element α ^L (L = 0,
1 ,. ． ． N−1 ≦ 2 ^m −2) is σ ₀ ,
σ ₁ ,. ． ． It is multiplied by σ _t and is 0, 1 and 2 respectively.
Squared ,. ． ． It is raised to the power t and input to the sum-of-products circuit 62. The product-sum circuit 62 calculates whether or not the expression (E94) is satisfied. That is, the sum σ ₀ + σ ₁ α + σ ₂ α ² +. ． ． + Σ _t α ^t =
If 0 holds, the correction circuit is activated and the error pattern ei is added by mod2 to correct the error.

[Procedure Amendment 9]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure Amendment 10]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

[Procedure Amendment 12]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 16

[Correction method] Change

[Correction content]

FIG. 16 ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 13, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

The algorithm will be described with reference to the flowchart of FIG. 15 and the state diagrams of the RAMs 11 and 12 and the register file 14 of FIGS. 16 and 17. Register 24 to perform a division entering the maximum coefficient of order "1" of Z ^16. Next, the value of the maximum degree of S (z) (8
Enter the value from 16 to 16) and execute the division.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (11)

[Claims] 1. An erasure generated by a register into which erasure is obtained by obtaining a syndrome polynomial S (z) of a received word and reliability information at the time of data demodulation or erasure information by a decoding result of a preceding stage of a code using double coding. Position polynomial σε (z)
Then, the Galois arithmetic unit multiplies the syndrome by the disappearance position polynomial to obtain a modified syndrome polynomial Sε (z)
Is calculated by an arithmetic expression of Sε (z) = σε (z) S (z) mod Z ^d-1 (where d is the minimum distance of the code), and an error position and an error numerical value are obtained by the Euclidean mutual division method. And the erasure correction decoding method, the modified syndrome polynomial S (z) is calculated, and this S
When the relation of Nr> deg Sε (z) holds between the degree degSε of ε (z) and the number Nr of erasures to be corrected, correction is performed by an algorithm that corrects only erasure correction, and Nr ≦ deg Sε (z ) <(D-1) / 2 + (Nr /
When the relationship of 2) is established, a signal indicating that correction is impossible is output, and it is entrusted to suboptimal measures such as data interpolation, and deg Sε (z) ≧ (d−1) / 2 + (Nr / 2) When Nr ≦ deg Sε (z), an error correction method is characterized in that an error position is obtained by using the Euclidean mutual division method and the error and erasure are corrected. 2. The error correction method according to claim 1, wherein the double coding is coding using a product code. 3. A syndrome polynomial is obtained from the received word, the coefficient of the syndrome polynomial is stored in a memory, and an error position is calculated between the coefficient and the coefficient of the Goppa polynomial Z ^d-1 by using an iterative algorithm by the Euclidean algorithm. , In the error correction method that calculates the error numerical value and corrects the error by this, in the mode of correcting erasure and error, use the same syndrome polynomial as the syndrome polynomial in the case of errors only decoding (Errors only decoding). Error correction method characterized by. 4. A memory for storing a modified syndrome or a coefficient of a syndrome and a memory for storing a coefficient of a Goppa polynomial Z ^d-1 as an initial value, and each coefficient is sequentially read out based on the Euclidean mutual division method, and a Galois operation is performed. Division, and in parallel with this, store the polynomial degree data in the degree latch circuit, subtract the polynomial degrees from each other with the arithmetic operation unit, and prepare for the next division by the Galois operation unit. Swap the polynomials in the next division. Then, the division is sequentially executed, and thus the basic equation is calculated using the arithmetic operation unit, the memory, the register and the order latch circuit: η (z) = σε (z) Sε (z) + [σe (z) φε
(Z) + φ (z)] g (z) and iterative decoding, the degree of the numerical polynomial η (z) and the position polynomial σ obtained by the Euclidean decoding decoding device
An error correction method characterized in that when deg η (z) <deg σ (z) does not hold between the orders of (z), the error is not corrected and the error is detected and the correction is impossible. 5. When the number of disappearances is set to Nr, the syndrome S (z) created from the received word is lost at least a plurality of times. ● (When j = 0, σε (z) = 1 is calculated) and determination is made by using Euclidean algorithm only when deg Sε (z) ≧ (d−1) / 2 + Nr / 2 Error correction method with routine. 6. A syndrome polynomial Sε modified by a memory for accumulating the coefficients of the syndrome polynomial S (z), an erasure register indicating an erasure position, and an erasure control circuit.
When calculating the coefficient of (z), the coefficient of S (z) is first copied, and then the disappearance position α _i1 of the disappearance having the lowest reliability is set to the form of (Z−α _i1 ) and the remaining Sε
(Z) and Galois arithmetic unit to calculate Sε (z) = Sε
(Z) × (Z−α _i2 ) and the result is RA in Sε (z)
The loss position α _i2 of the loss with the next lowest reliability stored in M (Z
-Α _i2 ) is multiplied by a Galois operator to obtain Sε (z) = S
ε (z) × (Z−α _i1 ), and in this way Sε
An error correction method characterized in that (z) is updated, and at most d-1 erasure positions are sequentially multiplied in this way, and the coefficient of Sε (z) is stored in the RAM. 7. A Galois field GF (2 ^m ) code with coefficients σ ₀ , σ ₁ , σ ₂ ,. ． ． When the code length N is shortened (that is, when N <2 ^m −1) in the chain search circuit in which the elements of the Galois field are successively generated by giving σ _t and the root of σ (z) = 0 is obtained, A position where the calculated error position does not exist (that is, 2 ^m -2 from the address N)
If there is a root indicating the address), the error correction method leaves only uncorrectable detection and does not correct the error, but leaves it to the next best measure such as data interpolation. 8. The code of the Galois field GF (2 ^m ) and the coefficients σ ₀ , σ ₁ , σ ₂ ,. ． ． The value of the order latch memory for accumulating the order of σ (z) in the chain search circuit for generating the elements of the Galois field one after another by giving σ _t and finding the root of σ (z) = 0 and the error calculated by the chain search circuit Detects that the numbers do not match and does not correct,
An error correction method that leaves it uncorrectable and entrusts it with suboptimal measures such as data interpolation. 9. An error correction method of a decoding method for obtaining an error locator polynomial and an error value polynomial from the syndrome polynomial S (z) and the Goppa polynomial Z ^d-1 using the Euclidean mutual division method when the minimum distance d of the code is set. And the received symbols input to the decoder are 1 in ascending order of reliability.
Second, second ,. ． ． d-1th order is performed, and Nr symbols (Nr is 0 ≦ Nr ≦ d
−1) erasure, and the erasure position polynomial σε
After obtaining (z), the modified syndrome polynomial is Sε
(Z) = σε (z) S (z) mod Z ^d−1 is calculated to calculate a modified syndrome polynomial and the number of erasures is changed from 0 to Nr in order to correct errors and erasures. The vanishing position polynomial σε (z) is calculated, and the modified syndrome Sε (z) is calculated as Sε (z) = σε (z) S (z) m.
calculated from od Z ^d- 1 and the degree deg Sε (z) of the modified syndrome Sε (z)
Between the minimum distance d and the number of disappearances Nr, (a) Nr ≦ deg
Sε (z) and deg Sε (z) ≧ (d−1) / 2
When + Nr / 2 holds, the error locator polynomial and numerical polynomial are obtained by the Euclidean mutual aid method to correct the error and decode the data. When (b) Nr> deg Sε (z) holds, only the erasure is decoded. (C) otherwise, ie, Nr ≦ deg Sε (z) and de
When g Sε (z) <(d−1) / 2 + Nr / 2, the number of erasures is sequentially changed and the corrected syndrome polynomial is calculated again, and the number of erasures at maximum Nr times is changed to correct the data error. , An error correction method in which the number of erasures is changed until the correction is completed to correct erasures or errors up to the number of erasures d-1. 10. In a method of performing double encoding such as a product code, the one which was not error-corrected because the syndrome was zero in the decoding process of the first code C1 was classified as class 0 reliability and single error. The corrected one is assigned the first-class reliability, the two-error corrected one is the second-class reliability, and the i-class error-corrected one is generally assigned the i-class reliability and the reliability. In a dual code decoding method in which information is transmitted as erasure when the second code is decoded and erasure error correction is performed, symbols for C2 decoding are β ₁ , β ₂ ,. ． ． , Β _{d-1 in order,} and the error correction method according to claim 9. 11. The error correction method according to claim 10, wherein the double encoding is encoding using a product code.