JPH0750420B2 - Power control device for digital circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to digital circuits, and more particularly to power saving devices for clocked digital circuits.

2. Description of the Prior Art Clocked digital circuits, for example microcomputer circuits consisting of a microcomputer and its associated peripheral integrated circuits (ICs), consume a relatively large amount of power. In applications where power consumption is important, it is desirable to reduce power consumption as much as possible. For example, it is desirable to reduce, if not completely, the power supplied to the microcomputer during the sleep mode of the microcomputer. Unfortunately, the microcomputer requires operating power along with the clock signal to wake up from sleep mode.

(Problems to be Solved by the Invention) Therefore, the known power-saving device for the digital circuit is arranged away from the microcomputer circuit.
However, arranging such a structure away from the microcomputer circuit cannot be used for a large amount of power-sensitive applications, for example, a battery-operated arithmetic unit. Therefore, there is a need for a power saving device that overcomes this disadvantage.

An object of the present invention is to provide a power saving device for a clock type digital circuit. More specifically, the present invention aims to provide an apparatus for a method of effectively reducing the power consumed by a microcomputer and its associated peripheral ICs.

(Means for Solving the Problem) The present invention solves the above-mentioned problems, and reduces the power consumption by eliminating the clock for the microcomputer while simultaneously supplying the peripheral circuit with the clock whose frequency is lowered during the sleep mode. Then, a power saving device for a microcomputer circuit is provided, which interrupts the sleep computer circuit to recover from the sleep mode.

(Embodiment) FIG. 1 shows a power-saving device for a microcomputer circuit. This device is a microcomputer (MPU) such as the Z80 available from Zilog Inc. and
It has a peripheral IC (PIC) 115 associated with the MPU 110. By using a typical Z80MPU, PIC115 can
It can be O, CTC, or SIO, which are available from Zilog.

MPU110 and PIC115 are address bus 116, data bus 11
7. IORQ / RD signal 118 and interrupt (INT) signal 119 are interconnected as usual. MPU clock signal 122
Although supplied to the MPU110, the peripheral clock signal 124 is the PIC115
Is supplied to.

The MPU clock signal 122 and the peripheral clock signal 124 are an integral part of the power saving device according to the present invention. These clock signals 122 and 124 are used by the control circuit 130 in combination with the pause signal 126 (supplied by the MPU 110) and the interrupt signal 119 (supplied by the PIC 115),
It becomes the MPU clock signal 122 and the peripheral clock signal 124 in the power saving apparatus of the present invention.

The control circuit 130 comprises a variety of conventional digital circuits that are interconnected and operate in the novel manner of the present invention.
These conventional digital circuits include a clock generator 132,
4-bit shift register 134, flip-flop 136,
There is a data selector 138, a (divide by 10) divider circuit 140, an AND gate 142, a NOR gate 144, and two inverters 146 and 148. During normal operation, the sleep line is in a binary high state (high), shift register 134 and flip-flop 136 are held in reset mode, and clock invalidation signal 150 is provided by flip-flop 136, The output of the clock generator 132 is passed through the AND gate 142. In this mode, the clock disable signal 150
The inactivity causes the data selector 138 to propagate the output of the clock generator 132 to the PIC 115. In this way, both MPU 110 and PIC 115 operate at full speed under normal operation.

The operation in the power saving mode according to the present invention is as follows. The MPU 110, as indicated by the pause signal 126,
Indicating the disabled state causes the interrupt signal 119 provided by the PIC 115 to be high (indicating no interrupts are present), releasing the shift register 134 and flip-flop 136 from reset mode. . From the next rising edge of the signal provided by clock generator 132, shift the logic "high" state at the SI input of shift register 134 to the first stage of the shift register. This shift in the shift register 134 is caused by the next three consecutive edges of the signal provided by the clock generator 132.
It continues until the logic "high" state at the input is shifted into the final stage of the shift register. At this point, a logic high state will appear at the SO output of the shift register. Referring again to the output of the clock generator 132, at the falling edge after the next rising edge, the data at the SO output of the shift register 134 is passed through the inverter 148 to the flip-flop 136.
Latched on. This causes the clock disable signal 150 to go low, which causes the MPU clock signal to become an AND gate.
It is prevented from being transmitted to MPU 110 through 142. The clock invalidation signal 150 transitioning to the "low" state selects channel A of the data selector 138 so that the divider circuit 140 can provide the output signal to the PIC 115. In this mode, MPU1
10 receives no clock signal, and the PIC 115 receives a clock signal at a frequency considerably lower than the frequency of the clock signal received during normal operation, that is, 1/10 of its normal speed. This significantly reduces the power consumed by the MPU. In addition, the PIC115 continues to operate at low speed, so it consumes considerably less power, but is still active,
An interrupt can be generated for the MPU 110 to get it out of the disable (sleep) mode.

To cause PIC 115 to exit MPU 110 from the disabled state, interrupt signal 119 is provided to shift register 134 and flip-flop 136 via MPU 110 and inverter 146 and NOR gate 144. This allows the shift register 134
And flip-flop 136 is held in reset mode again. As a result, the clock disable signal 150 transitions to "high" and the MPU 110 is in its normal active state.
Allows to receive MPU clock and data selector 1
38 is switched to the channel B input, which transfers the output of the clock generator 132 to the PIC115. From this point on, the MPU 110 processes the interrupt request provided by the PUC 115.

(Advantages of the Invention) According to the present invention as described above, the power consumption in a digital circuit can be significantly reduced.

Further, the digital circuit in the sleep mode can be easily restored.

[Brief description of drawings]

FIG. 1 is a block diagram of a power saving apparatus which is an embodiment of the present invention. 110 …… MPU, 115 …… PIC, 130 …… control circuit, 132 …… clock generator, 134 …… shift register, 136 …… flip-flop, 138 …… data selector

Claims (5)

[Claims] 1. A control means (1) for generating an interrupt signal (119).
15), a processing means (110) for generating a pause signal (126), and a power control device for a digital circuit having a clock means (132) for generating a first clock signal of a predetermined first frequency, a) A second clock signal (122) having an input for receiving the first clock signal and an output and having a predetermined first frequency is generated and supplied to the processing means, and the second clock signal (122) is provided in response to the pause signal. 2) invalidating means (134, 136, 144, 146) for invalidating the second clock signal and validating the second clock signal in response to the interrupt signal; and b) an input for receiving the first clock signal, and an output. , Generating a third clock signal (124) of the predetermined first frequency and supplying the third clock signal (124) to the control means, and pre-determining the predetermined first frequency of the third clock signal in response to the pause signal. A step-down means (138, 140) for stepping down to a predetermined second frequency and thereafter increasing the predetermined second frequency of the third clock signal to the predetermined first frequency in response to the interrupt signal, The processing means consumes substantially no power when the second clock signal is disabled, and the control when the predetermined first frequency of the third clock signal is stepped down to the predetermined second frequency. A power controller for a digital circuit, characterized in that the means consumes less power. 2. The control means (115) is a peripheral input / input.
2. An output integrated circuit, comprising:
A power control device for a digital circuit as described. 3. The power control apparatus for digital circuits according to claim 1, wherein said processing means (110) is a microprocessor. 4. The power control device for a digital circuit according to claim 1, wherein the step-down means (138, 140) comprises a frequency divider. 5. The power control device for a digital circuit according to claim 1, wherein the predetermined second frequency is 1/10 of the predetermined first frequency.