JPH07502130A - Color-enhanced display systems and how to use them - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Color-enhanced display systems and how to use them References relevant to this application The present invention is based on U.S. Patent Application No. 077,690,531, filed April 23, 1991. This is a partial continuation application of No. ``Video display system and its method of use'', and it is U.S. Patent Application No. 077,616,178, filed November 19, 1990 This is a continuation-in-part application for "Visual Signal Projection System and Method of Using the Same," filed in 1990. U.S. Patent Application No. 077586.506, filed on September 21, ``High Speed Color Display'' This is a continuation-in-part application for ``Spray System and Method of Use'' filed in June 1990. U.S. Patent Application No. 077546,283 filed on May 29th, ``Stackable Display This is a continuation-in-part application entitled “Structure of Ipanel System and Method for Manufacturing the Same”, filed in 1999. U.S. Patent Application No. 077506,429 filed April 9, 2013 [Stackable Disc] This is a partial continuation application for ``Structure of a play panel system and its manufacturing method'', and it is filed under 1. U.S. Patent Application No. 077506,621, filed on April 9, 1990, entitled This is a partial continuation application for ``Structure of display panel system and its manufacturing method,'' and No. 077,472,668 filed on January 30, 1990. "Crystal display panel system and its manufacturing method" and published on July 21, 1988. No. 077,222,144, “Gray Gradation for Video Displays” System” (currently abandoned) and the U.S. filed on April 11, 1990. Continuing patent application No. 077507,630 “Gray gradation system for video display” ( This is a continuation-in-part of U.S. Pat. No. 5,062°001). The aforementioned patent applications are all are included in this application.

Technical field TECHNICAL FIELD This invention relates generally to video display systems and methods of using the same. . In particular, the present invention is directed to an apparatus capable of projecting a large color image consisting of a television signal, and its use. Usage There are various types of full-color video display systems up to now.

Full-color display technology includes television monitors and direct-view videos. .

Although this method is satisfactory to some extent, video and TV using cathode ray tubes monitors have a limited screen size. Moreover, such a system Since direct-view monitors are expensive, manufacturing costs are also high.

Therefore, you can enjoy full coverage of large TV images without using expensive large screen monitors. It is desirable to create new and advanced systems that can be displayed on large screens.

Using rear projection system for red, green and blue images to enlarge the limited screen A method of projecting images from the rear onto a large transparent screen also appeared. This method is satisfactory to some extent. However, it is still expensive to manufacture and requires carrying a large display device. This is inconvenient because you have to do so.

Additionally, some of the light brightness is lost before reaching the screen, limiting image sharpness. It's coming.

Large color images resulting from relatively inexpensive and easily transported television signals are therefore A new video display system that can display images is desired.

Another method to solve blurred images projected on a large screen is to directly front It is a projection system. This front projection system is similar to the rear projection system, but It consists in projecting different images onto a large reflective screen. This method also It is satisfactory, but it must be properly focused to brighten the image. In addition, the projector must be fixed at an appropriate distance from the screen.

Therefore, it is possible to project images with relatively high luminance onto a large screen without fixing the projector. A system that can produce lean images is needed.

Another method to resolve image blurring is high-speed active matrix panels is used in conjunction with an overhead projector. such a fast Matrix panel provides full color display with thousands of bright colors It is possible to do so. Such a large number of colors are in the LCD display Advanced technology that can selectively adjust each individual pixel to create multiple levels of enhancement This is possible only through duty cycle techniques. Such a duty cycle Although this technique is satisfactory for high-speed active matrix LCD panels, it Less precise means are considered sufficient for web matrix panels. Therefore , low-speed LCD display panels can be manufactured without using too sophisticated duty cycle techniques. It is extremely necessary to create thousands of bright colors in a single color.

Attempts to retrieve large numbers of colors using active matrix displays It is disclosed in National Patent No. 077690,513. According to it, low-speed actuators The five-matrix panel has over 24,000 cells per synthetic building cell group. Selected and charged to create different color gradations to clarify composite pixels A control device with a patterned circuit forming pixel molecular groups It's confusing. Such a composite group technique is a slow active matrix panel. However, many different gradation levels can be used to further improve the color resolution of images. It is desired to produce a bell.

Disclosure of the invention The primary purpose of the present invention is to develop a new and advanced video system that creates large images from conventional signals. Our goal is to provide display systems.

Another object of the invention is to provide a new and improved visual display that is relatively inexpensive to manufacture and easy to project. to provide video display systems.

Yet another object of the present invention is to provide a plurality of discrete color gradations with relatively high visibility. Provides a new and advanced video display system capable of producing It's about doing.

In summary, the objectives mentioned above and more are Something suitable for placing on top of a regular film projector, such as an LCD active If you are using a relatively slow display panel, such as a matrix panel, to display your TV's video A variety of color displays can be created using the interface unit by connecting to an optical signal transmitter. This is achieved by providing a spray system. this display panel is a pixel molecule map consisting of individual pixel molecules containing subpixel molecule groups. Contains Trix. Each subpixel molecule responds to a television video signal. to create at least N gradations of one color. In this interface unit, X is N. If the size is even larger, individual colors can create multiple x+vi levels. It is equipped with a counting circuit that operates each pixel. −The set of pattern circuits is counted. It works with a circuit to convert the television video signal into N shades of color from one of multiple pigments of each individual color. Binary signal groups that manipulate sub-pixel molecules individually so that they can be splayed It makes it possible to hatch. The counting and pattern circuits are low speed active matrices. Group the vixel molecules in the xpanel, e.g. - group with 4 pixel molecules. Can be synthesized. For this, a 4-vixel molecule group is 185.00 Zero or more different color shades can be displayed by composite pixel groups. to identify a single composite pixel group that is charged up to 1 out of 8 steps. Connected.

A regular matrix such as the 640 x 480 matrix array found in Format timing to form the video signal so that it can be displayed in an array The foregoing and other objects, features and means of obtaining the present invention by employing a generator are as follows: may be better understood and clarified by reference to the specific representations and accompanying drawings. Let's be white.

Figure 1 shows an overhead sylloscope driven by a television signal and the current invention. This is a picture and diagram of a television projection system built based on this.

FIG. 2 shows a drawing of this device and the arrangement of FIG.

FIG. 3 is an exploded view of the display driving device shown in FIG. 1. As shown in FIG.

FIG. 4 is an exploded view of the color enhancement interface unit of FIG. 3.

FIG. 5 shows the format timing of the color enhancement interface control device of FIG. 3. FIG. 2 is an exploded structural view of the generator.

FIG. 5A is an exploded view of the color enhancement device of FIG. 4. FIG.

FIG. 5B is an exploded diagram illustrating the counting logic of the color enhancement device of FIG. 5A.

Figure 6 shows the operation of the microprocessor in the display driving device shown in Figure 1. FIG.

7A-B illustrate the operation of the format processor of the color enhancement control device of FIG. FIG.

FIG. 8 shows the matrix layout created by the format timing generator of FIG. This is a diagrammatic representation of the columns.

FIG. 98 is a diagram useful in understanding the operation of the format timing generator of FIG. FIG. 3 is a plan view of a format timing generator.

FIG. 9B is a diagram useful in understanding the operation of the format timing generator of FIG. FIG. 2 is a cross-sectional view of a format timing generator.

FIG. 10 is a flow diagram of the shutdown firmware of the color enhancement controller of FIG. 3.

FIG. 11 is an exploded view of the video control device of FIG. 4.

Figure 12 shows the pixel molecular groups in the active matrix panel of Figure 4. This is a diagram showing the process.

FIG. 13 shows the pixel molecule group in the active matrix panel 16 of FIG. Diagram of the loop, showing antiphase.

Best Mode for Accomplishing the Invention The details of the invention may be summarized in the following summary.

A. General description of the system (Figure 1) A.1. Overhead projector - (Figure 2) A, 2. Active Matri Box panel (Figure 3) A, 3. Interface unit (Figure 3) A, 3.1 ．． Signal conversion device (Figure 3) B. Color enhancement effect C0 interface control device details C91, format timing generator (Figure 5) C,1,1, microprocessor Function of C, 1, 2, format timing generator (Fig. 6) , Figure 7B) C12, memory control device (Figure 11) C03, video control device (Figure 11) C, 3, 1, Program cutoff (Figure 41 Figure 11) D, Detailed description of color enhancement device ri, 1. 2x2 pattern logic assembly.

D.1.1. 2x2 pattern logic formula and truth table, 2. 1X2 pattern Logic assembly D, 1, 2. IX2 pattern logic formula and truth table A, system General description of the system The related drawings, particularly Figure 1, are based on the present invention and also include a very large golden drawing. Television signals used in video display systems capable of displaying images. A No. 1 projection system 10 is illustrated. Therefore, this system 10 Projection display system The method is adopted as follows.

As shown in FIG. 1, system 10 is conventional in construction as a video cassette. A television such as a video cassette recorder 20 using (not shown) A projection system 80 is employed over the signal generation source and over.

The video cassette recorder 20 is a conventional US video cassette recorder for converting television broadcast signals into images. It emits Television Standards Committee (NTSC) signals or European PAL signals.

System 10 typically receives a conventional television signal from video cassette recorder 20. It consists of a display driving unit 11 which converts the video signal into a video signal. this video The signal is a matrix liquid crystal display panel that produces a color image from the video signal. Display devices such as 16 thin transistor films can A hundred color shades can be displayed. This drive unit also Detailed information is provided in U.S. patent application Ser. No. 071,586.506, which is also referenced in output from the personal computer 21 using the video drive module 26 that can change the normal computer video signal.

In this regard, the drive unit 11 has a video interface unit 13. A color enhancement module connected to the cassette recorder 20 or video drive module 26. An interface controller 12 is included. The interface controller 12 has a a format that serves to form a television signal that displays an image on display device 16; Built-in timing generator. The interface unit 13 has 13A and 1 3B are connected to recorder 2o and module 26 respectively with a pair of cables. There is.

In FIG. 12, each line and row of 240, 242, 244, 246, or 241, A composite pixel group arranged in columns or lines, such as 3,245,247 pixels. An active matrix panel 16 is shown illustrating the active matrix panel. composite pixel 300-305 are also roughly the same, so only the composite pixel 300 will be discussed here. This will be explained in detail.

If we look closely at the synthesized pixel 300 with reference to FIG. , 1, 2.3 identified synthetic pixel molecule groups 220, 225, 230, Consists of one 2x2 pixel molecular matrix divided into 231 is understood. 4-bixel molecular matrix.

Each pixel group has two lines or columns 240 and 242 and two columns each. It is composed of loops 241 and 243. The lines and columns of these pixel molecules are For example, a pixel group is defined as group 300.

As will be described in detail later, the interface controller 12 for color enhancement is in group 3. Many active matrix pixels within an individual composite pixel group such as 00 chromaticity to form a composite pixel group into one selected from the xel molecules It plays the role of assigning standards. In this regard, as well shown in Figure 12, , the data input to pixel molecule 220 is input to the pixel molecule at line 240. Used to define color change standards. A pixel molecule such as pixel molecule 220 has a total of three sub-vixel molecules, one for each of the primary colors red, green, and blue ( (not shown). Therefore, in such a combination, group 3 pixel molecules 220, 225, 230, 231 in each group such as 00 Each individual pixel molecule, such as You must understand that it will be loaded. In this way, among the synthetic groups 300 By selectively combining some of the pixel molecules such as the pixel molecules of Therefore, over 185,000 different color combinations can be created in the composite pixel 300. Jiru.

Here, the present invention will be ideally and concretely explained. The drive unit 11 is a video cassette Those skilled in the art will know that the video disc unit is connected to the recorder 20. A TV with a cutter 22, a video camera 24, a TV tuner 41, or an antenna 43A. It is accepted that a television signal generation source such as a television receiver 43 is used as shown in FIG. Easy to understand.

The red, green, and blue colors of the displayed image are A standard television lamp that displays images by converting them into analog signals that indicate color composition. Generate star scan. The interface control 12 for color enhancement is an interface controller 12 for color enhancement. It only controls the action of connecting the face unit 13 to the display device 16. However, a very large number of colors can be displayed on the active matrix panel 16. It also performs the function of quantizing ordinary RGB analog signals. This is clearly shown in Figure 1. As shown, color enhancement interface controller 12 is connected by cable 25. connected to an active matrix panel.

The video cassette recorder 2o used here records video from the TV. When viewed on a video cassette, any regular video cassette that can generate a standard NTSC signal It can also be a tracer. Video cassette recorder 2o drives line broadcast signals. CATV cable 41A connected to the moving unit or connected to a standard TV antenna. can do. Video cassette recorder 2o and overhead projector The display device 16, which cooperates with the computer system 80, is capable of displaying any television image. Video recordings can also be viewed as large projected images.

The over rad projection device 80 will be described in detail with reference to FIGS. 1 and 2. and supports an active matrix panel 16 having the purpose of image projection. A flat, transparent projection surface 82 is usually included in this device 8o. over hella The projection device 8o includes a light emitting electron tube for passing light into the panel 16, and FIG. 83 of the present invention.

In order to standardize the light generated by the electron tube and the reflector 83 on the panel, a standard Fresner lens is used. A lens 85 is placed within an overhead projector system 80.

In this regard, the optical assembly 88 may be configured to transmit light passing through the panel 16 or to a projection screen or other suitable device. This makes it possible to focus on the visible plane.

A preferred state of the invention is that Frassnel lenses 85 and 87 are disposed above panel 16. However, those skilled in the art will understand that the lens 8 is spaced apart from the panel 16. 5 and 87 may be placed in a case (not shown). be understood. In this regard, the television signal transmission system 10 and its The method of use is to attach a suitable visible surface using an easily installed and relatively inexpensive commercially available device. Easily and conveniently create full-color images using a thin film of passive matrix The transistor LCD panel 16 is connected to a video cassette cartridge (not shown). primary colors (red, green, Blue) selected number of pixels in a 640 x 480 pixel array in the distribution state It contains a vixel matrix array that generates vixel molecules.

Those skilled in the art will understand that a television video image is a television video image from a broadcast received by a television receiver. signal or directly connected to the interface unit 13 as shown in Figure 3 It will be understood that the signal is from a television camera. This active tomato Rixpanel 16 is incorporated herein by reference to U.S. Patent Application No. 077586, No. 506. is described in more detail.

Table ■ As best shown in FIGS. 1 and 3, the system 10 supports NTSC and VGA graphics. Can be used with any conventional television signal source that produces video images such as It is used like that. Table ■ shows the NTSC frequency for two normal video signal sources Details are shown below. As will be explained in more detail later, the system 10 An active matrix with a 640 x 480 pixel array into a reformatted signal that can drive the spacer panel 16.

FIG. 8 illustrates a typical representation of the current system 10. In this regard, an illustration The typical 525 line NTSC display format is shown in 801 for A 640 x 480 pixel array is shown. NTSC signal is 80 It occupies the display area indicated by 2 and has a combined frequency of 30Hz, 525 lines. It consists of two (7) 60H2,262,5 lines forming video information. pa Since the vertical resolution of channel 16 is lower than the resolution obtained from the NTSC signal, the current Stem 1o effectively converts the NTSC display format to the vertical resolution of panel 16, which is 480 lines. match.

Controller 12 ignores the first 22 horizontal lines and 23 horizontal lines within the video information frame. As a result, 480 effective lines (525 - 22 - 23 = 480) were created. The NTSC signal is formed by extracting the NTSC signal. This ignores the line at the top of the eye. Consists of a plethora of invisible scan lines and a mostly useless bottom of the display image. Therefore, it is an effective method.

The width of the NTSC screen is adapted to the 640 pixel width used by panel 16. or formatted.

In this regard, controller 12 controls the sample frequency of the video signal, as will be explained in more detail below. Adjust.

A.3 Interface unit Here, the interface unit 13 will be explained in more detail with reference to FIG. Normally, the interface unit 13 converts the NTSC television signal into a video cassette player. converts the recorder 2o into an analog RGB signal suitable for driving the controller 12. A signal converter 32 is provided. NTSC television signal is signaled by conductor 2OA It enters the input stage of converter 32. The issue is already there as well shown in Figure 3. It is connected to the video drive module 26.

In this regard, the video drive module 26 in the personal computer 21 Five output signals red, green, blue, horizontal sync (H3YNC) and vertical sync (VSYN) C) and having - sets of electrical conductors 26A-E, respectively, on cable 13B. is connected to the interface unit 13.

The user receives input from the video cassette recorder 2o and the video drive module 26. The interface unit 13 has an analog controller so that one signal can be selected from among the signals. It includes a multiplex unit 34 and a microprocessor 36. analog The output signal from the signal converter 32 or the video driver The output signal from the motion module 26 is passed to the color enhancement interface controller 12. It is an ordinary multiplexer. The microprocessor-36 Color-enhanced interface for source standards (VGA graphics, NTSC, PAL, etc.) Determine which device to connect to the face controller 12. Regarding this, the microprocessor The circuit 36 connects a single source reference signal to the controller 12. These signals are One set of electrical conductors for each analog multiplex unit 34 and controller 12. 34A-E. Once the microprocessor-36 is the controller 12, the microprocessor 36 becomes active. The appropriate sample frequency and power required to drive the matrix unit 16 the correct format data and pixel position formats. A command is generated on command/data line 36A (FIG. 5). microprocessor The sensor 36 also receives input signals from the signal converter 32 or the video drive module 26. multiplexer to receive either of the input signals from the controller 12 and pass it to the controller 12. A control signal (MUX C0NTR0L) for switching the unit 34 is generated. child The control signal (MIX C0NTR0L) is the multiplex unit on conductor 36B. Connected to knit 34. The interface unit 13 is also a remote red Receiving infrared signals from an external transmitter unit (not shown) It includes an infrared receiver 38 with a scepter 39.

In this regard, the user can microprocessor 36 to locate different types of video source signals. An infrared transmitter unit that generates a signal may be activated. this infrared Line receiver 38 has an output connected to microprocessor 36 on electrical conductor 38A. This is a normal infrared receiver unit.

Interface to amplify low-level audio signals accompanying video source signals. Base unit 13 can also be connected to a regular speaker, such as speaker 33A. The audio amplifier 33 includes an output jack.

The audio amplifier 33 is manufactured and sold by Signetics. It is an ordinary product like the model TDA1013B, manufactured by SignetiC. “Linear Data Manual” Volume 1 (1989) No. 7-20 Details are given on page 7.

A.3.1. Signal converter The signal converter 32 will be described in detail with reference to FIG. Motorola Linear/Interface Dev ices Data Book pages 9 to 183 to pages 9 to 1°90 and M otorola Application note AN1019D Types well known to those skilled in the art such as the TDA 3330 unit be. Other types of conversion from PAL or SECAM signals to RGB signals The utensils are also well known. For example, PAL-8ECAM-NTsc/RGB controller Bination converter is SGS THOMSON Video IC’5Data Phoenix, Alisina, listed on pages 1221-1227 of the Book 1000 East Bell Road (7) From SGS THOMSON Co., Ltd. Part number TEA 5640C can be purchased. The signal converter 32 is well known. Since this has already been done, we will not discuss it in detail here. The output signal of the signal converter 32 is transmitted through a set of electrical conductors. 32A-E are connected to the analog multiplex unit 34 on the red, green, Blue, carries horizontal tuning (H3YNC) and vertical tuning (VSYNC), respectively.

B. Color enhancement effect Regarding the color enhancement effect according to the present invention, the interface controller 12 As shown in FIGS. 3 and 4, the active matrix connected between the space panel 16 and the output stage of the analog multiplex unit 34. It is. In this regard, red, green, blue, horizontal sync (H6YNC) and vertical sync (V SYNC)+7)- connected to the input side of the controller 12 through conductors 34A-E. It is.

As best shown in FIG. 4, the color enhancement controller 12 is typically an active matrix A controller 18 for controlling video data supplied to the box panel 16 and an interface. a set of color intensifiers that quantize the video data supplied by the phase unit 13; control units 40, 42, 44 and quantized video data storage and withdrawal. storage controller 50 to control and format the video data to be displayed. It consists of a format timing generator 45 that is useful for. Memory Controller 5o is substantially similar to the controller described in U.S. Patent Application No. 077,616,178. Since they are similar, we will format them here as color enhancement units 40, 42, and 44. Only the timing generator 45 will be described in detail.

Considering the color enhancement units 40, 42, and 44 with reference to FIG. Since units 4o and 42.44 are almost similar to each other, emphasis unit 4o I will only explain about.

As best shown in FIGS. 4 and 5A, color enhancement unit 40 typically uses RGB An analog converter that converts the red part of a string of analog signals into a 6-bit digital signal. A digital converter 51 and a counting circuit array 52 for processing and storing digital signals. It is composed of

The counting circuit array 52 typically functions for each individual pixel within a composite pixel group. A counting unit that processes 6-bit digital data into 4-bit gradation levels Contains cuts. Active matrix panel as shown in Figure 12 The 16 pixel molecules are commonly designated 300, such as the subpixel molecule 220. The pixels are arranged in groups of four pixel molecules in a 2×2 array. normal a The active matrix panel 16 consists of three sub-pixel molecules of red, blue and green. It uses a set of pixel molecules. In Figure 12, among the three subpixel molecules, Only one is illustrated, and that is the two subpixel molecules in each remaining triplet. is known to operate in the same way under the control of color enhancement units 42 and 44. That's why. Furthermore, each sub-pixel molecule has a corresponding color enhancement unit. It is controlled by these 3-bit signals. Each 3-bit signal has 8 gradations in a single color will occur.

The counting unit 53 stores four bits of data representing 64 different gradations. are individually assigned to the sub-pixel molecules of each composite pixel of 0, 1.2.3. It is converted into four groups of up to 16 gradations constructed by applying

For example, if 6 bits of human data are quantized into 43 gradation levels, the counting unit The bit 53 converts the 6-bit level signal into a set of 0, 1, 2, and 3 (see Figure 12). ) into a 4-bit signal corresponding to one of the sub-pixel molecules. About this and its 4-bit signal is - one of the sub-pixel molecules during the display frame. Used to control one. At level 43, each 4-bit signal is different. 11, 11, 10, and 11 levels respectively in the display frame. is displayed corresponding to sub-pixel molecules 220.225.230.231.

As will be clear to those skilled in the art, each sub-pixel molecule can be activated up to eight shades; , more than 8 gray levels are possible for such active matrix panels Not.

Thus, according to the invention, pattern logic unit 59 divides the 4-bit signal into each sub-pixel. converts it into a 3-bit signal that controls the cell molecule. Therefore, a 3-bit signal is one The sub-pixel molecules serve to create only 8 gradations. However, from the frame The frame modulating a particular pixel between two adjacent chromaticities into a frame is 15 A gradation of color can be produced. In other words, pixels under a certain color saturation Converting between two specific levels, e.g. 4.5, for each frame can display gray levels between 4 and 5.

For example, for level 43, the 4 bit levels of 11, 11, 10, and 11 are 4 of the synthesized pixels under the frame-to-frame condition for 11 and 10. 5.5.5.5 and 5.5.4.5 to charge the sub-pixels. this 1x2 pattern logic 55 frames each subpixel between chroma levels 5 and 4. It modulates, that is, gradates the composite pixel image. As a result, the gradation measurement is Used to obtain more gray levels required from synthesized pixel molecules. Ru.

Each composite pixel provides a total of 64 levels to the third possible power level. It should be logically understood that there are 64 shades of light and shade for each of the primary colors: blue, green, and blue. It is. However, the combination of different patterns in one composite pixel is Bell creates images that are perceived in the same way, resulting in many extra situations. Yo Therefore, in the practical model of the system of the present invention, due to this extra Of the 64 combination levels, only 57 are combined by composite pixels for individual colors. It is made. Each pixel molecule in a composite pixel has three subpixel molecules, e.g. For example, it contains one for each primary color red, green, and blue, so − composite pixels are displayed. The total number of possible colors is 573 or 185,193 colors.

The counting array 52 also includes a buffer unit for temporarily storing grayscale signals. 55 and a bitmap memory unit 57.

The counting unit 53 will be explained with reference to FIG. 5B. The data digitized by the analog-to-digital converter 51 is temporarily converted into The buffer unit 102A stores 6-bit digital data into 4-bit It includes a 2.times.2 pattern logic unit 55 for gradating to the original tone code. or, The 2×2 pattern logic unit 110 temporarily converts the video data into a bitmap format. buffer unit l-102A for storing or receiving data in memory 57. It is connected between the output side and the input end of the output buffer unit 55.

Enhancement unit 40 also activates each vixel molecule to form video data. is connected between the bitmap memory 57 and the video controller 18.

Buffer 55 and bitmap memory 57 are both described in U.S. Patent Application No. 077,616. Since it is very similar to the corresponding unit described in more detail in , 178, The above will not be described in detail.

For the purpose of gradating the output data to the active matrix panel 16, the emphasis unit is Knit 4o further includes a pattern reversal circuit, generally indicated at 103. child In this regard, the pattern reversal circuit 103 is configured to convert synthetic pixels such as synthetic pixel 300 into Static pattern dynamic by reversing the internal pattern arrangement every frame Details of C interface control device that creates gradation C01, format timing generator As described later, when the device is operating, 2× The two-pattern logic unit 110 generates a synthetic color scheme for increasing the displayable gradations. 1x2 pattern logic unit combining video pixel molecular signals to form cells The input video data is quantized and encoded for processing by the TS 59.

In this regard, a 2x2 pattern logic unit 110 is located at each vixel molecule. The two least important bits are removed and the six most important bits are backed up. The data in the bitmap memory 57 is received by the filer 102A. Reduce or quantize the amount of data stored in. Regarding this, the data is received by buffer 102A and digitized by 2×2 logic unit 110. 4 bits received by the output buffer 55 as signal R3°-RO' output signal is generated.

Now, the format timing generator 45 shown in FIGS. 4 and 5 will be explained in detail. Specifically, format timing generator 45 is typically stored within controller 12. programmable counter array 46 and controller 12 to facilitate the formation of video data. Determine the appropriate sample rate depending on the type of video signal connected, and , a programmable jumper to facilitate the probability of proper storage order of video data. It consists of a cell clock generator.

As best shown in Figure 5, the programmable pixel clock generator Phase comparator 66, low pass filter 67, voltage controlled oscillator 68 and program Ordinary phase locking including division by a programmable divider or N counter 69 It is a loop array. The programmable pixel clock generator 47 is an analog Using the reference clock signal connected from the output of the multiplex unit, ing. The reference signal is identified by H3YNC and is connected to phase comparator 66 on conductor 34D. is connected to the input of Video data are placed in emphasis units 40, 42, and 44 respectively. The output pixel clock signal PXCLK, which synchronizes the data storage, is controlled by a voltage. is derived from the output of oscillator 68. of the oscillator 68 controlled by the voltage. The sample rate is a function of the output of programmable divider 69, described below. Ru.

Referring to FIG. 5, the programmable divider 69 will be described in detail. Microphone to facilitate normal sample rate settings required for video data storage It is programmed by a microprocessor. The following example is instructive, but restrictive. The video standard connected to controller 12 has a sample rate of 14J33MH. NTSC standard requiring z or all display data lines Let's assume that there are 910 samples. In this case, the one-part component of 910 has the following structural formula: The desired sample rate must be created as shown in .

HSYNC rate (NTSC standard) = 15.750KHz Sample rate=15.750KHzX910=14.　333MHz As will be explained later, although 910 pixel samples are obtained for one line, 9 Among the 10 pixels, 270 pixels are excluded because they represent more data than necessary.

In this regard, if the video standard is VGA graphics, e.g. The split component is required to extract a sample rate of 25.175 MHz. . Regarding this, the HSYNC signal has a reference sample rate of 25.175 MHz. In order to extract it, it is 800 times 31.47KHz. Here again, sample 8 A number of 00 represents excess data, such as 160 samples.

Ignore these 160 samples, the first 80 and last 80 of each line. be done.

According to FIG. 9A, the horizontal synchronization signal (H3YNC data) is indicated by 901.

As mentioned above, the vixel positions that are ignored and not stored are the H3YNC data signal 90. 1 is about to reach a logic high level, it is displayed as an invalid data group 902 and its As soon as the H5YNC data signal 901 reaches a logic high level, the invalid data group It is displayed as a group 903. The position of the pixel between groups 902 and 903 is Represents a valid data group 904 displaying panel 16. I will explain further If so, the horizontal retrace period occurs at the point where the H3YNC data signal is high logic.

The programmable counter array 46 will be described in more detail with reference to FIG. Typically, this array 46 is the number of vertical retrace lines in the frame of displayed information. A retrace counter 73 that determines the valid picture of a single line of displayed information. Establish the number of cells and also the horizontal regression that exists between the lines of displayed information. A pixel counter 75 to help determine the number of line pixels and a a line counter 77 for assisting in determining the number of valid lines of the frame of information; A file that cooperates with the microprocessor 36 to facilitate the operation of the plurality of counters described above. It consists of a format processor or controller 79.

Format processor or controller 79 under control of microprocessor 36 accesses the display device 16 and formats it appropriately for display. to store video data in each color enhancement unit 40, 42, 44. The retrace counter 73, the pixel counter 75, and the line Load signals LOAD R, LOADP that allow loading the counter 77 2 and LOAD L. Load signals LOAD R, LOAD P.

and LOAD L are A matte controller 79, a retrace counter 73, a pixel counter 75, a line counter and the counter 77. Microprocessor-36, file a format controller 79, a programmable splitter 69, and a counter for each of the above. Connector 36A connected between interfaces 73, 75, 77 is of suitable format. Command instructions and predetermined format data to establish microprocessor-36.

Memory controller 50 includes the necessary components to store video information and control memory operations. A counter so that the format processor 79 can issue a control signal. 73, 75 and 77 respectively follow terminal count signals TCR, TCP and TCL. - is fed to the matte processor 79. The terminal count signal is connected to conductors 73A and 75. B and 77B, respectively, to the processor 79.

The format processor 79 allows the memory controller 5o to input all even memory addresses. All even field lines of the response are stored in bitmap memory, and the odd field lines are stored in bitmap memory. Allow field lines to be stored in odd memory addresses. video Storing the information in this manner allows the video information to be displayed on the display device 16. An emphasis unit 40.4 for generating vertical lines of resolution 480 used for 2. Retrieve from bitmap memory of concatenated intersecting line format consisting of 44 make it possible to

During operation of the microprocessor, the microprocessor 36 determines the video line to be displayed and connects conductor 3 by command to the appropriate split. to the programmable divider 69 through a command/data line signal on 6A. Send it in. The operation of the microprocessor-36 is performed by the microprocessor-36. Detailed description with reference to the flow diagram in Figure 6 showing the steps carried out. do.

Referring to the flowchart of FIG. 6, when power is manually applied to the drive unit 11, The configuration program 600 begins with a start instruction 601 and a differential instruction box 603. default to the desired type of video signal source, e.g. NTSC, PAL, Set to VGA graphics, etc. After completing the default settings, The program is currently running on the analog multiplex unit 3 on the microprocessor. Proceed to decision instructions 605 to determine whether an H3YNC signal is being received from 4. . If no signal is received, the program will send instruction box 607 to analog Multiplex control signal MUX C0NTR0L from other video signal sources Switch HSYNC and VSYNC signals to connect to microprocessor-36 I can do it. After the MIX C0NTR0L signal is activated, the program returns to HS Whether YNC is being received from the next selected or capable source. The process returns to the determination instruction 605 to determine whether or not. The above processing is a video given the function Repeat until the signal source starts sending video synchronization information (HSYNC, VSYNC) It will be done.

If it is determined that the HSYNC signal is present at the decision point, the program branches to instruction 612 and causes microprocessor 36 to output HSYNC and vsYNc. Analyze the period and polarity of each signal. After instructions 612 are carried out, the program The system is microprocessor-3, which uses standard comparison techniques to meet strict video signal standards. 6, proceed to instruction 614. Once the video signal standard has been determined, Once the program is configured, the appropriate sample rate and format count data will be flushed. A programmable divider 69 and a programmable Proceed to instructions 616 forming the counter array 46 of the programmable counters. Regarding this As will be explained in detail later, the format processor 79 is a microprocessor on the 36A line. The format data provided by processor 36 is stored in counter 73.75. ．． 77, the LOADR signal, LOADP signal, and Make the LOAD L signal functional. Once the programmable divider 69 Once the programmable counter array 46 is formed, the program can be executed by the user. The process advances to decision instruction 618 to determine whether the video criteria have been changed. If the video standards change If not, the program remains at instruction 618 until the video signal source changes. I'm waiting. When the video signal source changes, the program changes the H3YNC signal. Proceed to decision instruction 620 which determines whether the video signal is coming from a source.

If the H3YNC signal is present, the program goes to instruction 612 and Proceed to. If the HSYNC signal is not present, the program executes instruction 620. The process then proceeds to decision instruction 605 and then proceeds as described above.

C, 1, 2, Format timing generator path 1 The operation of the format controller 79 will be described in detail with reference to FIGS. 7A and 7B. Fo - The matte control controls the various bitmap notes in the emphasis unit 40, 42, 44. In order to properly control the video data format in which the video is saved, the first step is to Processor 36 must determine: (1) Number of vertical blanking lines required for display information (2) Information that can be displayed Number of valid or displayable lines in any frame (3) Number of horizontal blanking pixels between each splayable line (4) Valid or displayable information within each line of displayable information. H3YNC and VSYNC signals created by the number of pixels that can be generated by the video signal source as well as each of the counters 73, 75, 77 to achieve proper format. A microprocessor is used to generate the appropriate counter array 46 data to be stored in the microprocessor. Processor 36 determines the type of signal from the video.

The following table shows the reference count information required to convert between VGA and NTSC signals. are doing.

■Table Once the microprocessor 36 determines the type of signal from the video, the The microprocessor 36 has a format utilized by the counter array 46. Send commands and format data.

Referring to FIGS. 7, 7A, and 7B, format processor 79 may form or Immediately after receiving the format command, start the format program 700. do.

The format program 700 starts with a start instruction 701, and the video source position of decision instruction 703 to determine whether the VSYNC signal is present. Proceed to position. If the VSYNC signal is not present, the program determines 703 Wait at the position. When the VSYNC signal occurs, the program to reset the vertical retrace cycle or start a new frame. Proceed to instruction box 702. Then the program checks the presence of H3YNC signal Proceed to decision box 705 to set the value. If the HSYNC signal is not present , the program waits at box 705.

When the f(SYNC signal is generated, the program increases the line counter 77. Proceed to instruction box 707 to increase the size.

After line counter 77 has been incremented, the program has generated a valid number of retrace lines. Proceed to decision instruction 708 to determine whether. If a valid number of retrace lines has not occurred If so, the program returns to decision box 705 and proceeds as previously described. child For this, the first 22 horizontal lines of data are shown in Figures 8 and 9. It should be understood that it will be abandoned. If a valid number of retraces occur, the Gram proceeds to instruction 709 to reset line counter 77. Once, When the in-counter 77 is set, the program will start with the first 480 lines to be stored. Proceed to instruction 710 to start a horizontal retrace cycle that produces a valid line. So The program then proceeds to decision instruction 711 to wait for the next H5YNC signal.

If there is no H3YNC signal, the program waits at the position of decision instruction 711. Ru. When the H3YNC signal occurs, the program increments the pixel counter 75. Proceed to instruction 713 to do so. Then the program generates a valid number of retrace pixels. Proceed to decision instruction 7.15 (FIG. 7B) to determine whether the change was made. If the result of a significant number If no line vixel occurs, the program returns to instruction 713 (FIG. 7A) and performs the previously described function. Continue performing Noh. If a significant number of retrace pixels occur, the program Valid video data is stored in the bitmap memory of ports 40, 42, and 44. Proceed to instruction 716 to configure the program. In this regard, the pixels at the point in instruction box 716 Counter 75 is reset and column and row counts are set by memory controller 50. Set to be useful. Column and row counts are set and pixel counter After 75 is reset, the program advances to instruction box 717 and sets the column and row counters. transfers the pixels to the memory controller, allowing latching of even and odd pixels, Memory control signals that allow data to be stored in bitmap memory to occur. Data is stored in each bitmap memory of emphasis units 40, 42, and 44. The control signals that store the data (such as signals that allow odd numbers and even numbers) are both US patent applications. No. 077,586,506 provides further details. I will explain the details later, but when But the video controller 18 is a bitmap in the enhancement unit 40.42.44. is woken up by its video controller 18 when memory access is required. This memory control signal includes a shutdown signal. In this regard, video controller 1 The new data request signal generated by 8 can be displayed for display. lines of video data are being read from the enhancement unit 40.42.44. During this period, data storage via the format timing generator 45 is temporarily stopped. It is something that makes you Format timing generator 4 via memory controller 50 The interrupt signal and memory control coming out from 5 stores the data line.

After transferring the data to memory, the program increments the pixel counter 75. Proceed to instruction 721 to do so.

After the pixel counter 75 is incremented, the program Proceed to decision instruction 723 to determine whether the error occurred by the counter 75. . If a valid number is not obtained, the program returns to instruction 717 in the above order. repeat. If a valid number of pixels is obtained, the program returns the line counter From decision instruction 723, proceed to instruction box 725 to increment 77.

After the line counter 77 has been incremented, the program has generated a valid number of lines. Proceed to decision instruction 727 to determine whether or not. If the frame is not completed If so, the program uses decision instruction 7 to start another line of information as described above. 11 (FIG. 7A). Once the frame is complete, the program continues to instruction 730 Reset to line counter 77. When the counter 77 is reset, the The program returns to instruction 703 to wait for the next VSYNC signal.

From the foregoing, the format controller 79 along with the microprocessor 36 is used to control the horizontal video A normal video signal, such as an NTSC signal, has 525 lines of information. 480 lines of horizontal video information as used by display device 16 It should be understood that it is possible to create a line display. especially, Microprocessor 36 and controller 79 control each displayable frame of video information. The 525 lines of horizontal information in the frame are 640 x 480 pixels on panel 16. Gather them in the center so that they can be displayed in an array. In this regard, horizontal display horizontal The last 23 lines of TA are also deleted.

be done.

Most abandoned horizontal lines consist of "overscanned" or "invisible" lines. , and the top and bottom of the displayable frame can normally be displayed. This method is not effective in practice since it contains little or no video information. Ru. For example, referring to Figure 9B, the timing diagram shows a horizontal line format. Illustrated with matte. In this regard, the group of invalid lines is generally 910 The groups of active lines are generally indicated by dots 920. invalid la The in910 group is abandoned just before and after the VSYNC signal reaches a logic high. . The first 23 lines before the VSYNC signal and the first 22 lines after the VSYNC signal are blank. It is an effective line. This VSYNC signal represents vertical retrace. Video by similar means The width of the frame of information that can be displayed depends on the sample rate of the video signal. This allows for 640 lines of vertical information in each frame. sun The rate of pulling or PXCLK is the rate at which the television signal produced by the video signal source The horizontal divisor (P It is set by setting the ratio of XCLK rate and H3YNC rate). Ru. The signal from video drive module 26 already has the appropriate format. Therefore, the formatting techniques described above are not necessary. Regarding kneading, the microprocessor The processor 36 selects the desired format for the video drive module 26. is connected to the format timing generator 45.

C12, memory control device The memory controller 50 will be described in detail with reference to FIG. This memory controller 5 0 is the storage of the video data coming in from the enhancement units 40, 42, and 44, respectively. and controls reading. In this regard, memory controller 50 is disclosed in US Pat. As detailed in Application Box No. 077586,506, emphasis units 40, 42. When the 44 bit memory accesses the video controller 18, the firmware shuts down. except interrupting the format processor 79 (Figure 5) via the program. The explanation will be omitted.

The video controller 18 used by the video controller 18 will now be described in detail with reference to FIG. Column counter 61 and row counter 6 generating PH3YNC and PVSYNC signals 2, and further controls the retrace of the video data from the enhancement units 40, 42, 44. It includes a data request signal used by the memory controller 5o to do this. to this Regarding this, whenever the column counter 61 reaches the terminal count, the PVSYNC signal is activated. occurs and the PH3YNC signal is sent whenever row counter 62 reaches the terminal count. generate a number. These PH5YNC and PVSYNC signals are used to display video information. Used by panel 16 to control play.

The video controller 18 also includes an even-odd multiplexer 65 and a firmware cut-off program. Contains 1100. In particular, the video data has a corresponding emphasis unit 40 for each line. , 42 and 44, respectively, so the format timing generator 45 and The format of the data stored in the emphasis units 40, 42, 44 and the video format From the bitmap memory in control unit 18 and emphasis unit 40, 42, 44 understand that cooperative operations are required between reading formatted data and must be understood. The above cooperative operation or handshake is blocked by the firmware. This is accomplished by the software program 1100.

Video controller 18 also connects the panel from another color grading unit (not shown). 16 includes a mode selective multiplexer 111 for multiplexing data to 16. child In this regard, the mode selective multiplex transmitter 111 will be described in detail with reference to FIG. 5B. The modem selection multiplexer 111 allows the user to transmit data through the infrared receiver 38. Once sprayed, you can select the format of the video data. In this regard, this The stem transfers video data to TV signal source mode or computer video output signal. It can be displayed from either source mode.

Referring now to FIGS. 4 and 11, the shutdown program 1100 will be described in detail. This video controller is used whenever the device 18 requests video data for display. The controller 18 connects the new data line between the video controller 18 and the memory controller 5o. Generates a cutoff control signal on the requested bus.

The shutdown control signal starts the shutdown firmware program 1100. to this The shutdown firmware program 1100 then starts at box 1101. , the data is stored in the bitmap memory of the enhancement unit 40.42.44. The process advances to an instruction box 1103 for stopping or interrupting the process. Then the program Multiple memory addresses from column counters within video controller 18 An instruction box to place the line on the address bus of the emphasis unit 40.42.44. Proceed to Cus 11o5.

The address bus of the emphasis units 40, 42, 44 is a format timing generator. Distributed by memory addressing and video control memory addressing. This is a normal address bus.

After the plurality of memory address lines are enabled, memory controller 50 commands Box 11o7 sets the column counter to VRAM5 or emphasis unit 40, 42.4. The RAS signal is generated while being transferred to the bitmap memory No. 4. then professional The program prevents the memory address bus from being controlled by the video controller 18. Proceed to instruction box 1109. The program then goes to instruction box 1111. and outputs all zeros to the address bus through the memory controller 5o. yes Then, the memory controller sends the CAS signal to the line position highlighting unit 40. ．． An instruction box that allows you to connect to a 42.44 bitmap memory. Proceed to step 1113. The program then proceeds to instruction 1115 and downloads the video data. Each enhancement unit 40.42.4 as accepted by the video controller 18 Input each bitmap memory in 4. In this regard, video data All rows of data are placed into their respective bitmap memories for display. You should understand that you are under pressure.

After the video data has been entered into the bitmap memory, the program is activated. A new line of data may be displayed on the dynamic matrix panel 16. The process advances to instruction 1117 which indicates that the memory input is complete, that is, acknowledges the completion of memory input. In particular, row PH3YNC produced by counter 62 is sent to a logic low level and the video Line counter 62 in controller 18 indicates that another new line of video data is needed. It stays in the low position until it reaches a terminal count indicating that the Other lines of data are needed. If required, another cut-off signal is generated. New request data signal for video control When generated by device 18, PH3YNC goes to an active level.

After checking the bitmap memory load, the program Proceed to instruction 1119 to return the control by the format timing generator 45 to the control by the format timing generator 45. nothing.

The program will then program the columns and rows in the format timing generator 45. Proceed to instructions 1121 to enable the count to be set, as previously described. Prog The RAM then restarts the format program 700 from the point where it was interrupted. Proceed to box 1123.

As best shown in FIG. 5A, pattern inversion circuit 103 generally includes CLKA, Dividers 104-106 that divide the PH5YNC and PVSYNC signals into two, and an additional 1× Unique O'R gate 107.109 that inverts the 2-pattern logic every frame. Contains a set of In this way, 15 levels of gradation inversion is achieved.

The digitized data from the analog-to-dental converter 51 is scaled and arranged. The output signal from the analog-to-digital converter 51 is transferred to the (R7-R2) is the input buffer 102A on all PXCLK signals. It is connected to the. On the other hand, the output signal from buffer 102A ( R7-R2) are connected to the inputs of pattern logic unit 110.

The pattern logic unit 110 will be described in detail with reference to FIG. 5A and Table ■. The tone logic unit 59 creates weight pixel chroma levels according to the truth table in Table 1. It consists of a single XILINK unit programmed to perform this , pattern logic unit 110 displays the red component of the video data. In order to increase the number of gray levels possible from 8 to 57 levels, bit For the purpose of processing the data stored in the map memory 57, the analog-digital The bitmap memory 57 is connected between the digital converter 51 and the bitmap memory 57. In particular, The turn logic unit 110 specifies the weight color saturation level pixels for generating the pixels. The chromaticity level of an individual pixel molecule within a group of pixel molecules is defined as a color gradation. It has the role of In this regard, this 2x2 pattern logic unit 110 Arrangement groups or groups of 4-pixel molecules such as turn groups (Figure 12) Compare each 6-bit data from the analog-to-digital converter 51 in relation to , chromatic intensity for a single component panel pixel such as panel pixel aOO (Figure 12) effectively quantize or achieve.

For such quantization, the pattern array is divided into groups 300 to 305 (Figure 12). created within a pixel group to sharpen composite pixel groups such as This can be clearly seen in Figure 12. Each synthetic group consists of 4 vixel molecules. Ru. As will be described in detail later, the pattern logic 59 is used to form a composite pixel image. one or more pictures in each composite group, such as composite group 300. Selectively energize cell molecules. pixel molecule 230.225.230.231 For example, one or all of the four possible pixel molecules such as group 300 You should understand that you may be active in one of these groups. death However, the human eye can only discern individual pixel molecules within columns and rows. Therefore, there are over 185,000 classification combinations of pixel molecules. To sharpen a single composite panel pixel image with different tonal levels of used for. In other words, selectively activated pixel molecules 220.22 5.234.231 is a composite panel pixel such as panel pixel 300. Creates 57 different weight pigment brightness levels for red pigments (as well as blue and green pigments) combined for export. Similarly, for pixel 221.227.232.223 Other pixel molecules such as composite panel pixel 302 also include other composite panel pixels such as composite pixel 302. combine to form.

As mentioned above, the liquid crystal panel 16 normally supplies only eight color gradations for each of the primary colors red, green, and blue. However, pattern logic 59 and 110 are connected to active matrix panel 16. Over 185,000 possible color tone combinations for each composite pixel in video pixels working together to combine molecular signals so that The pattern logic 110 will be explained in detail with reference to FIGS. 12 and 13. As each panel pixel molecule, such as panel pixel molecule 220, is addressed, A pair of location signals (pixel and line) are sent by the quadrant circuit 111. generated. In this regard, the pixel and line signals are Addressed quadrant location within a given composite pixel group. , 1゜2 ．． 3 is displayed. Regarding this, group 3o.

is 2x of columns (lines) and rows (pixels) with quadrant positions 0, 1, 2.3 It is formed in a two-matrix array.

To explain the quadrant circuit 111 in more detail with reference to FIG. 5B, the quadrant circuit 1 11 is the pixel clock level normally used for the 2×2 pattern logic unit 110. This includes one division by two dividers 103 which effectively halve the output. Split The device 103 is reset every HS YNC time.

Quadrant circuit 111 also includes two dividers that effectively halve the H8YNc rate. 108. Divider 108 receives the VSYNC signal It is reset every time.

Quadrant circuit 111 also receives control signal mode generated by microprocessor 36. Multiplexer unit 1 whose output signal lines are controlled via the Contains 12. Multiplex 112 is the output of divider 108 or signal conversion. Either two input signals of the odd field signals generated by the It has a number.

From the above, the output signal from the divider 108 or the odd feed from the signal converter 32 A 2x2 pattern logic unit is connected from either side of the field signal via multiplexer 112. It should be understood that this is gated to 110. In this regard, conductor 3 The television selection mode signal on 6C controls multiplexer 112.

Then, the location signals are determined by the following formula (Table ■): R7, R6, R5, R4, The quantized data from the analog-to-digital converter 51 identified as R3 and R2 are are coupled together to pattern logic 110.

Signal here! pd3,! pd2,! pdl,! pdO is a 4-bit composite signal R 3*-RO*, respectively. In this way the panel pixel molecule 22 The chromatic brightness emitted from individual panel pixel molecules such as 0 is ``odd and display The input data combined with the "mode" signal is identified as i3.12.11.10. 4 bits of data from the bitmap memory 57.

[Display Mode] signal is the active microcontroller in EGA/VGA mode. It should be understood that this is generated by processor 36.

To explain Table ■ in detail, Table ■ is a truth table that represents the operation of pattern logic 110. be. This truth table has input data fields, location data fields, and output data fields. It consists of three columns. The data in this truth table is base 1 instead of base 2. Note that it is displayed as 0.

The following example illustrates how this truth table works.

Example 1. Input bits R7, R6, R5, R4, R3°R2 are 0OOOO2 or It is 010. Pixel and line bits are OO2 or 015. It is. these With bits as input data, the pattern logic unit 110 uses the above formula to Calculate output data pd3, pd2, pdl, pdO. In this example, The output bits of the number are 000. as shown in the third column of the truth table. or 010 and Become. At this time, the input bits are R7, R6, R5, R4゜R3, R2 are o　o　o o o2 or o. If so, the output data is what the pixel and line values are. Note that it is always 010 no matter what.

Example 2. Input bits R7, R6, R5, R4, R3°R2 are 011012 or 13. , is. Pixel and line bits are OO2 or 010. in this case , third column of truth table, output bits pd3, pd2, pdl, p according to output data dO is 0112 or 3. . It is determined that

Embodiment 39 Manual bits R7, R6, R5, R4, R3°R2 are as in Embodiment 2. 01101□ or 13. . It is.

However, the pixel and line values are 112 or 3. .

It is. In this case, the output bits pcta, pd2, pdl, pcto are 0112 Or 310.

Example 4. Input bisoto R7, R6, R5, R4, R3゜R2 is 10100□ or It is 20Io. As in Example 1, the output bits pd3, pd2, The values of pdl, pdO are independent of the pixel and line bit values.

In this example, the output is 10'1° regardless of the pixel and line bit values. or 5. . It is.

Using the embodiments described above, one skilled in the art will understand that the input bits R7°R6, R5, R4, R3 , R2 and the given panel pixel numerator based on pixels and lines All possible output bits p that set each chromatic intensity for any panel pixel molecule It would be possible to define values for d3, pd2, pdl, pdo.

Table eeeeee D.2. 1x2 pattern logic unit This 1x2 pattern logic unit 59 More specifically, the pattern logic unit 59 is stored in the bitmap memory 57. Pulls out stored data and completes the formation of individual high color resolution composite pixels. Quantize each 4-bit byte. Regarding this, the data for 4-bit data is The spray mode signal is a set of 4 levels with 16 possible levels of input gradation. combination. Use Mo.

D.2.1. 1x2 pattern logic formula and truth table The quantized data shown in Table 2 is obtained from the following equation.

Irp2-(Sword/Te/Ear/Mi/Boiled◆Stone) From table ■ and table ■, 2×2 pattern logic 1 The cell of each composite pixel in the composite pixel formed via 10 is generally defined by Equation 1 It should be understood that it can have up to 15 special values defined by Ru. Here, Equation 1 is the number of colors per color component. = (Number of cell colors - 1) x Number of cells + 1 (1) Then 2X2 pattern logic unit The following equation was obtained for the point 110 using equation (1).

(15-1)X4+1=57 levels Similarly, for the IX2 logic pattern unit 59, the following equation is obtained using equation (1). Ta.

(8-1)×2+1=15 levels The unique and specific description of this application is set forth above, but is not limited thereto. However, various different modifications are possible and contemplated within the scope of the claims. You should understand that.

Fig, 5 FIG, 9B Vertical 5YNC marker c+t starting in new frame.

920-i-1111111111111 H8YNC machine starting on new line -ark

Claims (1)

[Claims] 1. Also includes multiple pixel elements that are grouped together to form multiple composite pixels. An interface for interfacing a video signal generator to a display device means for quantizing a device input tone level signal exhibiting at least X tone levels; , X/4 tonal levels, and one identification of the composite pixel. quantization means for converting an output gray level signal to be assigned to a quadrant, the output gray level; converting the signal into a group of binary signals and driving each one of the pixel elements. so that each composite pixel element has substantially Pattern means that can indicate individual gradation levels ,as well as By varying the conversion of the tone level signal on a frame-by-frame basis, individual pixel requirements can be pattern inversion means for gray curling the element; A scaling device consisting of. 2. The display system unit according to claim 1, wherein the display device is a liquid crystal display device. knit. 3. The liquid crystal display device is an active matrix thin film transistor liquid crystal display panel. 3. The display system unit according to claim 2, wherein the display system unit is a mobile phone. 4. The display panel comprises a matrix of electronically operated pixel elements, the pixels Claim 3, wherein each element is a set of three sub-pixel components. display system unit. 5. Each sub-pixel component is divided into N registers by one of the groups of the binary signals. When driven by one of the bells, each sub-pixel component exhibits a different color, resulting in color mixing. The display system unit according to claim 4, which generates a large number of color gradations by to. 6. The display system unit according to claim 5, wherein the color mixing method is an additive color mixing method. to. 7. The display system unit according to claim 5, wherein the color mixing method is a subtractive color mixing method. to. 8. Each one of the groups of binary signals is assigned a number of different color tone levels. as claimed in claim 1, in which the signals are grouped into groups of three binary signals representing display system unit. 9. The number must be at least 57 different tonal levels of one primary color. The display system unit according to claim 8. 10. RGB color composition signals allow display devices to generate many different color gradation levels. a device for coupling TV formatted signals having respective signal components to the display device; the individual pixel elements of the composite pixel in response to the TV formatting signal; A formatting means that generates a gray curling signal indicating the intensity level of the Temporarily stores the rayscaling signal to drive individual pixel elements of the display device. bitmap memory means to facilitate, and Each one of the gray curling signals is searched, and the search signal is The individual pixels are grouped into groups of binary signals to form the composite pixel. pattern means for driving the composite pixel elements, and the composite pixel is in a TV format. For each individual RGB color composite signal component that makes up a portion of the converted signal, Apparatus for providing pixel images with at least 57 different color component tone levels. 11. The formatting means is signal conversion means for converting a composite TV signal into an RGB analog video signal; The analog video signal is converted into individual digital signals that represent images that can be displayed in full color. analog/digital conversion means for converting into coupled to the analog/digital conversion means to quantize and store the digital signal; scaling means for storing the quantized digital signal; bit memory means for storing the quantized digital signal; Beauty Each one of the digital signals is searched and the digital signal is converted into a binary signal. individual pixels to form a composite pixel. and pattern means for driving the color elements to form a full color image. The device according to item 10. 12. Additionally, externally derived beat patterns and flickers in the full-color image 12. The apparatus of claim 11, comprising means for substantially removing car. 13. The scaling means buffer means for temporarily storing and quantizing the digital signal; and coupled to the buffer means to buffer the digital signal substantially without introducing quantization errors; 12. The apparatus according to claim 11, comprising encoder means for quantizing the signals. 14. The pattern means is means for retrieving the stored quantized digital signal; and means for retrieving the retrieved quantized digital signal; means for formatting and driving the display device with a video clock signal. 12. The apparatus according to claim 11. 15. RGB color composition signals allow display devices to generate many different color gradation levels. a method for coupling TV formatted signals each having signal components to said display device; generating a composite pixel image signal in response to the TV formatted signal; The composite pixel image signal is temporarily stored to drive the individual pixel elements of the display device. facilitate, Searching each one of the composite pixel image signals, the search signal consists of a binary signal. group, and consists of driving the individual pixel elements forming the composite pixel, Each individual R of which the composite pixel forms part of a TV formatted signal. Give pixel images with different color component gradation levels for the GB color composite signal components. How to do it. 17. into multiple pixel elements that are grouped together to form multiple composite pixels Interfacing video signal generators to display devices that produce more full-color images sing, A device input tone level signal exhibiting at least X tone levels is quantized to quantized and in one particular quadrant of the composite pixel, representing four tonal levels. to the assigned output gradation level signal, Convert the output tone level signal into a group of binary signals and assign pixel elements to it. each composite pixel element is one of each of the plurality of individual colors. A full image consisting of How to display color images. 18. Each sub-pixel element provides at least N tonal levels for each color. A table with multiple pixel elements, each containing a group of subpixel elements that interfacing a video signal generating device to the display means, each of the pixel elements; generate at least X tonal levels for multiple individual colors using one (However, X is substantially larger than N), generating a gray level signal so that each one of the sub-pixel elements corresponds to the plurality of individual pixels; Set a predetermined gradation level for each color, and The tone level signal is converted into a group of binary signals to form a group of sub-pixel elements. driving each one of the cough sub-pixel elements to each one of the plurality of individual colors; A frame consisting of X gradation levels can be displayed for each one. A method for forming color images.