JPH074975A - Timing generation circuit for light interference angular velocity meter - Google Patents

Abstract

PURPOSE:To generate reference timing signals which can highly sensitively detect respective components of two, three and four times harmonic frequency fm from interference light by using general components. CONSTITUTION:A clock signal is sequentially divided by 2 by first and second dividing means 33, and its output having inverse polarity is divided by 8 by a third dividing means 36 to obtain a reference signal of 3fmr. The inverse polarity output of the first dividing means 33 is divided by 3 by a fourth dividing means 43, and its output is divided by 8 by fifth and sixth dividing means 45, 46 to obtain a reference signal of 2fmr. The inverse polarity output of the fifth dividing means 45 is divided by 2 by a seventh dividing means 51 to obtain a reference signal of 4fmr. The fourth dividing means 43 comprises a JK flipflop, while other dividing means comprise D-type flipflops.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention allows right-handed light and left-handed light to pass through an optical path that makes at least one round, and determines the angular velocity about the axis applied to the optical path as a right-handed light and a left-handed light. The present invention relates to a timing generation circuit for generating a reference timing signal for detecting the phase difference in the optical interference gyro which is detected by the phase difference and the reference timing signal necessary for obtaining a stable operating point.

[0002]

2. Description of the Related Art A conventional optical interference angular velocity meter (hereinafter referred to as FOG) will be described with reference to FIG. Light I from the light source 11
Is sequentially introduced through the optical coupler 12, the polarizer 13 and the optical coupler 14 into the loop optical path 15 from both ends thereof. The left and right lights that propagate through the optical path 15 are phase-modulated by a phase modulator 16 arranged between one end of the optical path 15 and the optical coupler 14. The two lights having undergone the phase modulation are combined by the optical coupler 14 and interfere with each other, and again pass through the polarizer 13 and are branched to the light receiver 17 by the optical coupler 12 and photoelectrically converted. The optical path 15 is composed of, for example, an optical fiber wound plural times in a loop. In the state where the angular velocity in the circumferential direction is not applied to the optical path 15, the phase difference between the two lights in the optical path 15 is ideally zero, but the optical path 15
When the angular velocity Ω is applied around the circumference of, the angular velocity Ω causes a so-called Sagnac effect, which causes a phase difference ΔΦ _S between the two lights. This phase difference ΔΦ _S is
It is expressed by the following equation.

ΔΦ _S = 4πRLΩ / (Cλ) (1) where C: speed of light λ: wavelength of light in vacuum R: radius of optical fiber coil 15 L: length of optical fiber of optical fiber coil 15 The photoelectric conversion signal V _P from 17 can be expressed by the following equation when the phase modulation by the phase modulator 16 is P (t) = A sin ω _m t.

V _P = (I / 2) K ₁ {1 + cos ΔΦ (Σε _n · (−1) ⁿ · J _2n (X) · cos 2nω _m t ′) −sin ΔΦ (2Σ (−1) ⁿ · J _{2n + 1} (X) · cos (2n + 1) ω _m t ′)} (2) Here, Σ is from n = 0 to infinity, t ′ = t−τ / 2 ε _n = 1; n = 0.2; n ≧ 1 K: constant I: light emitted from the light source 11 J _n : first-order Bessel function X: 2 Asinπfmτ ΔΦ _S : phase difference between left and right lights in the optical system ω _m : angular frequency of phase modulation (ω _m = 2πfm ) Τ: Propagation time of light in the optical path 15 As apparent from the equation (2), the photoelectric conversion signal V _P has s
The term proportional to inΔΦ _S and the term proportional to cos ΔΦ _S are included, and thus the angular velocity Ω can be detected by measuring the intensity of the interference light.

The output of the photodetector 17 is input to the synchronous detection circuit 18, where the third harmonic component of the phase modulation frequency is
Reference timing signal f ₃ from the timing generation circuit 19
= 3f _m , the signal is synchronously detected and taken out. The output of the synchronous detection circuit 18 is further a low pass filter (LPF).
After the AC component is filtered by 21 and set to an appropriate gain, it is taken out to the output terminal 22 as an FOG output.
The output V ₃ of the FOG is expressed by the following equation.

V ₃ = I · K ₂ · J ₃ (X) · sin ΔΦ _S (3) By the way, since the input sensitivity in the formula (3) depends on the value of X of the Bessel function, it has been hitherto known (Japanese Patent Laid-Open No. 62-
12811) is the Bessel function J ₂ (X) and J
J ₃ (X) becomes the maximum value at the position where ₄ (X) intersects,
The phase modulation is operated at that position (X = 4.2), and J
₂ (X) and J ₄ (X) are substantially equal to each other, that is, the second harmonic component and the fourth harmonic component in the output of the photodetector 17 are substantially equal to each other. An automatic control loop is provided to control the drive state of. (See the Bessel function graph of FIG. 4.) That is, of the output of the photodetector 17, the second harmonic component of the phase modulation frequency is synchronously detected by the synchronous detection circuit 23 with f ₂ = 2f _m as the reference timing signal, and the fourth harmonic is generated. The wave component is synchronously detected by the synchronous detection circuit 24 with f ₄ = 4f _m as a reference timing signal.

The output V ₂ of the synchronous detection circuit 23 is supplied to the + input side of the differential amplifier 25, and the output V ₄ of the synchronous detection circuit 24 is input to the − input side of the differential amplifier 25. The output of the differential amplifier 25 is input to the integrator 26. The automatic voltage regulator 27 increases the voltage of the signal of the drive frequency f _m applied to the phase modulator 16 by the positive signal from the integrator 26, and applies it to the phase modulator 16 by the negative signal from the integrator 26. The automatic control loop is configured so that the voltage of the signal of the driving frequency f _m is reduced. Here, the device is such that the output of the differential amplifier 25 is zero, that is, V ₂ = V ₄
Then, the Bessel functions of the first kind J ₂ (X) and J ₄ (X) are applied to the phase modulator 16 by the automatic voltage regulator 27 so that the same value, that is, the value of X becomes about 4.20. Voltage is adjusted.

[0008]

As described above, the light receiver
The output of 17 is 2f_m3f_m4f_mEach reference of timing
Operation is stabilized by synchronous detection with the
Gyro output can be obtained with good sensitivity, but
The specific configuration of the trigger generation circuit 19 is not shown. Received at the place
The reference timing signal is opposite to the detected signal in the optical device 17.
In the case of phase, the polarity of the detection output becomes negative and the 90 degree phase
, The detection output becomes zero, and it is possible to detect.
I can't come. The object of the present invention is to output 2f from the output of the light receiver._mThree
f_m4f _mIt is possible to properly extract each component of
Of the timing generation circuit that generates each reference timing signal
It is to provide a concrete configuration.

[0009]

According to the present invention, the clock signal from the clock generator is divided in half by the first frequency dividing means, and the positive frequency division output is obtained by the second frequency dividing means. In 2
The frequency is divided by 1 and the divided output of the opposite polarity is divided by 1/8 by the third frequency dividing means and supplied to the first synchronous detection means as a reference timing signal. The polarity frequency division output is divided into ⅓ by the fourth frequency division means, the frequency division output is halved by the fifth frequency division means, and the positive frequency division output is divided into the sixth division. The frequency dividing means divides the frequency into 1/4 and supplies it to the second synchronous detection means as a reference timing signal, and the reverse polarity frequency division output of the fifth frequency dividing means is divided into 1/2 by the seventh frequency dividing means. It is then supplied to the third synchronous detection means as a reference timing signal.

[0010]

FIG. 1 shows an embodiment of the present invention. The clock signal from the clock generator 31 is the D flip-flop 3
The frequency is divided into halves by the first frequency dividing means 33 consisting of 2,
The positive frequency division output, that is, the D-type flip-flop 32
The Q output of is divided by a second by the second frequency dividing means 35 including the D-type flip-flop 34. Second frequency dividing means 3
5 reverse polarity frequency division output, that is, D flip-flop 34
Q output of is divided into ⅛ by the third dividing means 36. The third frequency dividing means 36 is a D-type flip-flop 37,
The half-cycles of 38 and 39 are connected in cascade, and the Q output of the flip-flop 37 is supplied to the flip-flop 38.
The q output of the flip-flop 38 is the flip-flop 39
And the Q output of the flip-flop 39 is used as the output of the third frequency dividing means 36.

On the other hand, the reverse polarity frequency-divided output of the first frequency dividing means 33, that is, the q-output of the D-type flip-flop 32 is frequency-divided to 1/3 by the fourth frequency-dividing means 43 including the JK flip-flops 41 and 42. To be done. The positive frequency-divided output is divided by a fifth by the fifth frequency dividing means 45 composed of the D-type flip-flop 44, and the positive-polarity divided output is divided by a sixth by the sixth frequency dividing means 46. Be lapped. 6th frequency dividing means 46
2 are D-type flip-flops 47 and 48, respectively.
The frequency dividers are connected in cascade.

The reverse polarity frequency-divided output of the fifth frequency dividing means 45, that is, the q-output of the flip-flop 44 is frequency-divided by half by the seventh frequency-dividing means 51 composed of the D-type flip-flop 49. The positive frequency division output of the sixth frequency dividing means 46 is halved by the eighth frequency dividing means 53 composed of the D-type flip-flop 52.
Is divided into. In this configuration, when the power supply voltage rises to a predetermined value as shown in FIG. 2 and the reset for each flip-flop is released (FIG. 2A), the clock generator 3
The clock signal from FIG. 1 (FIG. 2B) is divided into two by the first frequency dividing means 23, and the first frequency dividing means 23 outputs the clock signal shown in FIG.
Positive frequency division output and reverse polarity frequency division output as shown in C and D are obtained, and the positive polarity frequency division output is further divided into two by the second frequency dividing means 35, and is shown in FIG. 2E. Output is obtained,
The output is sequentially divided into halves at the first stage, the middle stage and the final stage of the third frequency dividing means 36, and the outputs shown in FIGS. 2F, G and H are obtained. The frequency division output of the third frequency division means 36 (see FIG.
H) is supplied to the synchronous detection circuit 18 in FIG. 3 as a reference timing signal f ₃ = 3f _mr .

Reverse polarity frequency division output of the first frequency division means 33 (see FIG. 2).
2D is divided by the fourth frequency dividing means 43 into one third, and
The output shown in is obtained. This frequency division output is the fifth frequency division means 4
It is divided into two by 5 and the positive division output is shown in Fig. 2J.
The output is further divided by the sixth frequency dividing means 46, and the Q outputs of the flip-flops 47 and 48 are as shown in FIGS. 2K and 2I. The frequency division output (FIG. 2L) of the sixth frequency dividing means 46 is supplied to the synchronous detection circuit 23 in FIG. 3 as the reference timing signal f ₂ = 2f _mr .

The reverse polarity frequency division output of the fifth frequency division means 45 is shown in FIG.
2M, and the output is divided by the seventh frequency divider 51 to be as shown in FIG. 2N, which is supplied to the synchronous detection circuit 24 in FIG. 3 as the reference timing signal f ₄ = 4f _mr. . The output of the sixth frequency dividing means 46 (FIG. 2L) is halved by the eighth frequency dividing means 53 and becomes as shown in FIG. 20, and this output is passed through the automatic voltage regulator 27 in FIG. It is supplied to the phase modulator 16 as a modulation signal of frequency f _m .

Reference timing signal of 3f _mr (FIG. 2H)
And 2f _mr reference timing signal (Fig. 2L) and 4f _mr
Temporal center of the reference timing signal (Fig. 2N) is, as is clear from FIG. 2, match each 1 / f _m, thus the output of the photodetector 17, 2f _ms component, 3f _ms component, 4f
Each _ms component can be detected with high sensitivity and 2f _ms
The component and the 4 f _ms component can be used for stable operation, and the gyro output can be obtained with high sensitivity by the 3 f _ms component.

Although the present invention is applied to the open loop type in the above description, it can be applied to the closed loop type.

[0017]

As described above, according to the present invention, high frequency components of 2, 3, and 4 times the modulation frequency f _m in the interference light can be detected with high sensitivity, and stable operation is achieved. Also, a highly sensitive gyro output can be obtained. Further, each frequency dividing means can be constituted by a general-purpose flip-flop, and it is easy to form a gate array to reduce the size and weight, and the number of parts can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing an operation example of FIG.

FIG. 3 is a block diagram showing an example of an optical interference angular velocity meter to which the present invention is applied.

FIG. 4 is a graph showing a Bessel function of the first kind.

Claims (1)

[Claims] 1. An optical path that makes at least one round, branching means that makes light from a light source enter the optical path as right-handed light and left-handed light, and right-handed light and left-handed light propagating through the optical path. An interfering means for interfering light, a phase modulating means for cascading between the branching means and one end of the optical path and providing a phase change to the clockwise light and the counterclockwise light, and the interfering light A light receiver for detecting light intensity as an electric signal, and a first for synchronously detecting a third high frequency of a modulation frequency of the phase modulating means among outputs from the light receiver and outputting an angular velocity.
Synchronous detection means, second synchronous detection means for synchronously detecting a second high frequency of the modulation frequency in the output from the photodetector, and fourth synchronous detection for the fourth harmonic of the modulation frequency from the output of the photodetector 3 synchronous detection means, difference detection means for detecting the difference between the output of the second synchronous detection means and the output of the third synchronous detection means, and the detection power of the difference detection means makes the detection power zero. In the timing generation circuit of the optical interference gyro including the means for feedback controlling the phase modulation means, a clock generator and a first frequency-dividing clock signal from the clock generator. The frequency dividing means, the second frequency dividing means for dividing the positive frequency-divided output of the first frequency dividing means by half, and the reverse polarity frequency-divided output from the second frequency dividing means by 8 minutes. The frequency is divided into 1 and its positive output is the first synchronous detection means. A third frequency dividing means for supplying as a reference timing signal, a fourth frequency dividing means for dividing the reverse polarity frequency divided output of the first frequency dividing means into one third, and an output of the fourth frequency dividing means. A fifth frequency dividing means for dividing the frequency by one half and a positive frequency dividing output of the fifth frequency dividing means are divided by four, and the positive polarity output is sent to the second synchronous detection means. Sixth frequency dividing means for supplying as a reference timing signal, and the reverse polarity frequency-divided output of the fifth frequency dividing means is halved and its positive output is supplied to the third synchronous detection means. And a seventh frequency dividing means, which is supplied as a.