JPH0748677B2 - Equalizer - Google Patents

Description

The present invention relates to an equalizer, and more particularly to an equalizer used in a digital wireless communication system.

[Conventional technology]

In a digital wireless communication system, when a received signal is distorted due to fading or the like, intersymbol interference occurs and the code error rate deteriorates. Therefore, the equalizer is often used to automatically equalize the distortion.

FIG. 2 is a block diagram showing a general example of a reception system using an example of such a conventional equalizer.

The receiving system shown in FIG. 2 is a data signal D _1p , D _2p , D _1q , D _2q.
And the error signals E _p and E _q (hereinafter these 6 signals are collectively referred to as data signals) and the intermediate frequency (hereinafter referred to as IF) signal I ₁ are input.
An equalizer 5 for outputting an IF signal I _2, the demodulation device 2 and outputs the signals S ₁ out of synchronization and enter the IF signals I ₂ data signal, the data signal _{D 1p · D 2p · D 1q} · D 2q Error rate signals S ₂ and 4
The reception signal processing device 3 that outputs the column data and the code conversion device 4 that inputs the four columns of data output by the reception signal processing device 3 and outputs the one column data are configured.

The receiving system shown in FIG. 2 is a receiving system of a digital radio communication system using a 16-value quadrature amplitude modulation system.

The IF signal I ₁ output from the receiving device (not shown) is equalized by the equalizer 5.
Are equalized to form the IF signal I ₂ . The demodulation device 2 demodulates the IF signal I ₂ and outputs a data signal. Of these data signals, the data signals D _1p , D _2p , D _1q , D _2q are the signals containing the information transmitted by the line, and are usually scrambled on the transmission side, and also used for wireless section monitoring such as parity bits. It contains the additional bits of. The reception signal processing device 3 descrambles the data signals D _1p , D _2p , D _1q , D _2q , _removes additional bits, performs speed conversion, and outputs data of four columns.
The reception signal processing device 3 also monitors the code error rate by means of a validity bit or the like, and outputs the error rate signal S ₂ as an alarm signal when the code error rate deteriorates below a predetermined value. The code conversion device 4 performs code conversion of four columns of data output from the reception signal processing device 3 from unipolar to bipolar, performs column conversion from four columns to one column (as necessary), and converts the converted data to the reception side. To the carrier terminal (not shown).

The demodulator 2 inputs the IF signal I ₂ and outputs the carrier signal CR / out-of-synchronization signal S _1, and the carrier synchronization circuit 21 inputs the IF signal I ₂ / carrier signal CR and outputs the baseband signals B _p and B _q . The quadrature detection circuit 22 that outputs and the identification circuit 2 _p that inputs the baseband signal B _p or B _q and outputs the data signal D _1p・ D _2p or the data signal D _1q・ D _2q and the error signal E _p or E _q And 2 _q .

The carrier wave synchronization circuit 21 reproduces the carrier wave signal CR in synchronization with the IF signal I ₂ and generates an out-of-synchronization signal S ₁ as an alarm signal when the carrier wave synchronization is out of synchronization. Quadrature detection circuit
The quadrature detector 22 quadrature-detects the IF signal I ₂ that is a 16-valued quadrature amplitude modulation wave with the carrier signal CR as a reference, and outputs a baseband signal B _p B _q
Is output. The discrimination circuit 2 _p discriminates the baseband signal B _p at the sampling point and outputs the data signal D _1p · D _2p , and also determines whether the data signal B _p is larger or smaller than the normal value (normal level) at the sampling point. Discriminate and the discrimination result is 2
The error signal E _p, which is a value signal, is output. Identification circuit 2
From the baseband signal B _q to the data signal D _1q
-Create D _2q and the error signal E _q .

The equalizer 5 is a transversal filter type equalizer, which has (2m + 1) taps and weights the real part and the imaginary part of the output of each tap except the center tap by 4 m.
Transversal filter 10 with individual weighting circuits
And the weighting control signals R _{m to} R that control each weighting circuit.
_-m · I _{m to} I _-m and a weighting control signal generation circuit 51.

The weighting control signal generation circuit 51 logically operates the data signal by a control algorithm incorporated therein to generate weighting control signals R _{m to} R _-m · I _{m to} I _-m . Each weighting circuit of the transversal filter 10 has a weighting control signal R _{m to} R _-m.
The IF signal I ₁ is equalized and becomes the IF signal I ₂ by being controlled by I _{m to} I _−m .

FIG. 3 is an explanatory diagram showing the arrangement of signal points in the 16-ary quadrature amplitude modulation method.

The p coordinate of each signal point corresponds to the data signals D _1p and D _2p , and q
The coordinates correspond to the data signals D _1q and D _2q .

The control algorithm of the weighting control signal generation circuit 51 includes
There are various algorithms including the ZF (Zero-forcing) method (for example, "Digital Signal Processing" edited by the Institute of Electronics and Communication Engineers).
(Sho 50-11-10) The Institute of Electronics and Communication Engineers, P.235-240). In both algorithms, the error signal E _{p at} all sampling points (of the discriminator 2 _p · 2 _q ) is usually independent of the position of the signal point (that is, the data signal D _1p · D _2p · D _1q · D _2q ). · E _q is used for generating the weighting control signals _{R m ~R -m · I m ~I} -m. The control algorithm using the error signals E _p and E _q at all sampling points in this way is called an all-equalization control algorithm. The all-equalization control algorithm requires only two data signals among the data signals D _1p , D _2p , D _1q, and D _2q that determine which quadrant in FIG. 3 the signal point is in. One is unnecessary.

The IF signal I ₁ becomes excessively distorted and cannot be equalized by the equalizer 5, resulting in a large distortion of the IF signal I ₂ , or
If the carrier wave synchronization circuit 21 of the demodulator 2 becomes out of synchronization due to excessive noise of the IF signals I ₁ and I ₂ , the data signal becomes undefined, and the equalizer 5 uses the all equalization control algorithm. If it is used, the equalization capability may be lost, and the IF signal I ₁ may not be equalized and may give a large distortion. IF signal again in this state
Even if I ₁ returns to the normal state, the distortion of the IF signal I ₂ remains large, and the carrier synchronization of the carrier synchronization circuit 21 may not be pulled in.

As described above, when the equalizer 5 uses the total equalization control algorithm, the error signal at all sample points
Since E _p and E _q are used, the equalization characteristic is excellent as long as the carrier wave synchronization of the demodulator 2 is pulled in, but the lead-in characteristic when the carrier wave is lost is poor.

In order to improve this pull-in characteristic, the signal points are the outermost signal points (signal points a ₁ , a ₂ , a ₃ , a ₄ ) circled in FIG. ₃ or the innermost signals in the signal point arrangement. Only when it is a point (signal point c ₁ , c ₂ , c ₃ , c ₄ indicated by triangle marks), the error signal E _p , E _q at the sample point is weighted by the control signal R _m
~ R _-m・ I _m ~ I _-m A control algorithm used to generate (known as such a control algorithm is called a partial equalization algorithm) is known.

If the partial equalization algorithm described above is used for the equalizer 5,
As will be described below, even if the carrier wave synchronization of the demodulation device 2 is lost and the data signal becomes indefinite, the weighting control signal generating circuit 51 causes the significant weighting control signals R _{m to} R _-m · I _{m to} I _-m. Can occur.

That is, when the carrier wave is not synchronized, the p-axis and the q-axis rotate about their intersections on the position plane shown in FIG. When the p-axis and q-axis are fixed, each signal point is
It is in a state of rotating on a concentric circle (shown by a broken line circle in FIG. 3) centering on the intersection of the axes.

In this state, for example, when the signal at the signal point a ₁ is sent out on the transmitting side, the received signal should be a signal in the area of any one of the signal points a ₁ a ₂ a ₃ a ₄ What is the signal point area?
It should be identified as a region including the signal point and surrounded by a straight broken line or a solid line (because of the 4-phase phase uncertainty of the reproduced carrier even if the carrier is correctly synchronized,
It is generally uncertain which of the above four areas is to be identified), but the signal points a _i · a _ij (i is 1, 2, 3 or 4, j is 1)
Alternatively, it is unclear which signal point region of 2) is identified as the signal. When it is identified as a signal in the area of the signal point b _ij , it is identified as an erroneous signal.
The signal at signal point a ₁ is sent on the transmitting side and the received signal is at signal point a _i
The error signals E _p and E _q obtained by the demodulator 2 are also correct error signals when correctly identified as signals in the region of, but they are correct when incorrectly identified as signals in the region of the signal point b _ij. The generation of the error signals E _p and E _q cannot be expected.
The same can be said when the signals at the signal points a ₂ , a _3, and a ₄ are transmitted on the transmitting side. The all-equalization control algorithm uses the error signal E _p
Since generating a weighting control signal _{R m ~R -m · I m ~I} -m using E _q loses equalization ability.

Next, as can be seen from FIG. 3, in the circle passing through the signal point b _ij , the total length of the arc passing through the area of the signal point a _i is much shorter than the total length of the arc passing through the area of the signal point b _ij . When the signal at the signal point b _ij is transmitted on the transmitting side when the carrier wave is asynchronous, the probability that the received signal is erroneously identified as the signal in the region at the signal point a _i is extremely small.

Almost same as the above description of the case where the signal of the signal points a _i or signal points b _ij at a carrier asynchronous is being transmitted on the transmission side, vice even when replacing the signal points a _i signal point c _i .

The partial equalization algorithm, the received signal signal point a _i or weighting control signal using the error signal E _p · E _q obtained when it is identified as a signal of the region of signal points c _i R _m ~R _{- m}
- generating a I _m ~I _-m, error signal E _p · E _q weighting control signals R _m to R _-m · using a false identified as a signal of a region of the received signal erroneously signal points b _ij Since I _{m to} I _-m are prevented from being generated, it is possible to generate control signals R _{m to} R _-m · I _{m to} I _-m with few errors even when the carrier wave is asynchronous.

As described above, the equalizer 5 has the equalizing ability even when the carrier waves are not synchronized, so that the demodulator 2 has an excellent carrier synchronization pull-in characteristic. However, the error signal E _p · E _q at the sampling point where the received signal is identified as a signal in the region of signal point b _ij
Is not used to generate the control signals R _m ~ R _-m・ I _m ~ I _-m , so the equalization characteristic of the partial equalization control algorithm is better than that of the full equalization control algorithm as long as the carrier synchronization is pulled in. Inferior.

As described above taking the total equalization control algorithm and the partial equalization algorithm as examples, the equalizer control algorithm has excellent equalization characteristics but poor demodulator carrier synchronization pull-in characteristics. Such a control algorithm will be referred to as the first control algorithm), and one having poor equalization characteristics but excellent pull-in characteristics (such a control algorithm will be referred to as the second control algorithm). No control algorithm is known that has excellent equalization and pull-in characteristics.

[Problems to be solved by the invention]

Since the conventional equalizer uses one of the first and second control algorithms described above, when the equalization characteristic is excellent, the carrier synchronization pull-in characteristic of the demodulator is inferior and the pull-in characteristic is poor. When it is excellent, there is a drawback that the equalization characteristic is poor.

An object of the present invention is to solve the above-mentioned drawbacks and provide an equalization circuit having excellent equalization characteristics and pull-in characteristics.

[Means for solving problems]

An equalizer according to the present invention reproduces a carrier signal in synchronization with a carrier wave to a digital modulated signal, and demodulates the digital modulated signal with the carrier signal as a reference to obtain a data signal. An equalizer for equalizing a signal in an intermediate frequency band or a baseband of the demodulator by a weighted control signal obtained by operation, wherein the equalization performance is excellent as the algorithm, but the carrier synchronization pull-in characteristic of the demodulator is used. Is inferior to the first control algorithm, and the equalization performance is inferior but has the second control algorithm in which the pull-in characteristic is excellent, and the first when the code error rate of the demodulator is better than a predetermined value. When the control value is worse than the predetermined value, the second control algorithm is used. To be done.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram showing a receiving system using an embodiment of the equalizer of the present invention.

The receiving system shown in FIG. 1 includes an equalizer 1 which is an embodiment of the present invention, a demodulating device 2, a received signal processing device 3 and a code converting device 4, and FIG. The equalizer 5 of the receiving system shown in (3) is replaced with the equalizer 1, and the error rate signal S ₂ output from the received signal processing device 3 is input to the equalizer 1.

The receiving system shown in FIG. 1 is also a receiving system of a digital radio communication system using the 16-ary quadrature amplitude modulation method.

The equalizer 1 includes a transversal filter 10 and a weighting control signal generation circuit 11 that receives the data signal and the error rate signal S ₂ and outputs the weighting control signals R _{m to} R _-m · I _{m to} I _-m. It is equipped with.

The weighting control signal generation circuit 11 includes the first control algorithm and the second control algorithm already described, and when the error rate signal S ₂ is not input, the first control algorithm is used to input the error rate signal S _2. If so, the second control algorithm logically operates the data signal to generate the weighting control signals R _{m to} R _-m · I _{m to} I _-m . The transversal filter 10 is controlled by the weighting control signals R _{m to} R _−m · I _{m to} I _−m to equalize the IF signal I ₁ into the IF signal I ₂ .

The operations of the demodulator 2, the received signal processor 3, and the code converter 4 are the same as in the receiving system shown in FIG.

If the code error rate is better than the predetermined value, the error rate signal S ₂ is not output, and therefore the equalizer 1 uses the first control algorithm. In this case, the equalizer 1 has excellent equalization characteristics. . In this case, since the quality of the IF signal I ₂ is good, there is no possibility that the carrier wave synchronization of the demodulator 2 will be lost.

When the carrier wave synchronization of the demodulator 2 is lost, the code error rate is extremely deteriorated and the error rate signal S ₂ is output. Since the equalizer 1 uses the second control algorithm, the carrier wave synchronization pull-in characteristic is excellent. ing.

If the code error rate is lower than a predetermined value and the carrier synchronization of the demodulator 2 is pulled in, the quality of the IF signal I ₂ is deteriorated and the carrier synchronization may be lost. 1 uses the second control algorithm to provide carrier synchronization loss. In this case, since the code error rate is deteriorated below a predetermined value, it is permissible that the equalization characteristic of the equalizer 1 is slightly deteriorated by using the second control algorithm.

As described above, the equalizer 1 has excellent equalization characteristics, and the demodulator 2 also has excellent carrier synchronization pull-in characteristics.

Although the embodiments of the present invention have been described with respect to the case where the 16-valued quadrature amplitude modulation wave is equalized in the IF band, the present invention can be applied to any case of the modulation method of the digital modulation wave.

The present invention can also be applied to an equalizer that equalizes a baseband signal of a demodulation device that demodulates a digital modulated wave. There is a method of using a data signal as a carrier wave synchronization method, and if the present invention is used for an equalizer that equalizes a baseband signal of a demodulator that adopts such a carrier wave synchronization method, the present invention that equalizes in the IF band, etc. It has the same effect as a chemical device.

〔The invention's effect〕

As described in detail above, the equalizer of the present invention has a control algorithm having excellent equalization characteristics and a control algorithm having excellent carrier synchronization pull-in characteristics of the demodulator, and controls both depending on whether the bit error rate is good or bad. Since we use different algorithms,
There is an effect that the equalization characteristic is excellent and the pull-in characteristic when the carrier synchronization of the demodulator is out of sync is also excellent.

[Brief description of drawings]

FIG. 1 is a block diagram showing a receiving system using an embodiment of an equalizer of the present invention, and FIG. 2 is a block diagram showing a general example of a receiving system using an example of a conventional equalizer. FIG. 3 is an explanatory diagram showing the arrangement of signal points in the 16-ary quadrature amplitude modulation method. 1 ... Equalizer, 2 ... Demodulator, 3 ... Received signal processor, 10 ... Transversal filter, 11 ... Weighting control signal generation circuit, 21 ... Carrier synchronization circuit, 22 ... Quadrature detection circuit , 2 _p・ 2 _q …… Identification circuit.

Claims (1)

[Claims] 1. A carrier signal is reproduced in synchronism with a digital modulated signal, and the data signal of a demodulator which obtains a data signal by demodulating the digital modulated signal with this carrier signal as a reference is logically operated by a control algorithm. In an equalizer for equalizing the signal in the intermediate frequency band or the baseband of the demodulator by the obtained weighting control signal, as the algorithm, the equalization performance is excellent but the carrier synchronization pull-in characteristic of the demodulator is poor. One control algorithm and a second control algorithm that is inferior in the equalization characteristic but excellent in the pull-in characteristic, and the first control algorithm when the code error rate of the demodulator is better than a predetermined value. Is used, and when the value is worse than the predetermined value, the second control algorithm is used. vessel.