JPH0748203B2 - Square matrix multiplier using three-dimensional device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a matrix multiplier, and more particularly to a configuration of a square matrix multiplier using a three-dimensional device for performing multiplication of a square matrix at high speed.

[Problems to be Solved by Prior Art and Invention] One of the numerical operation processes in scientific calculation is multiplication of a square matrix. Conventionally, such multiplication of a square matrix has been performed according to software using a computer. However, when performing square matrix multiplication by software, steps of reading data from a memory or a register, multiplying and adding read data, and storing an operation result in a memory or a register are inevitably required. There is a problem that the calculation time becomes long and high-speed processing cannot be performed.

On the other hand, when a hardware-discrete matrix arithmetic unit is configured by using a scalar arithmetic unit or the like, the number of wires connecting each arithmetic unit increases according to the number of elements of the matrix, and the device configuration is large-scale. It becomes complicated again. Furthermore, the wiring length from the data (matrix element) input circuit to the operation result (multiplication result) output circuit becomes long, signal propagation delay occurs, and it becomes impossible to perform matrix multiplication at high speed.

Therefore, it has been strongly desired to realize a square matrix multiplier having a compact structure capable of performing matrix calculation at high speed by a hardware structure.

The present invention has been made in view of the above technical background, and an object of the present invention is to provide a square matrix multiplier having a compact structure capable of performing multiplication of a square matrix at high speed.

[Means for Solving the Problem] A square matrix multiplier according to the present invention includes a plurality of storage elements arranged in rows and columns, each storing a corresponding element of a first square matrix. Storage means and a second storage means arranged in rows and columns, each comprising a plurality of storage elements for storing corresponding elements of a second square matrix, and arranged in rows and columns, each of the above A third storage unit including a plurality of storage elements for storing corresponding elements of the multiplication results of the first square matrix and the second square matrix; and the first storage unit of the first square matrix of the first storage unit. The storage element position for storing the element of the i-th row and the k-th column (both i and k are natural numbers) and the storage element position for storing the k-th row and the j-th column element of the second square matrix in the second storage means are respectively set. The specified information is generated and the i of the third storage means is generated. Pointer means for generating information indicating the storage element position of row j column, means for reading and multiplying the storage element contents of the first and second storage means designated by the pointer means, the output of the multiplying means and the above Adder means for adding the storage element content of the third storage means designated by the pointer means and storing the addition result in the same storage element of the third storage means designated by the pointer means; And the first, second and third storage means, the pointer means, the multiplication means and the addition means are formed on a plurality of semiconductor layers laminated on the same substrate to form a three-dimensional device. It is composed.

Preferably, the first storage means is configured so that each row is composed of a shift register and the contents of each shift register are cyclically shifted in the row direction.

Further, preferably, the second storage means is composed of a shift register, and the contents of the shift register are arranged to cyclically shift in the column direction.

Still further, preferably, the column-direction shift operation of the second storage means is performed once in the column direction when the row-direction shift in the first storage means makes one cycle through the elements of each row. To be configured.

Further, the shift register of the first storage means is designated by the pointer means so that the storage element contents on the diagonal of each storage element are read out, and this state is set to the initial state.

[Operation] Since the functional blocks required for performing matrix multiplication are stacked to form a three-dimensional device, it is possible to arrange corresponding elements of the functional blocks so as to overlap each other when seen in plan view. Unlike the discrete configuration, the connection wiring between each functional block does not need to be taken out to the outside, and can be configured with only internal wiring, and the number of wiring and wiring length can be set to the minimum required values. In addition, it is possible to obtain a high-speed square matrix multiplier having a compact structure without causing the internal wiring to be complicated. In particular, by configuring the first and second storage means using shift registers, the connection wiring between each element of different matrices and the selection configuration of each element become the simplest configuration and minimize the wiring length. It becomes possible.

[Embodiment of the Invention] FIG. 1 is a diagram showing an overall schematic configuration of a square matrix multiplier according to an embodiment of the present invention, which is a multiplication of 4 × 4 (4 rows × 4 columns) square matrices A and B. FIG. 3 is a diagram showing, as an example, a case where a configuration for performing is realized by a three-dimensional device having a six-layer structure.

Referring to FIG. 1, a square matrix multiplier using a three-dimensional device according to the present invention includes a first storage block 1 and a second storage block 1.
Storage block 2 and the first and second storage blocks 1,
From the pointer block 3 that generates the position information of the storage element to be accessed in 2 and the position information of the storage element to be accessed in the third storage block 6, and the first and second storage blocks 1 and 2. A multiplier block 4 for multiplying the read information; an adder block 5 for adding the output of the multiplier block 4 and the contents of the storage element designated by the pointer block 3 in the third storage block 6; A third storage block 6 for storing the output of the functional block 5 and a control signal generation block 7 for generating a timing control signal for controlling the operation in each functional block. The first storage block 1 stores each element of a square matrix A of 4 rows and 4 columns. The second memory block 2 stores each element of the square matrix B of the second 4 rows and 4 columns. The pointer block 3 generates storage element position information storing an element to be multiplied of the first and second square matrices A and B, and a third storage block in which the multiplication result is stored. The storage element position information in 6 is generated. The multiplier block 4 multiplies selected elements of the first square matrix A and the second square matrix B, and supplies the result to the adder block 5. The adder block 5 adds the result multiplied by the multiplier block 4 and the information from the storage element of the third storage block selected by the pointer block 3, and the addition result is the original storage element position. Store to. The third storage block 6 stores the multiplication result of the first square matrix A and the second square matrix B in correspondence with each matrix element.

The control signal generation circuit 7 counts the clock signal CLK and generates a pulse signal each time the count value reaches 4, 8 and 12, and a hexadecimal counter 71 outputs 4 counts and 8 counts. A 3-input OR gate 72 for receiving 12 and 12 count outputs, an inverter 73 for inverting the output of the OR gate 72, an AND gate 74 for receiving the clock signal CLK and the output of the inverter 73, an OR gate 72 output and a clock signal C
AND gate 75 for receiving LK. The output of the AND gate 74 provides the shift operation timing signal in the first storage block 1. The output of the AND gate 75 is the second storage block 2
The shift operation timing signal is given. The clock signal CLK gives a shift operation timing in the pointer block 3 and a data read and write operation timing signal in the third memory block 6. The hexadecimal counter 71 is reset in response to the reset signal RESET. This reset signal RESET is the first
Selection signal SELE for selecting data update and cyclic operation in the memory block 1 and the second memory block 2 of
Used as CT. The reset signal RESET is also used as a reset signal in the pointer block 3 and the third storage block 6.

In the above configuration, the respective functional blocks 1 to 6 are laminated on the same substrate to form a three-dimensional device. This first
In the illustrated embodiment, each functional block 1-6
Are formed in different semiconductor layers to form a 6-layer three-dimensional device. The control signal generation circuit 7 is provided as an external circuit, or provided on the same semiconductor layer as any of the functional blocks.

The structure of the three-dimensional device as described above is SOI (silicon
On-insulator) technology can be used. Therefore, the wirings between the respective functional blocks are connected via the via holes provided in the insulating layer separating the semiconductor layers in which the respective functional blocks are provided. Next, a specific configuration of each functional block will be described with reference to FIGS. 2 to 7.

First, the configuration of the first memory block will be described with reference to FIG. Referring to FIG. 2, first storage block 1 stores registers A11 to 411 arranged in a matrix of 4 rows and 4 columns in order to respectively store respective elements of a square matrix of 4 rows and 4 columns. Equipped with A44. The register Aij stores the i-th row and j-th column component of the matrix A as an initial state. Register Ai1 for each row
Ai4 (i = 1 to 4) form a shift register that can cyclically shift in the row direction. The contents of each register Aij are shifted bit by bit in the adjacent shift register in response to the rising edge of the shift signal SHIFT. The input unit of each row is provided with a selector 12 for selecting whether to receive new data a _i or to pass the already stored matrix element data in a circular manner. The select signal SELECT controls the operation of the selector 12 to pass new data or cyclic data. The output of each register Aij is transmitted to the pointer block of the third layer. Since the shift signal SHIFT given to the first memory block 1 is given by ANDing the output of the inverter 73 and the clock signal CLK, the register contents are shifted by 1 bit in the row direction at each rising edge of the clock signal CLK. , 4th
No shift operation occurs at the second clock.

FIG. 3 is a diagram showing a specific configuration of the second memory block. Registers B11 to B44 are arranged in a matrix of 4 rows and 4 columns so as to store each element of the 4 × 4 second square matrix B. Are arranged. The register Bij of the second memory block is provided so as to correspond to the register Aij of the first memory block, but in the configuration shown in FIG. 3, the register Bij is arranged so that the memory contents can circulate in the column direction. Is configured. That is, in the first storage block shown in FIG. 2, shift registers are arranged in the row direction, while in the second storage block shown in FIG.
Two shift registers are constructed. The data input section of each column responds to the select signal SELECT with new data bi.
Is provided, or a selector 22 is provided which performs either operation of inputting or passing through the matrix element data already written. The selector 22 selectively passes the cyclic data when the select signal SELECT is “L”, and selectively passes the new data bi when the select signal SELECT is “H” level. The configuration and operation of this selector 22 is the second
It is similar to the selector 12 shown in the figure. Each register Bij
The output is transmitted to the pointer block in the third layer. The contents of the register Bij are shifted in the direction of the 1-bit string every 4 clocks.

FIG. 4 is a diagram showing a specific structure of the pointer block, and four sub blocks P1 to P4 having the same structure are provided corresponding to each column. The pointer sub-block P1 corresponding to the first row is composed of a 4-bit shift register capable of cyclic shift in the row direction. The register P1i in this sub-block P1 is the first register in the first memory block.
Which register output of the registers in the row is selected to be sent to the fourth layer, and which register output of the first row of the second storage block in the second layer is selected and transmitted to the fourth layer And which register output of the register outputs of the third memory block included in the sixth layer is selected and transmitted to the adder block of the fifth layer. In the sub-block P1 of the first row, each pointer register P1i output is connected to the gate of the switching transistor SW1i, and this pointer output is transmitted to the third storage block in the sixth layer. Select switch SW1i
Receives the register A1i output from the first storage block and the register B1i output of the second storage block. Register A1i of the first storage block and 1 of the second storage block
The data a to be multiplied by the multiplier block of the fourth layer by selecting the registers B1i (i = 1 to 4) in the row in pairs
Transmitted as 1, b1. In this structure, register outputs located in the same row and the same column in each memory block are transmitted to the fourth layer. Each pointer register is reset by the reset signal RESET, and its stored contents are shifted by one bit in the row direction in response to the shift signal SHIFT. This pointer block P1
The shift signal given to is a clock signal from control signal generating circuit 7, and therefore the contents of pointer register P1i are shifted by one bit in the row direction at each rising edge of each clock signal CLK. The other sub-blocks P2 to P4 have the same configuration, and from the sub-block P2, the registers A2i, B2i (i = 1 to 1) of the second row of the first and second storage blocks
4) are selected in pairs and transmitted to the multiplier block of the fourth layer. In the third sub-block P3, the register A3i in the third row of the first storage block and the register B3i in the third row of the second storage block are selected in a pair and the contents of the register are set to the fourth. It is applied to the layer multiplier. The fourth sub-block P4 selects the registers A4i, B4i in the fourth row of the first storage block and the second storage block and supplies the output to the multiplier of the fourth layer. Sub block P2-P4
The pointer output from is also applied to the third storage block in the sixth layer as well as the first sub-block P1. The timing of applying the reset signal and the shift signal in each block is the same as that of the first sub-block P1, and the same shift operation and reset operation are performed.

Further, in the above-mentioned pointer structure, the contents of each pointer are shifted by one bit in the row direction in response to the shift signal SHIFT, but in response to the reset signal RESET, each register is set as follows.

That is, at the time of reset, only the diagonal element registers are set to 1 in the configuration of 4 rows and 4 columns.

Referring to FIG. 5, the multiplier block is composed of multipliers MPY1 to MPY4 provided corresponding to each row. The multiplier MPY1 multiplies the data a1 and b1 of the first row selected by the pointer block (sub-block P1) of the third layer by the multiplication result.
Output m1 to the fifth layer adder block. The multiplier MPY2 likewise receives, via the third layer, the elements a2, b2 of the second row selected by the pointer block (more precisely, the sub-block P2),
The multiplication result m2 = a2 · b2 is output to the fifth layer adder block. Similarly, the multiplier MPY3 is the matrix element a3, b of the third row selected by the pointer block (sub-block P3) of the third layer.
The product of 3 is taken and the multiplication result m3 is given to the fifth layer adder block, and the multiplier MPY4 receives and multiplies the matrix elements a4 and b4 output selected by the pointer block P4, and the multiplication result m4
To the adder block of the fifth layer.

Referring to FIG. 6, the adder block includes adders ADD1 to ADD4 provided corresponding to the respective rows. The adder ADD1 is the first selected by the output m1 of the multiplier MPY1 of the fourth layer and the pointer (sub-block P1) of the third storage block of the sixth layer.
The register output C1-out of the row is received and added, and the addition result C1-in is stored again in the storage element of the original third storage block. Adder ADD2 is the fourth layer multiplier MPY2 output
m2 and the output selected by the pointer (sub-block P2) of the data in the second row of the third storage block in the sixth layer
C2-out is added, and the addition result C2-in is stored again in the original storage element position. The adder ADD3 is the fourth layer multiplier MPY3
Output m3 and register output selected by the pointer (sub-block P3) of the elements in the third row of the third storage block
C3-out output is added, and the addition result C3-in is written again to the selected memory element position. The adder ADD4 adds the output MP4 of the multiplier MPY4 of the fourth layer and the output C4-out output selected by the pointer (sub-block P4) of the register outputs of the fourth row of the third storage block, The result of this addition
The C4-in is stored again in the original storage element position in the fourth row of the original third storage block.

The configuration of the third storage block 6 will be described with reference to FIG. The third memory block 6 is composed of blocks C1 to C4 provided for each row. Each block C1 ~
C4 has the same configuration, and each block has four registers Cij. The input / output unit of each register Cij is turned on in response to the pointer output Pij output from the third layer, and the input unit of the corresponding register Cij is coupled to the corresponding adder output of the fifth layer and the register Cij output is output. Switch TS that couples a section to the input of the corresponding adder
ij is provided. Each register Cij outputs its contents in response to the rising edge of the clock signal CLK, and the clock signal CL
The supplied data is written in response to the fall of K, and it is reset in response to the transition of the reset signal RESET to "H" level, and the contents of each register Cij are cleared. In this configuration, each of the blocks C1 to C4 exchanges data with the corresponding adders ADD1 to ADD4.

FIG. 8 is a diagram showing a configuration of the multiplier using the three-dimensional device described with reference to FIGS. 2 to 7, taken along the i-th row. As can be seen from FIG. 8, the square matrix multiplier has a b-layer three-dimensional device structure, so that the corresponding constituent elements in each row can be vertically stacked so that they overlap each other in plan view. It is possible to arrange the circuit structure in a simple manner, and the wiring connecting each circuit configuration is not complicated, and the number of wirings is minimized to achieve a compact configuration.
A dimensional structured square matrix multiplier has been implemented. With the above configuration, the wiring length from each matrix element storage portion to the storage portion for storing the multiplication result can be minimized, and since each circuit configuration is configured by hardware, high-speed multiplication can be performed. Is possible.

Next, the operation of the square matrix multiplier according to the embodiment of the present invention will be described with reference to FIGS. Here, FIG. 9 shows an operation waveform diagram, and FIG. 10 specifically shows a shift operation of register contents in the first memory block and the second memory block.

(1) Initial setting First, the reset signal RESET is set to "H" level. As a result, the selectors 12 and 22 are in a state of respectively passing the data newly given from the outside. Next, the values of the data a1 to a4 and the data b1 to b4 corresponding to the elements of the matrices A and B to be calculated are set, and the first storage block 1 and the second storage block 2 are responsive to the clock signal CLK. The values of the corresponding elements of the matrices A and B are set in the respective registers Aij and Bij of. This state is shown as an initial state in FIG. Now, the reset signal RESET is at "H" level, the register Cij in the third storage block 6 and the hexadecimal counter 71 are cleared, and the stored contents and the counter value are zero.
At the same time, the pointer register Pij included in the pointer block 3 is set so that only its diagonal element, that is, only Pii outputs the "H" level. In FIG. 10, the part above the broken line shows the matrix B, that is, the initial setting state of each register of the second memory block in the second layer and the shift operation thereafter, and the part below the broken line shows the first part.
7 shows the shift operation of each element of the matrix A in the memory block of FIG. Therefore, in the initial setting state,
The state shown as the initial value in the figure is the register Aij,
It is set to Bij. Since the pointer register Pij is reset by the reset signal RESET,
In the figure, the output of the part indicated by underlining below the number is selected. Here again, in FIG. 10, in the configuration of 4 rows and 4 columns, the position of row i and column j represents each register Aij, Bij, and the number (kl) shown at each position is the input matrix. Represents the element of row k and row 1.

(2) Multiply Reset signal RESET is set to "L" level and clock signal CLK
Is operated to perform matrix multiplication in response to the clock signal CLK.

First, the reset signal RESET is set to "L". As a result, the selectors 12 and 22 do not accept the external data, and circulate the internal data. Further, all the switches SWii that receive the pointer Pii output on the diagonal line in the pointer block are turned on, and the diagonal element aii from the first storage block and the diagonal element bii of the second storage block are output to the multiplier. Given. Multiplier MPY1 to MPY4
Respectively apply the given matrix elements to the fifth layer adder. Since the diagonal part of Cii is selected in response to the pointer register output in the register included in the adder block, the outputs of the adders ADD1 to ADD4 are ADD1 = a11 x b11 + c11 ADD2 = a22 x b22 + c22 ADD3 = a33 x b33 + c33 ADD4 = A44 x b44 + c44. When the clock signal CLK falls to "L", the corresponding value is written in the register Cii of the third memory block,
It is latched there. In response to the fall of this clock signal, the count value of the hexadecimal counter 71 is incremented by 1 and becomes 1.

When the clock signal CLK rises again, in response thereto, the contents of the register Aij in the first storage block are shifted bit by bit in the row direction. At the same time, the output of the pointer register Pij included in the pointer block is also shifted by one bit in the row direction. As a result, the storage contents of the register Aij in the first storage block will be in the state shown in FIG. On the other hand, the storage content of the storage block 2 does not change because the shift signal is generated each time the count number of the hexadecimal counter 71 reaches 4. Therefore, the outputs of the adders ADD1 to ADD4 are ADD1 = a11 * b12 + c12 ADD2 = a22 * b23 + c23 ADD3 = a33 * b34 + c34 ADD4 = a44 * b41 + c41. When the clock signal CLK shifts to "L", these addition results are latched in the registers C12, C23, C34, C41 of the third storage block selected by the pointer register, respectively. Further, the count value in the hexadecimal counter 71 is incremented by one and becomes 2.

Next, when the clock signal CLK shifts to "H", the first
The contents of the register Aij of the storage block 1 are shifted by 1 bit in the row direction, and the contents of the pointer register Pij are shifted by 1 bit in the row direction. At this time, the contents of the register Bij of the second storage block 2 are not shifted and the initial state is held. As a result, the pointer register Pi
The registers Aij, Bij, and Cij selected by j become the registers adjacent in the row direction to the registers selected in the step. Therefore, the output of the adder ADDi is ADD1 = a11 * b13 + c13 ADD2 = a22 * b24 + c24 ADD3 = a33 * b31 + c31 ADD4 = a44 * b42 + c42. When the clock signal CLK shifts to "L", the outputs of the adder ADDi are latched in the registers C13, C24, C31, C42 selected by the third pointer register Pij, respectively. The count value of the hexadecimal counter 71 becomes 3 in response to the change of this clock signal.

When the clock signal CLK becomes "H", the contents of the first memory block Aij are shifted by one bit in the row direction and the pointer is moved in the same manner as in the above steps, as shown in FIG. Register Pij output is also 1
Bitwise shifted in the row direction. At this time, since the count value of the hexadecimal counter 71 is still 3, the content of the register Bij in the second storage block 2 does not change. Therefore, the output of the adder ADDi is ADD1 = a11 * b14 + c14 ADD2 = a22 * b21 + c21 ADD3 = a33 * b32 + c32 ADD4 = a44 * b43 + c43. When the clock signal signal CLK shifts to "L", the outputs of these adders are written to the registers C14, C21, C32, C43 selected by the pointer registers, respectively, and latched there. In addition, the count value of the hexadecimal counter 71 is 1
Is incremented to 4 and becomes 4.

Next, when the clock signal CLK shifts to “H”, the shift signal of the first storage block 1 is transferred to the inverter 73 and the AND
It is not given by the action of the gate 74 and its stored contents do not shift. On the other hand, the shift signal SHIFT for the second memory block 2 is ORed in response to the rising of the clock signal CLK.
Generated by the output of the gate 72, the contents of the register Bij in the storage block 2 are shifted bit by bit in the column direction. The shift signal SHIFT of the pointer block 3 is a clock signal, and its contents are shifted bit by bit in the row direction. As a result, the contents of the registers Aij and Bij and the pointer register Pij are in the state shown in FIG.
The output of the adder ADDi is ADD1 = a12 x b21 + c11 ADD2 = a23 x b32 + c22 ADD3 = a34 x b43 + c33 ADD4 = a41 x b14 + c44. When the clock signal CLK shifts to "L", these adder outputs are respectively latched in the storage registers C11, C22, C33, C44 selected by the pointer register Pij. Further, the count value of the hexadecimal counter 71 is 5.

After repeating the above steps, the clock signal CLK is repeated 15 times.
By changing, Cij = Σa _ik b _kj , 1 ≦ i, k, j ≦ 4 is latched in the register Cij of the third memory block at the time when the 16th clock signal CLK falls. There is. Therefore, the product result of the square matrix A and the square matrix B is latched in the third storage block 6.

Although the above embodiment does not show the method of outputting the contents of the register Cij in the third storage block from this square matrix multiplier, the circuit configuration for outputting this multiplication result is in the application field of this multiplier. It is determined. That is, for example, if the register Cij of the third storage block has a shift register configuration as in the case of data input to the registers Aij and Bij in the first storage block and the second storage block, the multiplication result output is expressed in vector units. It becomes possible to output. When the data processing system exists in the seventh layer and the multiplication result is processed by the processing system, the output of the register Cij may be output in parallel to the seventh layer.

Further, in the above-described embodiment, the configuration in which the square matrix multiplier is realized by the six-layer three-dimensional device structure in which each functional block is formed in each semiconductor layer has been described. Even if the functional blocks are configured in one semiconductor layer and the matrix multiplier is realized by the three-dimensional device configuration including the semiconductor layers whose number is smaller than the number of functional blocks, the same effect as in the above embodiment can be obtained.

Furthermore, the timing signal generating circuit 7 may be provided outside the chip substrate in which this three-dimensional device is configured, or in the case of the configuration integrated on the same substrate, each functional block is configured. The degree of integration can be improved by integrating the semiconductor layer in any one of the existing semiconductor layers.

Furthermore, in the above embodiment, the 4 × 4 (4 rows × 4 columns) square matrix multiplication has been described. However, the square matrix multiplier according to the present invention is not limited to the order of 4, and square matrices of other orders may be used. Is also applicable.

[Effects of the Invention] As described above, according to the present invention, a functional block required for multiplication of a square matrix, that is, a first storage block that stores each element of the first square matrix, a second square matrix A second memory block for storing, a third memory block for storing each element of the square matrix of the multiplication result, and a position of a memory element for storing the element to be multiplied in the first memory block and the second memory block A pointer block for generating information and generating memory element position information of a third memory block for storing the multiplication result, and multiplying the memory element contents of the first and second memory blocks selected by the pointer block output The multiplication block, the multiplication result multiplied by the multiplication block, and the storage element contents of the third storage block designated by the pointer block are added together. In addition, since the addition block that stores the addition result in the original storage element position is stacked on the same substrate to form a three-dimensional device structure, a square matrix multiplier can be realized with a simple and compact configuration. Moreover, the wiring length and the number of wirings can be kept to the minimum necessary values, and a square matrix multiplier having a compact structure capable of performing high speed multiplication can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall schematic configuration of a square matrix multiplier which is an embodiment of the present invention. FIG. 2 is a diagram showing a schematic configuration of a first storage block for storing each element of the square matrix in the square matrix multiplier according to the embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a second storage block for storing each element of the second square matrix used in the square matrix multiplier according to the embodiment of the present invention. FIG. 4 is a diagram showing the structure of a pointer block used in a square matrix multiplier according to an embodiment of the present invention. FIG. 5 is a diagram showing a schematic configuration of a multiplier used in a square matrix multiplier according to an embodiment of the present invention. FIG. 6 is a diagram showing the structure of an adder block used in a square matrix multiplier according to an embodiment of the present invention. FIG. 7 is a diagram showing the configuration of a third storage block for storing the square matrix of the multiplication result used in the square matrix multiplier according to the embodiment of the present invention. FIG. 8 is a diagram showing the configuration of the i-th row of the square matrix multiplier according to the embodiment of the present invention. FIG. 9 is a waveform diagram showing the operation timing of the square matrix multiplier according to the embodiment of the present invention. FIG. 10 shows a first storage block and a second storage block in a square matrix multiplier according to an embodiment of the present invention.
FIG. 6 is a diagram showing a shift operation in the storage block and the pointer block of FIG. In the figure, 1 is a first storage block, 2 is a second storage block, 3 is a pointer block, 4 is a multiplier block, 5 is an adder block, 6 is a third storage block, and 7 is a block.
Is a control timing signal generation circuit, Aij (i, j = 1 to 4) is a register which is a storage element of the first storage block, and Bij
(I, j = 1 to 4) is a register which is a storage element in the second storage block, Cij (i, j = 1 to 4) is a register which is a storage element in the third storage block, and Pij (i, j = 1
~ 4) is a pointer register included in the pointer block, MPYi (i = 1 to 4) is a multiplier, ADDi (i = 1 to 4)
Is an adder, 12 and 22 are selectors for selecting whether to circulate data in the first and second storage blocks or input external data, and TSij (i, j = 1 to 4) is a third selector A transistor switch SWij (i, j = 1 to 4) for inputting / outputting to / from a register in the memory block is a switch for selecting a register of the first memory block and the second memory block. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A multiplier for multiplying first and second square matrices of n rows and n columns (n: natural number) arranged in rows and columns, each of which is the first square. First storage means including a plurality of storage elements for storing corresponding element data of a matrix and capable of cyclically shifting the storage data along the direction of the row, and arranged in rows and columns, Second storage means each including a plurality of storage elements for storing corresponding element data of the second square matrix, and capable of cyclically shifting the storage data along the column direction; And a third storage unit arranged in columns, each of which includes a plurality of storage elements for storing corresponding element data of a multiplication result of the first square matrix and the second square matrix; The i-th row and k-th column (1≤i≤n, 1≤ of the first square matrix of the storage means Position information of a storage element that stores element data of ≦ n) and a storage element that stores the element data of k row and j column (1 ≦ j ≦ n) of the second square matrix of the second storage means. To generate position information of the storage element at the i-th row and the j-th column of the third storage means, each of them cyclically shifts the retained information along the direction of the row. Pointer means including pointers of n rows for generating position information designating one column in each row, and the first and second storage means in response to the position information generated by the pointer means. And multiplying the output of the multiplying means and the content of the storage element of the third storage means designated by the position information from the pointer means, and An addition means for storing the addition result in the original storage element of the third storage means designated by the pointer means, and the first, second and third storage means, the pointer means, A square matrix multiplier using a three-dimensional device in which the multiplying means and the adding means are formed on a plurality of semiconductor layers stacked on the same substrate to form a three-dimensional device.