JPH0746897B2 - Redundant control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a redundant control device for controlling a conversion device such as a forward conversion device, an inverse conversion device, or a forward / inverse conversion device. .

[Conventional technology]

Redundancy of a control device in order to make a control system highly reliable has been actively performed in various fields. For example,
The automatic control device of 59-45603 has a triple control device, an intermediate value selection circuit is provided at the output stage of the control device, and the most probable signal among the output signals from the triple control device is selected to target device ( Device). The above control means is effective for a system that requires high reliability.

[Problems to be solved by the invention]

When the above redundant control means is applied to various kinds of inverse conversion devices (inverters), forward conversion devices (converters), or forward / inverse conversion devices, the following problems occur. First, FIG. 2 shows the relationship between the control device 5 and the inverse conversion device 6 according to the prior art. Various devices such as a transistor, a thyristor, and a gate turn-off thyristor can be applied as the switching element of the inverse conversion device 6. Here, an example using the transistors T _{R1 to} T _R4 is shown. Further, this is an example of a single-phase type inverse conversion device, and the gate signal applied to the base of each transistor has the timing shown in FIG.

On the other hand, the control device 5 inputs the signal from the sensor 1 to the tripled control circuits 2 to 4 to generate gate signals ai, bi, ci (i = 1 to 4) to the respective transistors, and select the intermediate value. Circuit Bi
Takes these intermediate values and extracts each of the transistors T _{R1 to} T _R4
Output the gate signals g1 to g4 to. Here, the intermediate value selection circuit selects and outputs the intermediate level signal of the three signals, but when the input signal is digital, this operation selects the intermediate signal in terms of timing. For example, it is assumed that the signals shown in FIGS. 4A, 4B, and 4C are input to the intermediate value selection circuit. Now for example, 0V logic "0", a logic "1" and 5V, until the time t _1, the output d since all the input signals are in the 0V also becomes 0V. Then, between the times t ₁ and t ₂ , one of the three input signals is 5V and the remaining two signals are 0V, so the output d is 0V. Between the times t ₂ and t ₃ , two input signals are 5V and one is 0V, so the output d is 5V. Since all the input signals are 5V from time t ₃ to time t ₄ , the output d is also 5V. Between time t ₄ and t ₅ , two input signals are 5V and one input signal is 0V, so output d
Remains at 5V. However, between time t ₅ and t ₆ , one input signal is 5V and the remaining two input signals are 0V, so the output d is 0V. The time t ₆ after that all the input signal is also output 0V since it is 0V. From the above, the output d can be selected as the input signal b, that is, the signal having an intermediate value in terms of timing.

By the way, if an intermediate value selection circuit that requires a power supply as described in the conventional example is applied to this intermediate value selection circuit, the output of the intermediate value selection circuit may suffer a stuck-at fault of logic "1", for example. In other words, the voltage of the power supply may be output as it is, or may be dropped and output from the intermediate value selection circuit. This fault occurs for example in the intermediate value selection circuit B4, the generation time, and Atsuta at time t _1, for example, Figure 3. As a result, the gate signal g4 does not become a waveform shown by the solid line at time t ₂ later become NaritsuPanashi a logic "1" as shown by a dotted line. Then the time t ₂ at transistor T _R1 and T _R4 are turned on simultaneously, there is a problem that a large current to a short circuit flows in both transistors T _R1, T _R4.

Further, when the output pulse of the intermediate value selection circuit is amplified by the pulse amplifier, the converter may be broken due to the influence of the failure of the pulse amplifier.

An object of the present invention is to provide an intermediate value selection circuit even if it fails,
It is an object of the present invention to provide a highly safe redundant control device in which the conversion device is not broken even if the pulse amplifier fails.

[Means for solving problems]

The above object is to provide a semiconductor device that constitutes each arm of a forward conversion device that converts alternating current to direct current, an inverse conversion device that converts direct current to alternating current, or a reverse conversion device that once converts alternating current to direct current and then reconverts it to direct current. The control signal applied to the gate
Pulse signals A, B, respectively output from the tripled control circuit
In a redundancy control device for selecting and generating any one of C by an intermediate value selection circuit, a pulse signal A and a pulse signal are respectively applied to the first, second and third transistors of the same type and the base and collector of the first transistor. A connection line for applying C, a connection line for applying the pulse signal C and the pulse signal B to the base and collector of the second transistor, and a connection signal for applying the pulse signal B and the pulse signal A to the base and collector of the third transistor, respectively. An intermediate value selection circuit is configured by a connection line and a signal line that commonly connects the emitters of the respective transistors, and a pulse amplifier that amplifies an output signal from the common connection signal line and a change in the output signal of the pulse amplifier And a pulse transformer that outputs only a portion, and the output signal of the pulse transformer is applied to the gate of the semiconductor element as the control signal. In, it is achieved.

[Action]

By adopting the above-mentioned configuration of the intermediate value selection circuit, that is, the non-power supply type, the stuck-at fault in which the power supply voltage is output as the control signal is eliminated, and the arm of the conversion device is not likely to be short-circuited. Also, even if the pulse amplifier fails and its output degenerates to "1", the output of the pulse transformer will not be kept at "1" unless the input signal changes, so the arm of the converter is There is no short circuit.

〔Example〕

Examples of the present invention will be described below. The parts with the same numbers in each figure indicate the corresponding parts. FIG. 1 is a block diagram showing an embodiment of the present invention. The conversion device 6 is a single-phase inverse conversion device (as a transistor arm), and the redundancy control device 5 is shown in FIG. It has a triple configuration similar to that of the above, except that the intermediate value selection circuits A1 to A4 are non-power supply type.

FIG. 5 shows an example of the structure of a powerless intermediate value selection circuit.
This uses NPN transistors 16 to 18, and can be applied when the input signal has a positive polarity (for example, 0 to 5 V). The diodes 19 to 21 are for preventing the breakdown of the transistors when a reverse voltage is applied between the base and the emitter of the transistors 16 to 18. It is assumed that the signals shown in FIG. 4 are applied as the inputs a, b, and c of the powerless intermediate value selection circuit. Each signal is logical “0” until time t _1.
Therefore, the output is also "0". In the period from time t ₁ to t _2, only the signal a has the logic “1”. As a result, the base of the transistor 16 is "1", the collector is "0",
Since the transistor is turned on, the collector voltage is output to the emitter almost as it is. Therefore, the emitter potential of the transistor 16 is "0". Transistors 17,18
Since both bases are both "0", their emitter potentials are "0" in the off state. That is, the output gi of the intermediate value selection circuit is “0” until time t ₂ . During the period from the time t ₂ to the time t ₃ , the base of the transistor 18 is “1” and the collector is “1”, so the transistor 18 outputs “1” in the ON state.
Since the base of the transistor 17 is "0", it is in the off state. Further, the transistor 16 has a base of "1", but the output of the transistor 18 is "1", whereby a reverse voltage is applied to the emitter, so that the transistor 16 is turned off. As a result, the output gi becomes "1". From time t ₃ to t ₄ , the output gi also becomes “1” because all inputs are “1”. In the same way, considering the state of the input signal, finally,
Output d in the figure, that is, an intermediate value can be selected.

Now, consider the failure mode of this non-power source type intermediate value selection circuit. First, it is assumed that all elements have failed in the short circuit mode. Since the outputs of the diodes 19 to 21 are connected to one point, if all the elements fail in the short-circuit mode, they are equivalently wired OR circuits (functionally AND). long as it summer as FIG. 4, the signal of logic "1" from the time t ₃ to t ₄ is output. That is, if the deviation of each input signal is within the allowable value in the operation timing of the switching element of the converter 6, the control is continued without any problem.

The same is true even if some elements fail. For example, assume that the transistor 18 has a short circuit failure. In this case, in FIG. 4, until the time t ₁ the input signal is "0" since "0" is output. From time t ₁ to t ₂ , since the input signal a is “1”, the output of the emitter becomes “1”, and via the diode 21,
"1" is output as is. From time t ₂ to t _4, this condition persists. Since the period from time t ₄ of t ₅ the input signal a is "0" emitter of the transistor 18 is "0", the operation of the transistor 16 and 17, indicate a logic "1",
The diode 21 is reverse-biased, and the emitter output “0” of the transistor 18 is not output. In this case, assuming that the diode 21 has also failed in the short circuit mode, the output becomes “0” after the time t ₄ . However, in either case, the output gi never goes to logic "1".

Next, when each element fails in the open mode, in this case, the signal is lost, that is, the output gi becomes “0”. Therefore, the logic "1" does not suffer the stuck-at fault.

As described above, the output of a non-power-supply type intermediate value selection circuit never becomes a logic "1" without any failure. This is because the output is determined only by the magnitude relationship of. If this intermediate value selection circuit is used, the transistors forming the arms of the conversion device 6 shown in FIG. 1 are not turned on at the same time, and the failure of the intermediate value selection circuit prevents the failure of the arm element.

It should be noted that the transistors on the market at present have a base-emitter voltage V _BE of several hundred mV instead of zero volt. Therefore, depending on the magnitude of the input signal, a low voltage may be output from the non-power-supply type intermediate value selection circuit by this voltage V _BE . As a result, the logic "1" never becomes "0", but the noise margin is reduced. In order to eliminate this voltage drop and increase the noise margin, the circuit described in the intermediate value selection circuit of Japanese Patent Laid-Open No. 59-14003, in particular, 6 NPN transistors are used to select the intermediate value for positive polarity signals.
The output part may be used.

Although the embodiment of FIG. 1 explained above is the case of the inverse conversion device, in the case of the forward conversion device, the control device 5 is the same, but instead of the inverse conversion device 6, the order of FIG. The conversion device 50 may be the control target. In this example, an AC voltage 55 is rectified by thyristors 51 to 54 which are switching elements, and a DC voltage is output between terminals 56 and 57. The redundant control device 5 of the present invention controls the firing angle of the thyristors 51 to 54 to control the DC voltage level.

Next, FIG. 7 shows an embodiment in the case of a forward / inverse converter.
The redundant control device 61 includes control circuits 62 to 64 for generating control gate pulses for both the forward conversion device and the inverse conversion device, and non-power supply type intermediate value selection circuits A1 to A4 (for the forward conversion device) and B1. ~ B4
Gate signals output by them (for inverse converter)
The g1 to g4 are applied to the gates of the thyristors 51 to 54, and the gate signals h1 to h4 are applied to the transistors T _{R1 to} T _R4 . here,
The DC reactor 58 is a smoothing filter, and the configuration shown in FIG. 7 is an example intended for a current type inverse conversion device. As described above, in the forward conversion device, the inverse conversion device, or the forward / inverse conversion device, by providing the non-power supply type intermediate value selection circuit in the output stage of the redundant control device, the intermediate value selection circuit fails. However, the arm of the switching circuit is not short-circuited, and the device as a whole can have high reliability.

Further, although each of the above embodiments is the case of the single-phase type, in the case of the three-phase type, a non-power-supply type intermediate value selection circuit may be provided corresponding to the number of switching elements required for this. .

FIG. 8 shows another embodiment of the present invention, and shows only the part of the redundancy control device 5 of FIG. In the present embodiment, the non-power-supply type intermediate value selection circuit is duplicated to provide two intermediate value selection circuits Ai1 and Ai2 for the gate signal gi for high reliability, and the outputs thereof are respectively output by the pulse amplifiers 311 to 342. After amplification, the signal is input to the signal selection circuit 35i via the pulse transformers 411 to 442, and one is selected by this selection circuit 35i to obtain the gate signal gi (i = 1 to 4). When the pulse amplifier is provided in this way, it always requires a power source, and as described above, the output may suffer a stuck-at fault of logic "1". For this purpose, a pulse transformer is provided in order to prevent arm element failure of the converter. Since the pulse transformer does not output a signal unless the input is changed AC-wise, the output of the pulse transformer 411 does not become "1" even if, for example, the pulse amplifier 311 has a stuck-at failure of logic "1".
If the non-power-supply type intermediate value selection circuit A12, the pulse amplifier 312, and the pulse transformer 412 which are redundantly provided are normal, the signal output from this is output to the switching circuit via the non-power-supply signal selection circuit 351. It The signal selection circuits 351 to 354 are arranged in the diode 36, 37 as shown in FIG. 9, for example.
It can be realized by a high value selection circuit consisting of.

FIG. 10 shows a powerless intermediate value selection circuit, a pulse amplifier,
An embodiment in which the pulse transformer section is tripled is shown, and the portion of the control device 5 in FIG. 1 is shown. It is needless to say that the intermediate value selection circuits A11 to A43 are all non-power supply type, and the signal selection circuits 361 to 364 may also be the non-power supply type high value selection circuit shown in FIG. Absent.

When using a pulse amplifier as shown in FIGS. 8 and 10, it is uneconomical to provide a power source for each pulse amplifier, and the amount of hardware increases. However, if this power supply is realized by one, the system will be down due to this power supply failure. Further, as shown in FIG. 12, in the dual system in which the outputs of the two power supply devices 72 and 73 are associated with each other through the diodes 70 and 71 and the output voltage is output to the terminal 74, a load (pulse amplifier) connected to the terminal 74 is connected. ) On the short-circuit side, a large current flows from the two power supply devices, both power supply devices become abnormal, and the power is lost. In order to eliminate such a common mode failure, the power supply devices 38 and 39 are provided corresponding to the redundant number of pulse amplifiers that are made redundant as shown in FIG. 11 (the redundant number in this case is 2). It is used as a power source for a pulse amplifier with redundant equipment. Specifically, for example, a power supply device
38 is connected to the pulse amplifier 311, ..., 341, and the power supply 39
Is connected to the pulse amplifiers 312, ..., 342. As a result, even if the power supply device 38 fails, for example, the control can be continued if the power supply device 39 and the pulse amplifiers 312, ..., 342 are normal. Further, even if the pulse amplifier 311 has a short circuit failure, control can be continued if other devices are normal. In this embodiment, the pulse amplifier has a dual system, but this is also the case when the number of redundant units is further increased. For example, when tripled as shown in FIG. 10, three power supply devices may be provided and connected in the same manner as in FIG.

〔The invention's effect〕

According to the present invention, the arm element short circuit of the converter does not occur due to the failure of the intermediate value selection circuit or the pulse amplifier. Therefore, the forward conversion device, the inverse conversion device, or the forward / inverse conversion device is made highly reliable. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional redundancy control device, and FIGS. 3 and 4 are operation explanatory diagrams of the device of FIG. 2 and FIG. Is a diagram showing a specific example of a non-power-supply type intermediate value selection circuit, FIG. 6 is a configuration diagram of a forward conversion device, FIG. 7 is a configuration diagram of a forward / inverse conversion device, and FIG. 8 is another embodiment of the present invention. A block diagram showing an example, FIG. 9 is a block diagram of the signal selection circuit of FIG. 8, FIG. 10 is a block diagram showing another embodiment of the present invention, and FIGS. 11 and 12 are power supplies for pulse amplifiers. FIG. 3 is an explanatory diagram of a supply method of. A1 to A4, B1 to B4, A11 to A43 ... No power source intermediate value selection circuit, 5
...... Control device, 6 …… Conversion device, 311-342 …… Pulse amplifier, 351-354 …… Non-power source type signal selection circuit, 411-443…
… A pulse transformer.

Claims (1)

[Claims] 1. A semiconductor element forming each arm of a forward conversion device for converting alternating current to direct current, an inverse conversion device for converting direct current to alternating current, or a reverse conversion device for once converting alternating current to direct current and then again converting it to direct current. Control signal applied to the gate of
Pulse signals A, B, respectively output from the tripled control circuit
In a redundancy control device for selecting and generating any one of C by an intermediate value selection circuit, a pulse signal A and a pulse signal are respectively applied to the first, second and third transistors of the same type and the base and collector of the first transistor. A connection line for applying C, a connection line for applying the pulse signal C and the pulse signal B to the base and collector of the second transistor, and a connection signal for applying the pulse signal B and the pulse signal A to the base and collector of the third transistor, respectively. An intermediate value selection circuit is configured by a connection line and a signal line that commonly connects the emitters of the respective transistors, and a pulse amplifier that amplifies an output signal from the common connection signal line and a change in the output signal of the pulse amplifier A pulse transformer that outputs only a portion is provided, and the output signal of the pulse transformer is applied to the gate of the semiconductor element as the control signal. Redundancy control apparatus according to claim.