JPH0746769B2 - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH0746769B2 JPH0746769B2 JP60248811A JP24881185A JPH0746769B2 JP H0746769 B2 JPH0746769 B2 JP H0746769B2 JP 60248811 A JP60248811 A JP 60248811A JP 24881185 A JP24881185 A JP 24881185A JP H0746769 B2 JPH0746769 B2 JP H0746769B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- fet
- circuit
- channel fet
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明はCMOS VLSIの出力回路に係り、特にモジユール
実装においてチツプ間の高速な信号伝送を行なうのに好
適なCMOS出力回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS VLSI output circuit, and more particularly to a CMOS output circuit suitable for high-speed signal transmission between chips in module mounting.
CMOS出力回路はデバイス性能の向上と、負荷駆動能力を
増すため、配線基板の伝送線路の特性インピーダンスに
比べて出力抵抗が低くなつている。一方、CMOS入力回路
は高入力インピーダンスであるため、伝送線路上に反射
ノイズが発生する。従つて、この反射ノイズが収まるま
で信号の受信を持つ必要があり、信号の伝搬遅延時間が
大きくなつていた。この対策として、特開昭59−208771
号に示されているような、入力回路にオーバシユートを
吸収する回路を挿入することが考えられているが、根本
的にきれいな伝送信号を得るためには、伝送線路を整合
終端する必要がある。従来、バイポーラLSIでは伝送線
路の受端に終端抵抗をつけて高速な信号伝送を可能にし
ているが、終端抵抗での消費電力が大きく、これをCMOS
LSIに適用するとCMOS回路の最大の特長である低電力な
利点を生かせない。一方、公表特許昭60−500355号には
出力回路の出力インピーダンスを伝送線路の特性インピ
ーダンスにほぼ等しくすることにより、受端からの反射
信号が送端で再び反射することを防止した回路が開示さ
れている。しかし、終端抵抗を出力回路の出力インピー
ダンスで代用する方法では、素子の製造上のバラツキの
ために出力インピーダンスが±50％近く変動し、従つて
反射信号を吸収するには不十分であつた。CMOS output circuits have lower output resistance than the characteristic impedance of the transmission line of the wiring board because of improved device performance and increased load driving capability. On the other hand, since the CMOS input circuit has a high input impedance, reflection noise occurs on the transmission line. Therefore, it is necessary to receive the signal until the reflection noise subsides, and the propagation delay time of the signal increases. As a countermeasure against this, Japanese Patent Laid-Open No. 59-208771
Although it is considered to insert a circuit that absorbs overshoot into the input circuit as shown in No. 1, it is necessary to match-terminate the transmission line in order to obtain a fundamentally clean transmission signal. Conventionally, a bipolar LSI has been equipped with a terminating resistor at the receiving end of the transmission line to enable high-speed signal transmission, but power consumption at the terminating resistor is large,
When applied to LSI, the advantage of low power, which is the greatest feature of CMOS circuits, cannot be utilized. On the other hand, Japanese Patent Laid-Open No. 60-500355 discloses a circuit in which the output impedance of the output circuit is made substantially equal to the characteristic impedance of the transmission line to prevent the reflected signal from the receiving end from being reflected again at the transmitting end. ing. However, the method of substituting the terminating resistor with the output impedance of the output circuit causes the output impedance to fluctuate by about ± 50% due to variations in the manufacturing of the element, and is therefore insufficient to absorb the reflected signal.
本発明の目的は低電力で高速な信号伝送を可能にする送
端終端方式のCMOS出力回路を提供することにある。An object of the present invention is to provide a CMOS output circuit of a transmission end termination system which enables high speed signal transmission with low power consumption.
本発明は出力回路に伝送線路を接続して出力信号を切換
えた時に、常に出力信号振幅の1/2の振幅の信号が伝送
線路に入射されるように、出力回路の出力抵抗を素子の
製造バラツキや電源電圧変動・温度変動にかかわらず補
償できる回路を付加したものである。これにより伝送線
路の送端から出力回路の出力信号振幅の1/2の振幅の入
射波が進行し、開放受端で反射され（従つて出力回路の
信号振幅が受端で得られる）、反射波が送端にもどつて
きて先端の信号振幅も出力回路の信号振幅に等しくなる
ので、次の送端での反射はおきない。According to the present invention, when the transmission line is connected to the output circuit and the output signal is switched, the output resistance of the output circuit is manufactured so that a signal having an amplitude half the output signal amplitude is always incident on the transmission line. A circuit that can compensate for variations, power supply voltage fluctuations, and temperature fluctuations is added. As a result, an incident wave with an amplitude half the output signal amplitude of the output circuit travels from the transmission end of the transmission line and is reflected at the open receiving end (thus, the signal amplitude of the output circuit is obtained at the receiving end) and reflected. Since the wave returns to the sending end and the signal amplitude at the tip becomes equal to the signal amplitude of the output circuit, there is no reflection at the next sending end.
以下、本発明の一実施例を第１図により説明する。第１
図において、１がＰチヤネルの出力MOS FET、２がＮチ
ヤネルの出力MOS FETである。各々直列に接続されたMOS
FET3〜5,6〜８は出力MOS FET1,2を駆動するドライブ回
路9,10を構成し、3,4,6がＰチヤネルMOS FET、5,7,8が
ＮチヤネルMOS FETである。MOS FET3,5,6,8のゲート電
極は出力回路の入力端子11に接続され、MOS FET4,7のゲ
ート電極は各々制御電圧発生回路12の出力に接続され
る。ドライブ回路９の出力はPMOSFET3のドレイン電極と
PMOS FET4のソース電極の接続点からとり出され、PMOS
FET1のゲート電極に接続される。ドライブ回路10の出力
はNMOS FET7のソース電極とNMOS FET8のドレイン電極の
接続点からとり出され、NMOS FET2のゲート電極に接続
される。出力回路の出力端子13はPMOS FET1とNMOS FET2
のドレイン電極に接続される。VDDは電源端子である。
制御電圧発生回路12はＰチヤネルMOS FET14,15、Ｎチヤ
ネルMOS FET16,17、抵抗18〜21、差動増幅器22,23から
成り、PMOS FET15とNMOS FET17はチツプ上に形成された
FETの特性をモニタするためのFETであり、MOS FET1,2,1
5,17のゲート幅を各々W1，W2，W15，W17とし、出力回路
の出力端子13に接続される伝送線路の特性インピーダン
スをZ0とすると、抵抗18の値は 抵抗19の値は である。PMOS FET15のドレイン電極と抵抗18の接続点は
差動増幅器22の正相入力に接続され、NMOS FET17のドレ
イン電極と抵抗19の接続点は差動増幅器23の正相入力に
接続される。また、抵抗20と21はその抵抗値が等しく、 の電圧を差動増幅器22,23の反転入力に供給する。差動
増幅器22,23の出力は各々MOS FET14,16のゲート電極に
接続され、MOS FET14,16のソース電極は各々MOS FET15,
17のゲート電極に接続される。制御電圧発生回路12の働
きをPMOS FET4のゲート電極へ出力を発生している側を
例に説明する。今、PMOS FETがtypical値よりもドレイ
ン電流が多く流れるように仕上がつているとすると、PM
OS FET15のドレイン電極の電位が上がり、差動増幅器22
の出力の電位が上がつて、PMOS FET14のゲート電極の電
位が上がるので、PMOS FET14のソース電極の電位すなわ
ちPMOS FET15のゲート電極の電位が上がり、ドレイン電
流が減少する。差動増幅器22の利得が十分高ければ、そ
の正相入力と反転入力の電位がほぼ等しくなるようにフ
イードバツクされるので、PMOS FET15のドレイン電極の
電位はほぼ に保たれ、PMOS FET15のドレイン電流はそのFET特性の
バラツキにかかわらず一定量 になるように制御される。逆に、 PMOS FETがtypical値よりもドレイン電流が少なく流れ
るように仕上がつている場合も、PMOS FET15はゲート電
極の電位が下がつて、ドレイン電流がtypicalの設計値
にほぼ等しくなるように制御される。このような制御電
圧発生回路の出力をPMOS FET4のゲート電極に印加する
ことにより、出力回路の入力端子11への入力信号が高レ
ベル（VDD）の場合にはPMOS FET3がしや断、NMOS FET5
が導通しているので、NMOS FET5のドレイン電極の電位
すなわちPMOS FET4のドレイン電極の電位は接地電位に
なり、チツプ内のMOS FETの特性のバラツキはチツプ間
のバラツキに比べて十分小さいので、PMOS FET1のゲー
ト電極の電位はPMOS FET15のゲート電極の電位に等しく
なる。一方、出力回路の入力端子11への入力信号が低レ
ベル（0V）の場合にはPMOS FET3が導通、NMOS FET5がし
や断しているので、PMOS FET1のゲート電極の電位はVDD
となる。従つて、出力端子13に特性インピーダンスZ0の
伝送線路を接続し、出力回路の入力端子11へ低レベルか
ら高レベルに変化する入力信号を印加する（初期状態で
出力端子13は接地電位とする）と、FET特性のバラツキ
にかかわりなく、 の電流を伝送線路に流し込むことができ、 の振幅の第１波を伝送線路に入射することができる。An embodiment of the present invention will be described below with reference to FIG. First
In the figure, 1 is a P-channel output MOS FET, and 2 is an N-channel output MOS FET. MOS connected in series
FETs 3 to 5, 6 to 8 form drive circuits 9 and 10 for driving the output MOS FETs 1 and 2, 3, 4 and 6 being P channel MOS FETs and 5, 7 and 8 being N channel MOS FETs. The gate electrodes of the MOS FETs 3, 5, 6, 8 are connected to the input terminal 11 of the output circuit, and the gate electrodes of the MOS FETs 4, 7 are connected to the output of the control voltage generating circuit 12, respectively. The output of the drive circuit 9 and the drain electrode of PMOSFET 3
It is taken out from the connection point of the source electrode of PMOS FET4,
Connected to the gate electrode of FET1. The output of the drive circuit 10 is taken out from the connection point of the source electrode of the NMOS FET7 and the drain electrode of the NMOS FET8 and connected to the gate electrode of the NMOS FET2. The output terminal 13 of the output circuit is PMOS FET1 and NMOS FET2
Connected to the drain electrode of. V DD is a power supply terminal.
The control voltage generation circuit 12 is composed of P-channel MOS FETs 14 and 15, N-channel MOS FETs 16 and 17, resistors 18 to 21, and differential amplifiers 22 and 23. The PMOS FET 15 and the NMOS FET 17 are formed on the chip.
It is a FET to monitor the characteristics of FET, and MOS FET1,2,1
If the gate widths of 5 and 17 are W 1 , W 2 , W 15 and W 17, respectively, and the characteristic impedance of the transmission line connected to the output terminal 13 of the output circuit is Z 0 , the value of the resistor 18 is The value of resistor 19 is Is. The connection point between the drain electrode of the PMOS FET 15 and the resistor 18 is connected to the positive phase input of the differential amplifier 22, and the connection point between the drain electrode of the NMOS FET 17 and the resistor 19 is connected to the positive phase input of the differential amplifier 23. Also, resistors 20 and 21 have the same resistance value, Is supplied to the inverting inputs of the differential amplifiers 22 and 23. The outputs of the differential amplifiers 22 and 23 are connected to the gate electrodes of the MOS FETs 14 and 16, respectively, and the source electrodes of the MOS FETs 14 and 16 are connected to the MOS FETs 15 and 15, respectively.
It is connected to 17 gate electrodes. The operation of the control voltage generating circuit 12 will be described by taking the side generating an output to the gate electrode of the PMOS FET 4 as an example. Now, assuming that the PMOS FET is finished so that the drain current flows more than the typical value, PM
The potential of the drain electrode of OS FET15 rises and the differential amplifier 22
Since the potential of the output of the FET rises and the potential of the gate electrode of the PMOS FET14 rises, the potential of the source electrode of the PMOS FET14, that is, the potential of the gate electrode of the PMOS FET15 rises, and the drain current decreases. If the gain of the differential amplifier 22 is sufficiently high, the positive-phase input and the inverting input are fed back so that the potentials thereof are substantially equal to each other, so that the potential of the drain electrode of the PMOS FET 15 is almost equal. The drain current of the PMOS FET15 is kept constant regardless of variations in the FET characteristics. Controlled to be. On the contrary, even if the PMOS FET is finished so that the drain current flows less than the typical value, the PMOS FET15 is controlled so that the potential of the gate electrode decreases and the drain current becomes almost equal to the typical designed value. To be done. By applying the output of such a control voltage generation circuit to the gate electrode of the PMOS FET4, when the input signal to the input terminal 11 of the output circuit is at high level (V DD ), the PMOS FET3 turns on and off, the NMOS FET FET5
, The potential of the drain electrode of the NMOS FET5, that is, the potential of the drain electrode of the PMOS FET4 becomes the ground potential, and the variation of the characteristics of the MOS FET in the chip is sufficiently smaller than the variation between the chips. The potential of the gate electrode of FET1 becomes equal to the potential of the gate electrode of PMOS FET15. On the other hand, when the input signal to the input terminal 11 of the output circuit is low level (0V), the PMOS FET3 is conductive and the NMOS FET5 is turned on and off. Therefore, the potential of the gate electrode of the PMOS FET1 is V DD
Becomes Therefore, the transmission line having the characteristic impedance Z 0 is connected to the output terminal 13, and the input signal changing from the low level to the high level is applied to the input terminal 11 of the output circuit (the output terminal 13 is set to the ground potential in the initial state). ), Regardless of variations in FET characteristics, Current can be flowed into the transmission line, The first wave having the amplitude of can be incident on the transmission line.
NMOS FET7のゲート電極へ接続されている制御電圧発生
回路の下側も全く同様にしてNMOS FETの特性のバラツキ
を補償し、出力回路の入力端子11へ高レベルから低レベ
ルに変化する入力信号が印加された時（初期状態で出力
端子13はVDDの電位とする）、FET特性のバラツキにかか
わりなく、伝送線路から の電流を吸い込むことができ、 の振幅の第１波を伝送線路に入射することができる。こ
のように常にCMOS出力回路の信号振幅VDDの1/2の振幅の
第１波を伝送線路に入射することができるので、この第
１波が開放受端で反射されて同じ振幅の第２波が受端か
ら送端（出力回路）に向つて進行し、CMOS出力回路の振
幅が得られる。この第２波が送端に達すると出力回路の
出力端子13の電位は、出力回路の入力端子11が低レヘル
の時はPMOS FET1がしや断、NMOS FET2が導通している状
態で接地電位となり、入力端子11が高レベルの時はPMOS
FET1が導通、NMOS FET2がしや断している状態でVDDの
電位となるので、送端での反射は発生せず、出力回路か
らの入射波は一往復で反射が収まる。The same applies to the lower side of the control voltage generation circuit connected to the gate electrode of the NMOS FET7 to compensate for variations in the characteristics of the NMOS FET, and to the input terminal 11 of the output circuit, an input signal that changes from high level to low level is input. When applied (the output terminal 13 is set to the potential of V DD in the initial state), it is transmitted from the transmission line regardless of the variation in the FET characteristics. Can absorb the current of The first wave having the amplitude of can be incident on the transmission line. In this way, the first wave having an amplitude half the signal amplitude V DD of the CMOS output circuit can always be incident on the transmission line, so that the first wave is reflected at the open receiving end and the second wave having the same amplitude is received. The wave travels from the receiving end to the sending end (output circuit), and the amplitude of the CMOS output circuit is obtained. When this second wave reaches the sending end, the potential of the output terminal 13 of the output circuit becomes the ground potential when the PMOS FET1 is turned off and the NMOS FET2 is turned on when the input terminal 11 of the output circuit is low rehearsal. , And when input terminal 11 is high level,
Since the potential of V DD is reached when FET1 is conducting and NMOS FET2 is turned off, no reflection occurs at the sending end, and the reflection of the incident wave from the output circuit is completed in one round trip.
制御電圧発生回路12はMOS FETの製造上の特性バラツキ
ばからではなく、温度変動によりFET特性が変化した場
合にも、チツプ上の温度はほぼ一定と考えられるので、
その変動を補償することができる。また、電源電圧が変
動して出力MOS FETに流せるドレイン電流や、CMOS出力
回路の出力振幅が変化した場合にも、PMOS FET15のドレ
イン電極の電位、NMOS FET17のドレイン電極の電位が になるように働き、従つて出力回路の第１波の信号振幅
も となるので、その変動を補償することができる。本実施
例の回路のなかで抵抗18〜21は、その抵抗値の精度が制
御電圧発生回路12の補償精度に直接関係している。特に
抵抗18,19は抵抗値の絶対値の精度が問題であり、高精
度の抵抗が必要である。このように高精度な抵抗は、ア
ナログICで用いられている公知のイオン注入法や、複数
の拡散抵抗を形成しておき、これをレーザ・トリミング
などの手段により抵抗値を調整することなどにより得ら
れる。またLSIの実装上のデイメリツトを生ずるが、抵
抗を外付けにすることもできる。本実施例で用いられる
差動増幅器22,23の１例を第２図に示す。24,25はＰチヤ
ネルMOS FET26,27,28はＮチヤネルMOS FETであり、差動
増幅回路を構成する。また、ＰチヤネルMOS FET29とＮ
チヤネルMOS FET30はCMOSインバータを構成している。
本差動増幅器はこの２段構成であり、31は正相入力端
子、32は反転入力端子、33は出力端子である。34は差動
増幅回路の電流源であるNMOS FET28のバイアス電源端子
であるが、特別な電源電圧を設けることなく電源電圧V
DDに接続するように設計することもできる。The control voltage generating circuit 12 is considered not to be due to variations in the characteristics of the MOS FET during manufacturing, but the temperature on the chip is almost constant even when the FET characteristics change due to temperature fluctuations.
The fluctuation can be compensated. Also, when the power supply voltage fluctuates and the drain current that can flow in the output MOS FET or the output amplitude of the CMOS output circuit changes, the potential of the drain electrode of PMOS FET15 and the potential of the drain electrode of NMOS FET17 are also So that the signal amplitude of the first wave of the output circuit also Therefore, the fluctuation can be compensated. In the circuits of this embodiment, the resistors 18 to 21 have resistances whose accuracy is directly related to the compensation accuracy of the control voltage generating circuit 12. In particular, the resistors 18 and 19 have a problem in the accuracy of the absolute value of the resistance value, and thus high-precision resistors are required. Such high-precision resistors can be obtained by the well-known ion implantation method used in analog ICs or by forming multiple diffused resistors and adjusting the resistance value by means such as laser trimming. can get. In addition, although the LSI mounting causes some demerits, the resistor can be externally attached. An example of the differential amplifiers 22 and 23 used in this embodiment is shown in FIG. 24 and 25 are P-channel MOS FETs 26, 27 and 28 are N-channel MOS FETs, which form a differential amplifier circuit. Also, P channel MOS FET 29 and N
The channel MOS FET30 constitutes a CMOS inverter.
This differential amplifier has this two-stage configuration, 31 is a positive phase input terminal, 32 is an inverting input terminal, and 33 is an output terminal. 34 is the bias power supply terminal of the NMOS FET 28, which is the current source of the differential amplifier circuit, but it does not require a special power supply voltage.
It can also be designed to connect to the DD .
また、第１図の回路においてPMOS FET4をNMOS FET5のソ
ース電極と接地電源の間に入れ換えてもよい。同様にNM
OS FET7をPMOS FET6のソース電極と電源VDDの間に入れ
換えてもよい。Further, in the circuit of FIG. 1, the PMOS FET4 may be replaced between the source electrode of the NMOS FET5 and the ground power supply. Similarly NM
The OS FET7 may be replaced between the source electrode of the PMOS FET6 and the power supply V DD .
第３図は第１図の出力回路をトライステート出力回路に
変形した実施例である。第１図のドライブ回路９はＰチ
ヤネルMOS FET35,36とＮチヤネルMOS FET37,38から成る
２入力NAND回路の出力端子とNMOS FET37の間にPMOS FET
4を追加したドライブ回路43に置き換えられ、ドライブ
回路10はＰチヤネルMOS FET39,40とＮチヤネルMOS FET4
1,42から成る２入力NOR回路に出力端子とNMOS FET40の
間にNMOS FET7を追加したドライブ回路44に置き換えら
れている。PMOS FET4のゲート電極45には第１図と同じ
制御電圧発生回路12（図示せず）の差動増幅器22の出力
が接続され、NMOS FET7のゲート電極46には制御電圧発
生回路12の差動増幅器23の出力が接続されている。２入
力NAND回路43の入力はデータ入力端子11とEnable入力端
子47に接続され、２入力NOR回路44の入力はデータ入力
端子11とEnable入力端子に入力を接続したＰチヤネルMO
S FET48とＮチヤネルMOS FET49から成るインバータ50の
出力に接続されている。従つて、Enable入力が低レベル
の時はドライブ回路43の出力はVDD、ドライブ回路44の
出力は接地電位となり、出力MOS FET1,2ともにしや断
し、出力はHighインピーダンスになる。Enable入力が高
レベルであり、データ入力が低レベルの時は、ドライブ
回路43の出力はVDD、ドライブ回路44の出力はNMOS FET7
の働きにより制御電圧発生回路12のモニタ用NMOS FET17
のゲート電極の電位に等しくなり、出力PMOS FET1がし
や断し、出力NMOS FET2が導通する。Enable入力が高レ
ベルであり、データ入力が高レベルの時は、ドライブ回
路43の出力はPMOS FET4の働きにより制御電圧発生回路1
2のモニタ用PMOS FET15のゲート電極の電位に等しく、
ドライブ回路44の出力は接地電位になり、出力PMOS FET
1が導通し、出力NMOS FET2がしや断する。制御電圧発生
回路の働きは第１図の実施例と同じであり、これにより
FET特性のバラツキや電源電圧の変動にかかわりなく、
出力端子に接続された伝送線路にCMOS出力回路の信号振
幅VDDの1/2の振幅の第１波を入射することができ、１往
復で信号の反射を収めることができる。第３図において
も、第１図の実施例と同様にPMOS FET4をNMOS FET38と
接地電源の間に、またNMOS FET7をPMOS FET39と電源VDD
の間に入れるようにしてもよい。FIG. 3 shows an embodiment in which the output circuit of FIG. 1 is modified into a tri-state output circuit. The drive circuit 9 shown in FIG. 1 is a PMOS FET between the output terminal of the 2-input NAND circuit composed of the P-channel MOS FETs 35 and 36 and the N-channel MOS FETs 37 and 38 and the NMOS FET 37.
Replaced by the drive circuit 43 with 4 added, the drive circuit 10 is P-channel MOS FET 39, 40 and N-channel MOS FET 4
It is replaced by a drive circuit 44 in which an NMOS FET7 is added between the output terminal and the NMOS FET40 in the two-input NOR circuit consisting of 1,42. The gate electrode 45 of the PMOS FET 4 is connected to the output of the differential amplifier 22 of the same control voltage generation circuit 12 (not shown) as in FIG. 1, and the gate electrode 46 of the NMOS FET 7 is connected to the differential of the control voltage generation circuit 12. The output of the amplifier 23 is connected. The input of the 2-input NAND circuit 43 is connected to the data input terminal 11 and the Enable input terminal 47, and the input of the 2-input NOR circuit 44 is connected to the data input terminal 11 and the Enable input terminal.
It is connected to the output of an inverter 50 consisting of S FET 48 and N channel MOS FET 49. Therefore, when the Enable input is at the low level, the output of the drive circuit 43 is V DD , the output of the drive circuit 44 is the ground potential, both the output MOS FETs 1 and 2 are turned off, and the output becomes the high impedance. When the Enable input is high level and the data input is low level, the output of drive circuit 43 is V DD and the output of drive circuit 44 is NMOS FET7.
By the function of, the NMOS FET17 for monitoring the control voltage generation circuit 12
Becomes equal to the potential of the gate electrode, the output PMOS FET1 turns on and off, and the output NMOS FET2 turns on. When the Enable input is high level and the data input is high level, the output of the drive circuit 43 is controlled by the control voltage generation circuit 1 by the action of the PMOS FET4.
2 is equal to the potential of the gate electrode of the monitor PMOS FET15,
The output of the drive circuit 44 becomes the ground potential, and the output PMOS FET
1 becomes conductive and output NMOS FET2 turns off. The function of the control voltage generating circuit is the same as that of the embodiment shown in FIG.
Regardless of variations in FET characteristics and fluctuations in power supply voltage,
The first wave having an amplitude half the signal amplitude V DD of the CMOS output circuit can be incident on the transmission line connected to the output terminal, and the reflection of the signal can be contained in one round trip. Also in FIG. 3, as in the embodiment of FIG. 1, the PMOS FET4 is connected between the NMOS FET38 and the ground power supply, and the NMOS FET7 is connected between the PMOS FET39 and the power supply V DD.
You may put in between.
第４図は本発明の他の実施例であり、制御電圧発生回路
12（図示ぜず）は第１図と同じであるが、出力MOS FET
1,2を駆動するドライブ回路が異なる。ＰチヤネルMOS F
ET51とＮチヤネルMOS FET52から成るインバータ53の出
力PMOS FET1と出力NMOS FET2の共通のドライブ回路であ
り、インバータ53の出力とPMOS FET1のゲート電極の間
にはPMOS FET4、インバータ53の出力とNMOS FET2のゲー
ト電極の間にはNMOS FET7が挿入されている。PMOS FET4
のゲート電極45には第１図と同じ制御電圧発生回路12の
差動増幅器22の出力が接続され、NMOS FET7のゲート電
極46には制御電圧発生回路12の差動増幅器23の出力が接
続されている。PMOS FET4のゲート電極45の電位は電源
電圧VDDより少なくともPMOS FET14と15のしき値電圧の
絶対値の和だけが下がつた値であり、NMOS FET7のゲー
ト電極46の電位は接地電位より少なくともNMOS FET16と
17のしきい値電圧の和だけ上がつた値である。従つて、
入力端子11への入力信号が低レベルの時、PMOS FET51が
導通し、NMOS FET52がしや断してインバータ53の出力電
位はVDDとなるので、出力PMOS FET1のゲート電極は
VDD、出力NMOS FET2のゲート電極は制御電圧発生回路12
のモニタ用NMOS FET17のゲート電極の電位に等しくな
る。一方、入力端子11への入力信号が高レベルの時、PM
OS FET51がしや断し、NMOS FET52が導通してインバータ
53の出力電位は接地電位となるので、出力PMOS FET1の
ゲート電極は制御電圧発生回路12のモニタ用PMOS FET15
のゲート電極の電位に等しく、出力NMOS FET2のゲート
電極は接地電位となる。これにより第１図の実施例と同
様に出力端子に接続した伝送線路上の信号の反射を１往
復で収めることができる。FIG. 4 shows another embodiment of the present invention, which is a control voltage generating circuit.
12 (not shown) is the same as in Fig. 1, but output MOS FET
The drive circuits that drive 1 and 2 are different. P channel MOS F
It is a common drive circuit for the output PMOS FET1 and output NMOS FET2 of the inverter 53 consisting of the ET51 and the N-channel MOS FET52. Between the output of the inverter 53 and the gate electrode of the PMOS FET1, PMOS FET4, and the output of the inverter 53 and NMOS FET2. An NMOS FET7 is inserted between the gate electrodes of. PMOS FET4
The output of the differential amplifier 22 of the control voltage generation circuit 12 is connected to the gate electrode 45 of the same, and the output of the differential amplifier 23 of the control voltage generation circuit 12 is connected to the gate electrode 46 of the NMOS FET7. ing. The potential of the gate electrode 45 of the PMOS FET 4 is lower than the power supply voltage V DD by at least the sum of the absolute values of the threshold voltages of the PMOS FETs 14 and 15, and the potential of the gate electrode 46 of the NMOS FET 7 is at least the ground potential. With NMOS FET16
This is a value increased by the sum of 17 threshold voltages. Therefore,
When the input signal to the input terminal 11 is at a low level, the PMOS FET51 conducts, the NMOS FET52 turns on and off, and the output potential of the inverter 53 becomes V DD , so the gate electrode of the output PMOS FET1 is
V DD , the gate electrode of the output NMOS FET2 is the control voltage generator 12
It becomes equal to the potential of the gate electrode of the monitoring NMOS FET17. On the other hand, when the input signal to input terminal 11 is high level, PM
OS FET51 is turned off and NMOS FET52 is turned on and the inverter is turned on.
Since the output potential of 53 is the ground potential, the gate electrode of the output PMOS FET1 is the monitoring PMOS FET15 of the control voltage generation circuit 12.
Of the gate electrode of the output NMOS FET2 is at the ground potential. As a result, similarly to the embodiment of FIG. 1, the reflection of the signal on the transmission line connected to the output terminal can be accommodated in one round trip.
第５図は本発明の他の実施例である。第１図，第３図，
第４図の実施例では出力MOS FETにゲート・ソース間電
圧を制御して、負荷に流せるドレイン電流がFET特性の
バラツキにかかわらず一定になるようにしているが、本
実施例は論理をとる（出力を低レベルまたは高レベルに
する）ための出力MOS FET101,102と電源の間に、負荷に
流せるドレイン電流を一定に調整するためのMOS FET10
3,104を挿入したものである。101,103がＰチヤネルMOS
FET、102,104がＮチヤネルMOS FETである。ＰチヤネルM
OS FET105とＮチヤネルMOS FET106は出力MOS FET101,10
2を駆動するためのインバータ（ドライブ回路）を構成
する。107が出力回路の入力端子であり、108が出力端子
である。PMOS FET103とNMOS FET104のゲート電極に制御
電圧を供給する制御電圧発生回路109は第１図の実施例
の回路と類似しているが、モニタ用MOS FET110〜113の
接続が異なる。110,111がＰチヤネルMOS FET、112,113
がＮチヤネルMOS FETであり、MOS FET101,102,103,104,
110,111,112,113のゲート幅を各々W101，W102，W103，W
104，W110，W111，W112，W113とすると である。また抵抗114の値は 抵抗115の値は である。PMOS FET111,110と抵抗114は直列に接続され、
PMOS FET110と抵抗114の接続点が差動増幅器118の正相
入力に接続される。同様に抵抗115とNMOS FET112,113は
直列に接続され、抵抗115とNMOS FET112の接続点が差動
増幅器119の正相入力に接続される。差動増幅器118と11
9の反転入力には抵抗値の等しい抵抗116と117により の電圧が供給される。差動増幅器118,119には例えば第
２図の回路が用いられる。差動増幅器118,119の出力は
各々PMOS FET111と103、NMOS FET113と104のゲート電極
に接続される。PMOS FET110のゲート電極は接地され、N
MOS FET112のゲート電極は電源VDDに接続される。第１
図の実施例と全く同様に、差動増幅器118,119の利得が
十分高ければ、FET特性のバラツキや電源電圧の変動に
かかわらず、MOS FET110,112のドレイン電極の電位が になるようにMOS FET111,113のゲート電極の電位は制御
される。この制御電圧がMOS FET103,104のゲート電極に
供給されるので、出力端子108に特性インピーダンスZ0
の伝送線路を接続し、入力端子107に低レベルから高レ
ベルに変化する入力信号を印加する（初期状態で出力端
子108は接地電位とする）と、NMOS FET106が導通、PMOS
FET105がしや断、PMOS FET101が導通、NMOS FET102が
しや断して、出力端子108の電位は となる。この第１波が開放受端で反射されて電位はVDD
となり、反射波が出力端子108まで戻つて来て反射が収
まる。一方、入力端子107に高レベルから低レベルに変
化する入力信号を印加する（初期状態で出力端子108はV
DDの電位とする）と、PMOS FET105が導通、NMOS FET106
がしや断、NMOS FET102が導通、PMOS FET101がしや断し
て、出力端子108の電位は となる。この第１波が開放受端で反射されて接地電位と
なり、反射波が出力端子108まで戻つて来て反射が収ま
る。本実施例においても、PMOS FET101をPMOS FET103と
電源VDDの間、NMOS FET102をNMOS FET104と接地電源の
間、PMOS FET110をPMOS FET111と電源VDDの間、NMOS FE
T112をNMOS FET113と接地電源の間に入り換えてもよ
い。また、出力MOS FET101,102のドライブ回路をNAND回
路とNOR回路に置き換えることによりトライステート出
力回路に変形することができる。FIG. 5 shows another embodiment of the present invention. Figure 1, Figure 3,
In the embodiment shown in FIG. 4, the gate-source voltage is controlled in the output MOS FET so that the drain current that can be passed through the load becomes constant regardless of variations in the FET characteristics. However, this embodiment takes the logic. MOS FET10 for adjusting the drain current that can flow to the load between output MOS FET101,102 (to make the output low level or high level) and the power supply constant
It is an insertion of 3,104. 101 and 103 are P channel MOS
FETs 102 and 104 are N-channel MOS FETs. P Channel M
OS FET105 and N channel MOS FET106 are output MOS FET101,10
An inverter (drive circuit) for driving 2 is configured. 107 is an input terminal of the output circuit, and 108 is an output terminal. The control voltage generation circuit 109 for supplying the control voltage to the gate electrodes of the PMOS FET 103 and the NMOS FET 104 is similar to the circuit of the embodiment of FIG. 1, but the connection of the monitor MOS FETs 110 to 113 is different. 110,111 is P channel MOS FET, 112,113
Is N channel MOS FET, and MOS FET101,102,103,104,
The gate widths of 110, 111, 112, 113 are W 101 , W 102 , W 103 , W respectively.
104 , W 110 , W 111 , W 112 , W 113 Is. The value of the resistor 114 is The value of resistor 115 is Is. The PMOS FETs 111 and 110 and the resistor 114 are connected in series,
The connection point between the PMOS FET 110 and the resistor 114 is connected to the positive phase input of the differential amplifier 118. Similarly, the resistor 115 and the NMOS FETs 112 and 113 are connected in series, and the connection point of the resistor 115 and the NMOS FET 112 is connected to the positive phase input of the differential amplifier 119. Differential amplifier 118 and 11
The inverting input of 9 is Is supplied. The circuit of FIG. 2 is used for the differential amplifiers 118 and 119, for example. The outputs of the differential amplifiers 118 and 119 are connected to the gate electrodes of the PMOS FETs 111 and 103 and the NMOS FETs 113 and 104, respectively. The gate electrode of the PMOS FET 110 is grounded and N
The gate electrode of the MOS FET 112 is connected to the power supply V DD . First
Just like the embodiment shown in the figure, if the gains of the differential amplifiers 118 and 119 are sufficiently high, the potentials of the drain electrodes of the MOS FETs 110 and 112 will be irrespective of variations in the FET characteristics and fluctuations in the power supply voltage. The potentials of the gate electrodes of the MOS FETs 111 and 113 are controlled so that Since this control voltage is supplied to the gate electrodes of the MOS FETs 103 and 104, the characteristic impedance Z 0
When the input signal that changes from a low level to a high level is applied to the input terminal 107 (the output terminal 108 is set to the ground potential in the initial state), the NMOS FET 106 is turned on and the PMOS is turned on.
FET105 is disconnected, PMOS FET101 is conductive, NMOS FET102 is disconnected, and the potential of output terminal 108 is Becomes This first wave is reflected at the open receiving end and the potential is V DD
Then, the reflected wave returns to the output terminal 108 and the reflection stops. On the other hand, an input signal that changes from high level to low level is applied to the input terminal 107 (in the initial state, the output terminal 108 is V
The potential of DD ) and the PMOS FET105 are conductive, and the NMOS FET106
The potential of the output terminal 108 is Becomes This first wave is reflected at the open receiving end to become the ground potential, the reflected wave returns to the output terminal 108, and the reflection is stopped. Also in this embodiment, the PMOS FET 101 is connected between the PMOS FET 103 and the power supply V DD , the NMOS FET 102 is connected between the NMOS FET 104 and the ground power supply, the PMOS FET 110 is connected between the PMOS FET 111 and the power supply V DD , and the NMOS FE is connected.
The T112 may be exchanged between the NMOS FET 113 and the ground power supply. Also, by replacing the drive circuit of the output MOS FETs 101, 102 with a NAND circuit and a NOR circuit, it can be transformed into a tri-state output circuit.
実施例中のMOS FETにはすべてエンハンスメント形を用
いることができるが、PMOS FET4,13、NMOS FET7,15にデ
イプリーシヨン形を用いると出力MOS FET1,2のゲート・
ソース間電圧を大きくとることができ、ゲート幅を小さ
くすることができるので、セル面積の点で有利である。
また、PMOS FET103,111、NMOS FET104,113にもデイプリ
ーシヨン形を用いるとそのゲート幅を小さくすることが
でき、セル面積の点で有利である。The enhancement type can be used for all the MOS FETs in the embodiment, but when the depletion type is used for the PMOS FET4,13 and the NMOS FET7,15, the gates of the output MOS FET1,2 are
Since the source-to-source voltage can be increased and the gate width can be reduced, it is advantageous in terms of cell area.
Further, if the PMOS FETs 103 and 111 and the NMOS FETs 104 and 113 are also of the depletion type, their gate width can be reduced, which is advantageous in terms of cell area.
CMOS回路には直流電流が流れないが、本発明の実施例の
制御電圧発生回路には直流電流が流れる。しかし、LSI
チツプ上に搭載される多数の出力回路に対し、制御電圧
発生回路は少なくとも１つあればよいので制御電圧発生
回路を設けたことによる消費電力の増加や、セル面積の
増加はほとんど問題にはならない。No direct current flows through the CMOS circuit, but a direct current flows through the control voltage generating circuit of the embodiment of the present invention. However, LSI
Since at least one control voltage generation circuit is required for many output circuits mounted on the chip, an increase in power consumption and an increase in cell area due to the provision of the control voltage generation circuit are hardly problems. .
本発明によれば、素子の製造バラツキや電源電圧変動・
温度変動にかかわらず、出力回路に接続される伝送線路
をLSIチツプ内で送端終端することが可能であり、LSIチ
ツプ間の高速な信号を行なうことができる。しかも、出
力回路自身はCMOS形の回路なので非常に消費電力を小さ
くすることができる。According to the present invention, manufacturing variations of elements and power supply voltage fluctuations
The transmission line connected to the output circuit can be terminated in the LSI chip regardless of temperature fluctuations, and high-speed signals can be transmitted between the LSI chips. Moreover, since the output circuit itself is a CMOS type circuit, the power consumption can be greatly reduced.
なお、送端終端伝送方式では送端に近いほど信号の遅延
時間が大きくなる。これを許容できない信号ネツトに関
しては、負荷を出力回路のあるLSIチツプから遠いもの
と近いものにグループ分けし、それぞれ別の出力回路で
ドライブするようにすればよい。In addition, in the transmission end termination transmission system, the signal delay time becomes longer as the transmission end is closer. For signal nets that cannot tolerate this, the loads may be grouped into those far from the LSI chip having the output circuit and those close to the LSI chip, and driven by different output circuits.
第１図，第３図，第４図，第５図はそれぞれ本発明の実
施例の出力回路図であり、第２図はそのなかで用いられ
る差動増幅器の一例の回路図である。 1,101,103…出力PMOS FET、2,102,104…出力NMOS FET、
15,110,111…モニタ用PMOS FET、17,112,113…モニタ用
NMOS FET、9,10,43,44,53…出力MOS FETドライブ回路、
12,109…制御電圧発生回路、22,23,118,119…差動増幅
器、50…インバータ。1, FIG. 3, FIG. 4, and FIG. 5 are output circuit diagrams of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a differential amplifier used therein. 1,101,103 ... Output PMOS FET, 2,102,104 ... Output NMOS FET,
15,110,111… PMOS FET for monitor, 17,112,113… For monitor
NMOS FET, 9,10,43,44,53 ... Output MOS FET drive circuit,
12,109 ... Control voltage generation circuit, 22,23,118,119 ... Differential amplifier, 50 ... Inverter.
Claims (6)
ETを有し、両FETのドレイン電極を接続して出力端子に
出力信号を与える出力トランジスタ回路と、 入力端子に供給される入力信号を受けて、上記第１のＰ
チャネルFETのゲート電極を駆動する第１のドライブ回
路と上記第１のＮチャネルFETのゲート電極を駆動する
第２のドライブ回路と、 上記第１のＰチャネルFETのドレイン電流をモニタする
第１のモニタ用トランジスタと上記第１のＮチャネルFE
Tのドレイン電流をモニタする第２のモニタ用トランジ
スタとを含み、上記第１および上記第２のモニタ用トラ
ンジスタのドレイン電流の大きさが所定の値になるよう
に帰還制御することにより、上記出力トランジスタ回路
の出力インピーダンスを上記出力端子に接続された伝送
線路の特性インピーダンスと略等しくするための制御信
号を上記第１及び第２のドライブ回路に与える制御回路
と、 を具備したことを特徴とする出力回路。1. A first P-channel FET and a first N-channel F.
An output transistor circuit that has an ET and connects the drain electrodes of both FETs to give an output signal to the output terminal, and receives the input signal supplied to the input terminal,
A first drive circuit that drives the gate electrode of the channel FET, a second drive circuit that drives the gate electrode of the first N-channel FET, and a first drive circuit that monitors the drain current of the first P-channel FET. Monitor transistor and the first N-channel FE
A second monitoring transistor for monitoring the drain current of T, and performing feedback control so that the magnitudes of the drain currents of the first and second monitoring transistors become a predetermined value, thereby providing the output A control circuit for giving a control signal for making the output impedance of the transistor circuit substantially equal to the characteristic impedance of the transmission line connected to the output terminal, to the first and second drive circuits. Output circuit.
電源の間のFETに直列に第２のＰチャネルFETが挿入さ
れ、そのゲート電極の電位を調整することにより第１の
ドライブ回路の出力信号の低レベルを調整し、第２のド
ライブ回路はその出力端子と正側電源の間のFETに直列
に第２のＮチャネルFETが挿入され、そのゲート電極の
電位を調整することにより第２のドライブ回路の出力信
号の高レベルを調整するようにしたことを特徴とする特
許請求の範囲第１項記載の出力回路。2. A first drive circuit, wherein a second P-channel FET is inserted in series with an FET between an output terminal of the first drive circuit and a negative power source, and the potential of the gate electrode of the second P-channel FET is adjusted to adjust the potential of the first drive circuit. By adjusting the low level of the output signal of, the second drive circuit inserts a second N-channel FET in series with the FET between its output terminal and the positive power supply, and adjusts the potential of its gate electrode. The output circuit according to claim 1, wherein the high level of the output signal of the second drive circuit is adjusted.
は共通の一つのドライブ回路であって、該ドライブ回路
の出力と上記出力トランジスタ回路の第１のＰチャネル
FETのゲート電極の間に第３のＰチャネルFETが挿入さ
れ、そのゲート電極の電位を調整することにより上記出
力トランジスタ回路の第１のＰチャネルFETのゲート・
ソース間電圧を調整し、該ドライブ回路の出力と上記出
力トランジスタ回路の第１のＮチャネルFETのゲート電
極の間に第３のＮチャネルFETが挿入され、そのゲート
電極に電位を調整することにより上記出力トランジスタ
回路の第１のＮチャネルFETのゲート・ソース間電圧を
調整するようにしたことを特徴とする特許請求の範囲第
１項記載の出力回路。3. The first drive circuit and the second drive circuit are one drive circuit in common, and the output of the drive circuit and the first P channel of the output transistor circuit.
A third P-channel FET is inserted between the gate electrodes of the FETs, and the gate of the first P-channel FET of the output transistor circuit is adjusted by adjusting the potential of the gate electrode.
By adjusting the voltage between the sources and inserting a third N-channel FET between the output of the drive circuit and the gate electrode of the first N-channel FET of the output transistor circuit, and adjusting the potential on the gate electrode. The output circuit according to claim 1, wherein the gate-source voltage of the first N-channel FET of the output transistor circuit is adjusted.
１のＰチャネルFETの1/a（ａは任意の数）倍のゲート幅
を持つ第４のＰチャネルFETにて構成し、第４のＰチャ
ネルFETのドレイン電極はaZ0（Z0は伝送線路の特性イン
ピーダンス）抵抗値を持つ第１の抵抗の一方の端子と第
１の差動増幅器の正相入力に接続され、第１の差動増幅
器の出力は第２または第３のＰチャネルFETと第５のＰ
チャネルFETのゲート電極に接続され、第５のＰチャネ
ルFETのソース電極は第４のＰチャネルFETのゲート電極
に接続され、第１の抵抗の他方の端子は負側電源に接続
され、上記第２のモニタ用トランジスタとして第１のＮ
チャネルFETの1/b（ｂは任意の数）倍のゲート幅を持つ
第４のＮチャネルFETにて構成し、第４のＮチャネルFET
のドレイン電極はbZ0の抵抗値を持つ第２の抵抗の一方
の端子と第２の差動増幅器の正相入力に接続され、第２
の差動増幅器の出力は第２または第３のＮチャネルFET
と第５のＮチャネルFETのゲート電極と接続され、第５
のＮチャネルFETのソース電極は第４のＮチャネルFETの
ゲート電極に接続され、第２の抵抗の他方の端子は正側
電源に接続され、第１および第２の差動増幅器の反転入
力はともに正側電源と負側電源の中心の電位に接続され
た制御電圧発生回路として上記制御回路を構成すること
を特徴とする特許請求の範囲第２項または第３項記載の
出力回路。4. A fourth P-channel FET having a gate width 1 / a (a is an arbitrary number) times as large as that of the first P-channel FET is used as the first monitoring transistor. The drain electrode of the P-channel FET is connected to one terminal of the first resistor having the resistance value aZ 0 (Z 0 is the characteristic impedance of the transmission line) and the positive phase input of the first differential amplifier, and the first difference The output of the dynamic amplifier is the second or third P-channel FET and the fifth P-channel FET.
The gate electrode of the channel FET, the source electrode of the fifth P-channel FET is connected to the gate electrode of the fourth P-channel FET, the other terminal of the first resistor is connected to the negative power source, The first N as a second monitoring transistor
A fourth N-channel FET having a gate width 1 / b (b is an arbitrary number) times that of the channel FET.
Has a drain electrode connected to one terminal of a second resistor having a resistance value of bZ 0 and a positive phase input of the second differential amplifier,
The output of the differential amplifier is a second or third N-channel FET
And a gate electrode of the fifth N-channel FET,
The source electrode of the N-channel FET is connected to the gate electrode of the fourth N-channel FET, the other terminal of the second resistor is connected to the positive power supply, and the inverting inputs of the first and second differential amplifiers are The output circuit according to claim 2 or 3, wherein the control circuit is configured as a control voltage generation circuit connected to the center potentials of the positive power supply and the negative power supply.
低レベルまたは高レベルの論理をとる第６のFETと、出
力電流を調整するための第７のFETとを直列に接続して
構成したことを特徴とする特許請求の範囲第１項記載の
出力回路。5. The output transistor circuit is configured by connecting in series an output terminal, a sixth FET having a low level or high level logic, and a seventh FET for adjusting an output current. The output circuit according to claim 1, wherein:
ジスタとして第６のFETの1/c（ｃは任意の数）倍のゲー
ト幅を持つ第８のFETと、第７のFETの1/c倍のゲート幅
を持つ第９のFETにて構成し、第８のFETと第９のFETに
はcZ0の抵抗値を持つ第３の抵抗が直列に接続され、抵
抗の電源の接続していない端子はさらに第３の差動増幅
器の正相入力に接続され、第３の差動増幅器の反転入力
は出力信号の高レベルと低レベルの中心の電位に接続さ
れ、第３の差動増幅器の出力は上記出力トランジスタ回
路の第７のFETと第９のFETのゲート電極に接続された制
御電圧発生回路として上記制御回路を構成することを特
徴とする特許請求の範囲第５項記載の出力回路。6. An eighth FET having a gate width 1 / c (c is an arbitrary number) times that of a sixth FET as the first and second monitoring transistors and one of the seventh FETs. It is composed of a 9th FET having a gate width of / c times, and the 8th FET and the 9th FET are connected in series with a 3rd resistor having a resistance value of cZ 0 , and the power supply of the resistor is connected. The terminal which is not connected is further connected to the positive phase input of the third differential amplifier, and the inverting input of the third differential amplifier is connected to the high-level and low-level center potentials of the output signal. The output of the dynamic amplifier constitutes the control circuit as a control voltage generation circuit connected to the gate electrodes of the seventh FET and the ninth FET of the output transistor circuit. Output circuit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60248811A JPH0746769B2 (en) | 1985-11-08 | 1985-11-08 | Output circuit |
| US06/894,103 US4719369A (en) | 1985-08-14 | 1986-08-07 | Output circuit having transistor monitor for matching output impedance to load impedance |
| DE19863627681 DE3627681A1 (en) | 1985-08-14 | 1986-08-14 | OUTPUT SWITCHING |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60248811A JPH0746769B2 (en) | 1985-11-08 | 1985-11-08 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62109426A JPS62109426A (en) | 1987-05-20 |
| JPH0746769B2 true JPH0746769B2 (en) | 1995-05-17 |
Family
ID=17183756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60248811A Expired - Lifetime JPH0746769B2 (en) | 1985-08-14 | 1985-11-08 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746769B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161916A (en) * | 1987-12-18 | 1989-06-26 | Toshiba Corp | Semiconductor integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60149209A (en) * | 1984-01-17 | 1985-08-06 | Toshiba Corp | Operating point compensating circuit |
-
1985
- 1985-11-08 JP JP60248811A patent/JPH0746769B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62109426A (en) | 1987-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4719369A (en) | Output circuit having transistor monitor for matching output impedance to load impedance | |
| US4614882A (en) | Bus transceiver including compensation circuit for variations in electrical characteristics of components | |
| EP0678983B1 (en) | Output buffer current slew rate control integrated circuit | |
| US4477737A (en) | Voltage generator circuit having compensation for process and temperature variation | |
| US6593795B2 (en) | Level adjustment circuit and data output circuit thereof | |
| US5939937A (en) | Constant current CMOS output driver circuit with dual gate transistor devices | |
| EP0536536B1 (en) | A low voltage swing output MOS circuit for driving an ECL circuit | |
| US5105102A (en) | Output buffer circuit | |
| KR19990067849A (en) | Voltage tolerant output buffer | |
| EP1229649B1 (en) | Output circuit | |
| JP2010178346A (en) | Output buffer having predriver for compensating slew rate against process variation | |
| US4782252A (en) | Output current control circuit for reducing ground bounce noise | |
| US5719525A (en) | Enhanced voltage tracking circuit for high voltage tolerant buffers | |
| EP0606727B1 (en) | Automatic control of buffer speed | |
| US5986473A (en) | Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects | |
| US6366122B1 (en) | Tristate driver for integrated circuit in interconnects | |
| EP0357366B1 (en) | Improved current mirror circuit | |
| US6118303A (en) | Integrated circuit I/O buffer having pass gate protection with RC delay | |
| US6157215A (en) | Method and apparatus for controlling impedance | |
| US6078207A (en) | Output amplitude regulating circuit | |
| US4943740A (en) | Ultra fast logic | |
| US4845388A (en) | TTL-CMOS input buffer | |
| US5777496A (en) | Circuit for preventing more than one transistor from conducting | |
| US5043605A (en) | CMOS to ECL output buffer | |
| US6850100B2 (en) | Output buffer circuit |