JPH0746285A - Data receiver - Google Patents

Abstract

PURPOSE:To suppress the increase in the processing quantity by deciding an identification point of a reception signal with high accuracy when noise, frequency offset and fading are in existence and adding power of only samples whose identification point is roughly estimated through synchronization. CONSTITUTION:Data A/D-converted by A/D converters 17, 18 at a clock whose frequency is an integral number of multiple of a symbol clock are received by a memory 21. A UW detection circuit 32 detects a symbol string from phase information of received data and estimates a frame position to roughly estimate an identification position and to obtain power of the identification position roughly estimated in the reception data stored in the memory 21. The position of the identification point is detected from maximum power resulting from adding synchronizingly power of the reception signals for each sample number the same as number of the A/D converters 17, 18 (N samples) to reduce the processing quantity of identification point detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus for use in a digital communication receiver or the like for detecting the position of an identification point by using power information which is not affected by the total symbol length and phase of a received signal.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration of a conventional data receiving apparatus, and FIG. 3 is a diagram showing a configuration of conventional data. FIG. 4 is a diagram showing the arrangement of signal points in the 16QAM (16-ary quadrature amplitude modulation) system.

In the example shown in FIG. 3, the sample ratio (oversampling ratio) of the A / D converter with respect to the symbol rate is N, the number of symbols in a known symbol string (UW: unique word) for identifying a frame is M, and , And the frame length is L. In addition, in the example shown in FIG.
Amplitude is modulated with values orthogonal to the I and Q signals. In FIGS. 2, 3 and 4, data from the transmitting antenna 2 of the transmitter 1 is received by the receiver 4 through the receiving antenna 3.

The received data from the receiver 4 is sampled by the A / D converter 5 at an integer multiple of the symbol clock (hereinafter referred to as N
I signal Sa described as double oversampling) is obtained. Further, the A / D converter 6 obtains a Q signal Sb oversampled N times. The I signal Sa and the Q signal Sb are stored in the memory 6. At the same time, the phase calculation circuit 7 calculates the reception phase from the I signal Sa and the Q signal Sb, and the error calculation circuit 8
Output to. The error calculation circuit 8 performs the following processing on M reception phase sequences.

First, a frequency offset is obtained from the difference between the M reception phase sequences and the phase sequence of the unique word stored in the memory 10 by the least square method, and the frequency offsets of the M reception phase sequences are calculated. Make a correction. The sum of squares of the difference between the reception phase train subjected to frequency offset correction and the phase train of the unique word is obtained.

This is sent to the discrimination point detection circuit 9 as a squared error Se. The discrimination point detection circuit 9 finds the point at which the square error is the minimum, and the head address Sf in which the received data is stored is obtained from the address on the memory 6 at that time. Based on the head address Sf, the memory 6 outputs the I signal Sg and the Q signal Sh at the identification point position to the data decoding circuit 12. The data decoding circuit 12 outputs the decoded data obtained by decoding the 16QAM signal.

[0007]

However, in the above conventional data demodulation device, since the received phase is used to detect the identification point, the identification is performed when the phase information is deteriorated due to noise, frequency offset, fading or the like. The point detection will be wrong and normal decoding will not be possible. Further, since the unique word is short, the reception level is lowered only in the unique word section due to fading or the like, and the identification point cannot be detected.

The present invention solves such a conventional problem. Even when noise, frequency offset, or fading is present, the discrimination point of the received signal can be accurately determined, and the discrimination point is roughly estimated. It is an object of the present invention to provide an excellent data receiving apparatus capable of synchronously adding the powers of only the selected samples and suppressing the increase in the processing amount.

[0009]

In order to achieve the above object, a data receiving apparatus of the present invention uses a frame-structured transmission signal composed of a known symbol sequence for identifying a frame and data as an integer multiple of a symbol clock. A / D conversion means for obtaining the digitized reception data sampled in 1., symbol sequence detection means for estimating a frame position by detecting a symbol sequence from the phase information of the obtained reception data, and roughly estimating an identification point position, It is configured to include an identification point detection unit that performs power-synchronized addition of received data in a range that is roughly estimated and detects the position of the identification point from the added maximum value.

[0010]

With such a configuration, in the data receiving apparatus of the present invention, the data is fetched by A / D conversion at an integer multiple of the symbol clock, the symbol string is detected from the phase information of the received data, and the frame position is estimated. The rough estimation of the discrimination point position is performed to obtain the power of the roughly estimated discrimination point position of the data, and the powers of the received signals are synchronously added for each number of samples (N samples) equal to the number of A / D conversions, and the maximum The position of the identification point is obtained from the value. That is, the entire symbol length of the received signal is used, and the power information that is not influenced by the phase is used. Therefore, even if there is noise, frequency offset, or fading, the discrimination point of the received signal is accurately determined, and the power is synchronously added only to the samples for which the discrimination point is roughly estimated by the UW detection means, thereby suppressing an increase in processing amount. To be

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data receiving apparatus of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the data receiving apparatus of the present invention. In FIG. 1, the data receiving apparatus includes a transmitter 11 for quadrature-modulating and transmitting transmission data, a transmitting antenna 12, and a receiving antenna 1.
3 and a receiver 14 that quadrature-detects the reception signal from the reception antenna 13 and separates it into an in-phase component I signal S15 and a quadrature component Q signal S16.

Further, this data receiving apparatus is provided with the I signal S1.
5, Q signal S16 is sampled at an integer multiple of the symbol clock and digitized I signal S19 and Q signal S20
A / D converters 17 and 18 for outputting the I signal S19,
The Q signal S20 is stored and the symbol-extracted I signal S2 is stored.
2, the memory 21 for outputting the Q signal S23, and the I signal S2
The data decoding circuit 24 has a data decoding circuit 24 for decoding the data of each of the Q signal S23 and the Q signal S23 by a threshold value and outputting the decoded data S25.

Further, this data receiving apparatus is provided with an I signal S
19, a phase calculation circuit 26 for obtaining the reception phase S27 of the Q signal S20, an error calculation circuit 28 for obtaining the sum of squares of the errors from the phase sequence of the unique word stored in the memory 29 from the M reception phase sequences, Unique word phase sequence S30
And a memory 29 for storing

Further, the data receiving apparatus is arranged such that the position S of the identification point of the UW position S33 is calculated from the minimum value of the sum of squares S31 of the error.
UW detection circuit 32 which performs rough estimation of 34, and I signal S35
And the power from the Q signal S36, and performs the synchronous addition S38 for every N samples, and the memory 2 at that time from the maximum value of the synchronous addition result and the estimated value of UW.
The identification point detection circuit 39 for detecting the start address S40 of the received data stored in No. 1 of FIG.

Next, the operation of the configuration of this embodiment will be described. In this operation, UW detection, rough discrimination point estimation processing, discrimination point detection processing, and data decoding processing are performed.
Here, the A / D converters 17, 1 for the symbol rate
The sample ratio (oversampling ratio) of 8 is N and the frame length is L.

First, the UW detection and discrimination point rough estimation processing will be described. The I signal S19 over-sampled N times by the A / D converter 17 and the Q signal S20 over-sampled N times by the A / D converter 18 are stored in the memory 21. At the same time, the phase calculation circuit 26 calculates the reception phase from the I signal S19 and the Q signal S20, and outputs the reception phase to the error calculation circuit 28. The error calculation circuit 28 performs the following processing on M reception phase sequences.

First, a frequency offset is obtained from the difference between the M received phase sequences and the phase sequence of the unique word stored in the memory 29 by the least square method. Then, the frequency offset is corrected for the M reception phase sequences. The sum of squares of the difference between the reception phase train subjected to frequency offset correction and the phase train of the unique word is calculated.

This sum of squares is output to the UW detection circuit 32 as a squared error S31. The UW detection circuit 32 finds the minimum point of the squared error, and the rough estimation value S33 of the identification point position and the UW address S34 are obtained from the value of the minimum point. Here, the discrimination point is obtained from the three samples by rough estimation of the discrimination point.

Next, the discrimination point detection processing will be described.
I signal S35 and Q signal S3 stored in the memory 21
The power is calculated from 6 and the following equation (Equation 1) is obtained for each N samples.
Sequentially as shown in.

[0021]

[Equation 1]

The memory 21 uses the address of the SUM that takes the maximum value of the synchronous addition result in the discrimination point detection circuit 39 from the result of the synchronous addition for one frame of data and the UW detection value detected by the UW detection circuit 32 in the memory 21. Start address of S40
(Hereinafter referred to as ADDR). Then, symbol extraction is performed from the data stored in the memory 21 by the following equation (Equation 2).

[0023]

[Equation 2]

Further, the data decoding process will be described. Symbol extracted symbol I signal S22 and Q signal S
23, the 16QAM signal is compared with the threshold value as shown in FIG. 3, and the decoded data string S25 is output.

[0025]

As is apparent from the above description, the data receiving apparatus of the present invention uses all the symbol lengths of the received signal and uses the power information which is not influenced by the phase, so that noise, frequency offset and fading are caused. Even in the case of the above, the discrimination point of the received signal is accurately determined, and the power is synchronously added only to the sample for which the discrimination point is roughly estimated by the UW detection means, so that an increase in the processing amount can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data receiving apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional data receiving device.

FIG. 3 is an explanatory diagram showing a conventional data structure.

FIG. 4 is an explanatory diagram showing an arrangement state of signal points in a conventional 16QAM system.

[Explanation of symbols]

 14 receiver 17,18 A / D converter 21,29 memory 24 data decoding circuit 26 phase calculation circuit 28 error calculation circuit 32 UW detection circuit 37 synchronous addition circuit 39 discrimination point detection circuit

Claims (1)

[Claims] 1. An A / D conversion means for obtaining digitized reception data obtained by sampling a transmission signal having a frame structure composed of a known symbol sequence for identifying a frame and data, at an integral multiple of a symbol clock, and the obtained reception. The symbol position is detected from the phase information of the data to estimate the frame position,
Data reception including symbol string detection means for roughly estimating the position of the identification point and identification point detection means for performing power-synchronous addition of received data in the roughly estimated range and detecting the position of the identification point from the added maximum value. apparatus.