JPH0743948B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, in particular, a semiconductor using a so-called non-volatile memory transistor that can hold information for a long time by changing a threshold voltage according to information. The present invention relates to a memory device, and more particularly to a memory device in which stress applied to a gate when writing data is reduced.

[Conventional technology]

Conventionally, a circuit for selecting a row (word line) of this type of semiconductor memory device has a structure as shown in FIG. In the figure, 1 is a memory cell array, 2 is a decoder for selecting several rows from all rows of the memory cell array, and in this example, four rows are selected. 3 and 4 are row selection transistors, 5 to 8 are word lines of memory, C0 to C3, ▲ ▼ to ▲ ▼ are signals applied to row selection transistors 3 and 4, and 9 and 10 are from the address buffer. , 12 is a predecoder that outputs signals C0 to C3, ▲ ▼ to ▲ ▼ according to the signal from the address buffer. This predecoder has a 2-input AND121, one input has two negative logic AND122,123, and two inputs have a negative logic AN.
It is composed of D124 and inverters 125-132.

Next, the connection state of the transistors in the memory array
Shown in the figure. In the figure, the same parts as those in FIG. 2 are denoted by the same symbols. T1 and T2 are memory transistors in the same row, 13 and 14 are their control gates, 15 and 16 are floating gates, 17 and 18 are source electrodes, 19 and 20 are drain electrodes, and 21 and 22 are drain lines. Transistor T1
The gate 13 of the is a transistor by the common word line 5
It is electrically connected to the gate 14 of T2, and likewise, the gates of the memory transistors on the same row are all electrically connected by a common word line.

Next, the operation will be described. A case where data is written to a memory transistor selected by an address signal in memory cell array 1 will be described. In this device, writing to a memory transistor means injecting electrons into the floating gate of the memory transistor, and the stored content after the injection is defined as “0”, and the floating gate of the memory transistor is defined. Eliminating electrons from is called erasing,
The memory content after being pulled out is defined as "1". Before writing to the memory transistor, electrons are not accumulated in the floating gate of the memory transistor, that is, the stored content is defined as "1". First, the decoder 2 selects word lines 5 to 8 from all word lines. On the other hand, the predecoder 12 receives the signals 9 and 10 from the address buffer, and sends the signals C0 to C3 and ▲ ▼ to ▲ ▼ to the row selecting transistors 3 and 4 so that the transistor 3 is turned on and the transistors 3 and 4 are turned on. Only the word lines where 4 is off are selected. In this case, the selected memory transistor is divided into eight blocks in the memory cell array 1.
There are a total of eight blocks, one from each of the blocks D0 to D7. The eight selected memory transistors are connected to the same word line, and this word line is selected by the decoder 2, the predecoder 12, and the transistors 3 and 4 for row selection as described above, and a high voltage is applied. Will be applied. At this time, the word line to which the selected memory transistor is not connected is set to a predetermined voltage lower than the high voltage.

On the other hand, the high voltage is applied to the drains of the eight selected memory transistors via the drain lines selected by the column selection decoder (not shown).

In this way, by applying a high voltage to both the gate and drain of the selected memory transistor, electrons are injected into the floating gate of the memory transistor, and data is written to the memory transistor (memory content “0”). Be done.

At this time, the high voltage is also applied to the gate of the non-selected memory transistor connected to the word line to which the gate of the selected memory transistor is connected.
Since a high voltage is not applied to the drain line to which the drain of the non-selected memory transistor is connected, writing to the non-selected memory transistor, that is, injection of electrons into the floating gate is not performed.

Therefore, a so-called stress voltage is applied to the gate of the non-selected memory transistor in the same row as the selected memory transistor, and the number of times the stress voltage is applied causes the non-selected memory transistor to be already in the non-selected memory transistor. When data is being written, that is, electrons are being injected into the floating gate, gate extraction may occur.

Here, the gate extraction will be described. In FIG. 3, when the memory transistor T1 is selected and writing is performed to this memory transistor T1, it is assumed that the unselected memory transistor T2 has already been written. Since a high voltage is applied to the word line 5 to write to the memory transistor T1, a stress voltage is applied to the gate 14 of the memory transistor T2. That is, since the memory transistor T2 has already been written, electrons are injected into its floating gate 16, but the electrons are attracted toward the gate 14 by the strong electric field due to the high voltage applied to the gate 14. May be lost. This is called gate extraction.

[Problems to be solved by the invention]

The conventional semiconductor memory device is configured as described above,
When writing data, a stress voltage is applied to the gates of all the other memory transistors on the same row as the target memory transistor. Therefore, for example, 32 memory transistors are lined up in one row, and when writing to all of these 32 memory transistors, the maximum of other memory transistors on the same row as the target memory transistor ( 32-1) = a stress voltage of 31 times is applied, which has the drawback that there is a high possibility that the gate will be pulled out.

The present invention has been made in order to reduce the above-mentioned problems, and significantly reduces the number of times a stress voltage is applied to all gates of other memory transistors on the same row as a target memory transistor. It is an object of the present invention to provide a semiconductor memory device that reduces the number of gates and makes it difficult to pull out the gate.

[Means for solving problems]

A semiconductor memory device according to the present invention has a control gate and a floating gate, stores information “0” or “1” depending on whether or not electrons are stored in the control gate, and stores “0” or “1” before writing data. A plurality of memory cell arrays in which non-volatile memory transistors referred to as "1" are arranged in a matrix of a plurality of rows and a plurality of columns and corresponding to the plurality of memory cell arrays are provided, and each corresponds to a corresponding memory cell array. A plurality of word line groups having a plurality of word lines connected to the control gates of a plurality of memory transistors arranged in a row, and a plurality of word line groups provided corresponding to the plurality of memory cell arrays. Receiving write data for multiple memory cell transistors in the cell array and writing these data When all the data are "1", it outputs the non-selection signal, and outputs the selection signal at other times, and receives the output from the address signal and the control signal output circuits. The word line group corresponding to the control signal output circuit that outputs the non-selection signal is supplied with the same level potential as the word line not selected by the input address signal to the word line selected by the input address signal. Word line selection that applies a potential for writing "0" to the word line selected by the input address signal in the word line group corresponding to the control signal output circuit that outputs the selection signal A decoder is provided.

[Action]

In the present invention, as described above, the memory cell array in which the nonvolatile memory transistors are arranged in a matrix of a plurality of rows and a plurality of columns is divided into a plurality of memory cell arrays, and the divided memory cell arrays should be written. When all the data is “0”, the word line in the memory cell array has the same level as the word line in the non-selected memory cell array, and therefore is selected when writing to all the memory transistors in the memory cell array. High voltage is applied only to the word line of the divided memory cell array to which the memory transistor is connected,
The number of times the stress voltage is applied is greatly reduced, making it difficult to pull out the gate.

〔Example〕

An EPROM which is an embodiment of the present invention will be described below with reference to the drawings. Here, writing into the memory transistor of the EPROM means injecting electrons into the floating gate of the memory transistor, and the storage content after this injection is defined as "0". Further, withdrawing electrons from the floating gate of the memory transistor is called erasing, and the stored content after this erasing is defined as "1". Before writing to the memory transistor, electrons are not stored in the floating gate of the memory transistor, that is, the stored content is "1".
It is said that.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, reference numerals 1a and 1b denote divided memory cell arrays, each of which has a control gate and a floating gate. “0” or “1” depending on whether or not
Nonvolatile memory transistors that store this information and are set to "1" before writing data are arranged in a matrix of a plurality of rows and a plurality of columns. 2 is a decoder that selects 4 lines from all the word lines of the memory cell array, 3 and 4 are more specific 1 from the selected word lines
Row selection transistors for selecting only word lines of the book, 5a to 8a and 5b to 8b are divided word lines, and the word lines 5a to 8a are provided corresponding to the memory cell array 1a. A word line group connected to the control gates of a plurality of memory transistors arranged in the corresponding row of
5b to 8b are provided corresponding to the memory cell array 1b, and constitute a word line group connected to the control gates of a plurality of memory transistors arranged in the corresponding row of the memory cell array 1b. Reference numerals 9 and 10 are signals from the address buffer, D0 to D7 are write data, and write data D0 to D3 is one selected for each of the four blocks D0 to D3 divided into blocks in the memory cell array 1a. The write data D4 to D7, which are data to be written in the memory transistor, are divided into four blocks D4 to D4 in the memory cell array 1b.
Data for writing to one memory transistor selected for each block of D7. By taking the NAND of the signals of the write data D0 to D3, D4 to D7, 11 is written by adding the same level as the normal selected word line to the divided word line of the divided memory cell array that the memory transistor needs to write, 4-input NAND (stress reduction circuit) that controls the pre-decoder to reduce the voltage applied to the memory transistor to the same level as the unselected divided word line in the divided word line of the divided memory cell array where the memory transistor does not require writing This 4-input NAND 11a is a memory cell array 1a
Corresponding to each block in the four blocks D0 to D3 of the memory cell array 1a, one selected memory transistor, write data D0 to D3 for a total of four selected memory transistors, and write these A control signal output circuit that outputs a non-selection signal when all of the data D0 to D3 are "1" and outputs a selection signal at other times, and a 4-input NAND 11b is provided corresponding to the memory cell array 1b, 4 blocks of memory cell array 1b
Each block in D4 to D7 has one selected memory transistor, write data D4 to D7 for a total of four selected memory transistors are received, and it is unselected if all of these write data D4 to D7 are "1". A control signal output circuit that outputs a signal and outputs a selection signal at other times is configured. 12a and 12b are signals from the address buffer 9,1
Signals C0L to C3L, ▲ ▼ to ▲ ▼, C0R to C, which are sent to the transistors 3 and 4 for row selection in response to the signal of 0 and the circuit 11
It is a predecoder that generates 3R, ▲ ▼ to ▲ ▼. In the predecoder, 133 has 3 inputs A
ND, 134 and 135 are three-input ANDs with one negative input, and 136 is a three-input AND with two negative inputs. The decoder 2, the predecoders 12a and 12b, and the row selecting transistors 3a, 3b and 4
Address signal and above control signal output circuit by a and 4b
Receives the output from 11a, 11b, and outputs the non-selection output signal. Write "0" to the word line selected by the input address signal in the word line group corresponding to the control signal output circuit that outputs the selection signal while applying the same level potential as the unselected word line. This constitutes a word line selection decoder for applying a high voltage which is a potential for

Further, FIG. 4 shows a circuit configuration of an EPROM incorporating the above-described circuit of the embodiment. In the figure, 22 is a row decoder, 23 is a column decoder, 24 is a row address input buffer, 25 is a column address input buffer, 26 is a sense amplifier, 27 is an input buffer,
28 is an output buffer. The row decoder 22 of FIG. 4 includes the decoder 2 and transistors 3 and 4 of FIG. The predecoder 12 shown in FIG. 4 is equivalent to the circuits 12a and 12 shown in FIG.
Corresponds to b.

If the EPROM is 128k, for example, one word line is selected from the vertical 512 word lines. The method is that the decoder 2 first selects four word lines from the 512 word lines. , And one of four signals is selected from the signal of the circuit 12. That is, the circuit 12 alone cannot directly select one from the 512 word lines.

The EPROM memory cell array is divided into eight blocks D0 to D7 as shown in FIGS. 1 and 2, but when writing data, one memory cell is written for each block, and a total of eight memory transistors are written simultaneously. It is done.

D0 to D7 are "0" (low) or "1" (high) input from the data input / output terminal of FIG. 4 when writing.
8 data signals, and the stress reducing circuit shown in FIG. 4 is shown in FIG. The circuits 11a and 11b take the NAND of the signals D0 to D3 and D4 to D7.

Next, the operation will be described with reference to FIG. A case of writing data to a memory transistor selected by an address signal in memory cell arrays 1a and 1b will be described. Since this embodiment is intended for an EPROM, in the initial state of writing to the memory transistor, it is assumed that no electrons are stored in the floating gate of the memory transistor, that is, the stored content is "1". It is what First, the decoder 2 selects word lines 5 to 8 out of all word lines.
Select. On the other hand, the pre-decoder 12 receives the signal from the address buffer, and receives C0L to C3L, ▲ ▼ to ▲
The signals ▼, C0R to C3R, and ▲ ▼ to ▲ ▼ are sent to the row selecting transistors 3 and 4 to select one of the word lines 5 to 8. Here, if the write data D0 to If D3 is all "1", that is, the same as the stored contents before writing (initial state), the predecoder 12a uses the signals of the NAND circuit (stress reduction circuit) 11a and the signals of the address buffers 9 and 10 as memory. A potential of the same level as a word line that is not selected by the address signal input to any of the word lines 5a to 8a of the cell array 1a is applied, that is, in the same way that no word line 5a to 8a is selected. To be done. That is, the memory cell array 1a
When the write data to the four memory transistors selected by the address signal to be written to all are "1", that is, when it is not necessary to inject electrons into the floating gate of the memory transistor, the word corresponding to the memory cell array 1a is written. The word lines in the line group are set to the same level as non-selected so that high voltage is not applied. On the other hand, the memory cell array 1b also performs the same processing when the write data D4 to D7 are all "1".

As described above, in the present embodiment, regardless of the content of the write data in the related art, the high voltage is applied to the gates of all the memory transistors connected to the word line to which the memory transistor to be selected is connected. The cell array is divided into two, and the high voltage is applied only to the word line of the memory cell array, which is one of the divided memory cell arrays and to which the memory transistor whose write data is “0” is connected. Since the gate voltage is applied, the number of times the stress voltage is applied is significantly reduced, and there is an effect that gate extraction is less likely to occur.

For example, assume that the write data D0 to D7 are 1,1,1,1,1,0,0,1. Then, the write data D0 to D3 are all "1".
Therefore, the high voltage is not applied to the word lines 5a to 8a, and only one of the word lines 5b to 8b is applied with the high voltage. That is, since no high voltage is applied to the memory transistors in the memory cell array 1a, stress voltage is not applied to half the memory transistors as compared with the conventional one. For example, the above example
The 128k type has 256 memory transistors per row, and the conventional example has 256 memory transistors connected to one word line, so at least 8 selected are excluded. In contrast to the stress voltage applied to 248 cells, in the present embodiment, since there are two memory cell arrays, 128 memory transistors are connected to one word line. In the case of the write data described above, no voltage is applied to the gates of the memory transistors of the memory cell array 1a, and at least 124 memory transistors excluding the four memory transistors selected in the memory cell array 1b are used. Although a stress voltage is applied, it is almost halved compared to the conventional example. Conversely, write data D0-
If D7 is 1,0,0,1,1,1,1,1, write data D
Since 4 to D7 are all "1", the high voltage is not applied to the word lines 5b to 8b, and the high voltage is applied to only one of the word lines 5a to 8a.
No high voltage is applied to the memory transistor in the memory cell array, and if the write data D0 to D7 are all "1", no high voltage is applied to the memory transistor in the memory cell arrays 1a and 1b.

Therefore, the number of stress voltages applied to the memory transistors when writing data to all the memory transistors in the memory cell arrays 1a and 1b is reduced.

In the above embodiment, the case where the memory cell array is divided into two has been described. However, if the memory cell array is not subdivided so much, the effect of having such a function on the circuit complexity and the chip area is increased. Can be said to be none.

It is also possible to further subdivide the memory cell array. In principle, the more subdivided the memory cell array, the smaller the number of stresses applied to the gate of the memory transistor. That is, in the case of 2 divisions, there are 256 possibilities of data when one word is composed of 8 bits, and there is an effect that stress is reduced for 31 kinds of data. If the memory cell array is divided into four
It is effective in 175 out of 256 ways, and you can expect a great effect in practical use.

Further, it is of course possible to divide the memory array asymmetrically so that the capacity of the divided memory array becomes 1 to 3.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, it has a control gate and a floating gate, and stores “0” or “1” information depending on whether or not electrons are accumulated in the control gate. However, a plurality of non-volatile memory transistors, which are set to “1” before data writing, are arranged in a matrix of a plurality of rows and a plurality of columns, and are provided corresponding to the plurality of memory cell arrays. , A plurality of word line groups having a plurality of word lines connected to the control gates of a plurality of memory transistors arranged in corresponding rows of the corresponding memory cell array, and provided corresponding to the plurality of memory cell arrays. , Each receives write data for a plurality of memory cell transistors of the corresponding memory cell array. , If the write data is all "1", it outputs a non-selection signal, and outputs a selection signal at other times, and a plurality of control signal output circuits, and an output from the address signal and the control signal output circuits. The word line selected by the input address signal in the word line group corresponding to the control signal output circuit receiving and outputting the non-selection signal has the same level as the word line not selected by the input address signal. A word that applies a potential and applies a potential to write "0" to the word line selected by the input address signal in the word line group corresponding to the control signal output circuit that outputs the selection signal. A line selection decoder is provided, and when all the data to be written in the memory cell array divided into a plurality is “0”, the memory By adding the same level as the word line of the non-selected memory cell array to the word line in the re-cell array, when writing to all the memory transistors of the memory cell array, the word line of the divided memory cell array to which the memory transistor to be selected is connected Since a high voltage is applied to the memory cells, the number of times the stress voltage is applied is greatly reduced, and gate extraction is made less likely to occur, even if the word lines belong to the same row, the memory transistor to which the writing is attempted belongs. The same level as that of the normal selected word line can be applied only to the word line of the block, and the number of times the stress voltage is applied to the gate of the memory transistor can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional row selection circuit, FIG. 3 is a diagram showing a configuration in a row direction of a memory cell array, and FIG. First
It is a block configuration diagram of an EPROM in which the circuit of the figure is incorporated. In the figure, 1a and 1b are divided memory cell arrays, 5a to 8a are divided word lines, 2 is a decoder, 3a, 3b, 4a and 4b are transistors, 12a and 12b are predecoders, and 11a and 11b are 4-input NAs.
ND (control signal output circuit). The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Toyama 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corp. Kita Itami Works (56) Reference JP-A-58-171799 (JP, A) JP-A-SHO 58-118093 (JP, A) JP 59-132495 (JP, A) JP 59-135698 (JP, A)

Claims (1)

[Claims] 1. A control gate and a floating gate, which store "0" or "1" information depending on whether or not electrons are accumulated in the control gate,
A plurality of memory cell arrays in which non-volatile memory transistors set to “1” before data writing are arranged in a matrix of a plurality of rows and a plurality of columns, and are provided corresponding to the plurality of memory cell arrays, and each of them corresponds to each other. A plurality of word line groups having a plurality of word lines connected to the control gates of a plurality of memory transistors arranged in corresponding rows of the memory cell array, and the word line groups provided corresponding to the plurality of memory cell arrays, respectively. Receives write data for a plurality of memory cell transistors of a corresponding memory cell array, outputs a non-selection signal when all of the write data is "1", and outputs a selection signal at other times. Not selected by receiving control signal output circuit, address signal and output from the above control signal output circuits Signal is applied to the word line group corresponding to the control signal output circuit that outputs the signal to the word line selected by the input address signal, the same level as the word line not selected by the input address signal. At the same time, a word line selection decoder that applies a potential for writing "0" to the word line selected by the input address signal in the word line group corresponding to the control signal output circuit that outputs the selection signal. A semiconductor memory device comprising: