JPH0743673A - Display device for ohp projector with kinds identification function - Google Patents

Abstract

PURPOSE:To eliminate the revision of a switch, to automatically set a circuit, to simplify operation and reduce a cost by discriminating the kind with a connection cable according to the kind of a connected information processor and programing the data of the circuit matching with the kind for the discriminated signal to a liquid crystal controller. CONSTITUTION:In a display device 6 for an OHP projector provided with the liquid crystal controller inputting a video signal outputted from the information processor 1 and always outputting it, this device is provided with the circuit discriminating the kind of the information processor 1 and a means revising the circuit of the liquid crystal controller by programing according to the signal of the kinds discrimination circuit. When a personal computer 1 outputting a horizontal synchronizing signal and a vertical synchronizing signal is selected, when the plug 9 of the cable 2 from the personal computer 1 is inserted into a connector, the kind selection 1 terminal of the connector is grounded, and the fact that the personal computer 1 is the type outputting R, G, B signals and the horizontal synchronizing signal and the vertical synchronizing signal is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a screen (C
The present invention relates to an OHP projector in which a large number of people can simultaneously see a CRT display by applying the same signal as the (RT) display to liquid crystal.

[0002]

2. Description of the Related Art In a conventional OHP projector display device,
In order to change the model of the information processing device, it is necessary to change the switch of the display device for the OHP projector, and depending on the model of the information processing device, the logic of the horizontal synchronizing signal and the vertical synchronizing signal may be forward or normal. It was necessary to invert, use the horizontal signal, or not use the horizontal signal.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the display device for a projector, it is necessary to change the switch of the display device for an OHP projector, or depending on the model of the information processing device, it is necessary to invert or reverse the logic of the horizontal synchronization signal and the vertical synchronization signal. Since there were various cases where the horizontal synchronizing signal and the vertical synchronizing signal were not used, the circuit became large.

[0004]

DISCLOSURE OF THE INVENTION The present invention is to solve the above-mentioned problems and is a display for an OHP projector having a liquid crystal controller which inputs a video signal output from an information processing device and constantly outputs it. In the apparatus, a model identification function-equipped OH having a circuit for discriminating the model of the information processing apparatus and means for changing the circuit of the liquid crystal controller by programming according to a signal of the model discrimination circuit
A display device information processing device for a P projector is proposed.

[0005]

The display device for an OHP projector of the present invention discriminates the model by the connection cable according to the model of the connected information processing device, and responds to this discrimination signal by the circuit suitable for the model. By programming data in the LCD controller, the circuit is automatically changed.

【Example】

An embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a first embodiment and is an external perspective view showing a state in which a personal computer 1 that outputs a horizontal synchronizing signal and a vertical synchronizing signal is selected. The personal computer 1 is connected to the CRT 4 via the cables 2 and 3. The shape of the connecting portion between the personal computer 1 and the cable 2 is a D-SUB 25-pin male on the personal computer 1 side, and the connecting portion between the CRT 4 and the cable 3 is D.
-SUB high density 15 pin male. Cables 2 and 3
Is connected to the connectors 7 and 8 provided on the display device 6 for the OHP projector mounted on the OHP projector 5 and the plugs 9 and 10.
Have been inserted.

FIG. 2 is a circuit diagram of the first embodiment shown in FIG.
The video cable 2 is arranged between the personal computer 1 and the display device 6 for the OHP projector, and the D-SUB 15-pin female connector as the plug 9 of the cable 2 and the connector 7 of the display device 6 for the OHP projector 6 are connected. -Connecting a SUB 25-pin female to a D-SUB 25-pin female as the connector 7 of the OHP projector display device 6 and the D-SU of the cable 3.
Connect with B25 pin male. The CPU 11 stores an LED 12 indicating a power-on state, a program and configuration data (circuit design data of the field programmable gate array “FPGA” 16) and setting data (data to be given to the circuit designed by the FPGA 16). ROM 13 and RA for storing work memory
M14 and DIP SWIT to set the status of port 1
It is connected to CH1 (15). CPU11 is F
For PGA16, output port for configuration data, output port for setting data, restart (RST)
Output port, port 1 for controlling LCD black and white inversion
To connect.

Next, the operation will be described. When the plug 9 of the cable 2 from the personal computer 1 and the connector 7 are inserted, the model selection 1 terminal of the connector 7 is grounded and the CPU 1
It is determined that the personal computer 1 is a type that outputs the R, G, G signals, the horizontal synchronizing signal, and the horizontal synchronizing signal when the port 2 of 1 is grounded. From the connector 7, the respective signals of R, G and B corresponding to the three primary colors of light and the horizontal synchronizing signal H.H. SY
NC1 and vertical sync signal V.V. SYNC1, R, G, B signals, composite sync signals are CR via cable 3.
To the FPGA 16 and the horizontal synchronizing signal H.T. SYNC1 and vertical sync signal V.V. SYNC1 is applied. R, G, B signals are connected to AD converter and FP
Output to LCD by GA16. H. SYNC1 and P
The clock oscillated from the LL circuit 18 is set to 1 / NH.
The SYNC frequency divider circuit inputs the signal to the phase comparator of the PLL circuit 18, and the oscillation frequency of the clock CLK changes so that the phases match, and the oscillation frequency becomes stable, and the clock CLK becomes the same frequency as the video signal. Clock C
LK is 1 / NH. The signal is sent to the SYNC frequency divider, the R / G / B signal A / D converter and the LCD 17. RG
The signal of B is synchronized with CLK by the A / D converter, divided into 3 bits, and supplied to the LCD 17 through the logic conversion circuit of the FPGA 16. In the logic conversion circuit, D
R output from the A / D converter is controlled by controlling the port 1 of the CPU 11 according to the state of IP SWITCH 1.
The 3-bit input logic of each of G and B is switched to positive logic or negative logic and output to the LCD.

FIG. 3 is an external perspective view of the second embodiment.
Connect in the same way as the connection diagram with the personal computer 1 in Fig. 1. At that time,
The modified video cable 20 is used to connect to the video connector 21. Video connector 21 connected
R, G, and B signals are respectively connected to the video connector 7 and the A / D converter via a buffer, and the H.H. SYNC1, V.I. The signal of SYNC1 is connected to the video connector and FPGA 16 via the buffer. Since the personal computer 19 does not output the composite sync signal, the signal from the video cable 20 is not input to the video connector 7. However, the composite sync of the video connector 7 is connected to the video connector 8 and the separator 22 via the buffer, and the separator 2
2 is connected to the FPGA 16.

The model selection 1 of the video cable 20 is GND
, And the model selection 2 is open. When the CPU 11 recognizes the state in which the model selection 1 is selected from the port 2 and the port 3, the restart signal RST is output to the FPGA 16, and then the configuration data and the setting data corresponding to the personal computer 19 of the ROM 13 are output, and the FPGA 16 is output. Change the internal circuit of. The changed FPGA 16 is an H.264 device from the personal computer 19. SYNC
1, V.I. It becomes a circuit for inputting SYNC1, and outputs the signal from the FPGA 16 to the LCD 17. In addition, H. S
The clock oscillated from the YNC 1 and the PLL circuit 18 is set to 1 / NH. The frequency divider circuit of the SYNC inputs the signal to the phase comparator of the PLL circuit, and the oscillation frequency of the clock CLK changes so that the phases match and the oscillation frequency becomes stable, and the clock CLK becomes the same frequency as the video signal.

The clock CLK is 1 / NH. SYNC frequency divider and R / G / B signals are converted into A / D converter and L
It is sent to CD17. The R, G, and B signals are divided into 3 bits each in synchronization with CLK by an A / D converter, and are supplied to the LCD 17 through a logic conversion circuit. In the logic conversion circuit, the port 1 of the CPU 11 is controlled according to the state of the DIP SWITCH 1 (15), and the R, G, and B 3-bit input logics output from the A / D converter are positive logic or negative logic. And is output to the LCD 17. Further, when the power is turned on, the CPU 11 is connected to an LED 12 for displaying, a ROM 13 for storing configuration data, setting data and programs for the personal computers 1 and 19, and a RAM 14 for use as a work.

From the state where the video cable 20 and the CRT cable 23 of FIG. 3 are connected, the video cable 2 of FIG.
0, the state where the connection is changed to the video cable 24 will be described. Connect in the same way as the connection diagram with the personal computer 1 in Figure 2,
At that time, the changed video cable 2 is used to connect to the video connector 7. The R, G, and B signals from the connected video connector 7 pass through buffers,
Connected to the video connector 24 and A / D converter,
The signal of the composite sync is connected to the video connector 8 and the separator 22 via the buffer.

The personal computer 19 is an H.264 computer. SYNC1 and V.I.
Since the SYNC1 signal is not output, the video cable 2
Signals from 0 are not input to the video connector 7.
However, H.264 of the video connector 7 SYNC1 and V.I. S
The YNC 1 is connected to the video connector 20 and the FPGA 16 via a buffer. The composite sync signal input by the separator is H.264. SYNC2 and V.I. SY
The signal is divided into NC2 signals, and this signal is output to the FPGA 16. The model selection 2 of the video cable 20 is short-circuited to GND, and the model selection 1 is open. CP
In U11, when the model selection 2 is selected from the port 2 and the port 3 and the state is recognized, the restart signal RST is output to the FPGA 16, and then the configuration data and the setting data corresponding to the personal computer 19 of the ROM 13 are output, and the FPGA 16 is output. Change the internal circuit of.

The modified FPGA 16 is a personal computer 19
H. 2 which is a composite sync signal separated from the H. 2 signal via a separator. SYNC2, V.I. It becomes a circuit for inputting SYNC2, and outputs the signal from the FPGA 16 to the LCD 17. In addition, H. The clock oscillated from the SYNC2 and the PLL circuit 18 is set to 1 / NH. The SYNC frequency divider circuit inputs the signal to the phase comparator of the PLL circuit 18, and the oscillation frequency of the clock CLK changes so that the phases match, and the oscillation frequency becomes stable, and the clock CLK becomes the same frequency as the video signal. The clock CLK is 1 / NH.
The SYNC frequency divider and R, G, B signals are sent to the A / D converter and LCD. R, G, B signals are A / D
The converter divides each into 3 bits in synchronization with CLK and supplies it to the LCD 17 through a logic conversion circuit.

In the logic conversion circuit, the DIP SWITCH
The port 1 of the CPU 11 is controlled depending on the state of 1 (15), and the input logic of each 3 bits of R, G, and B output from the A / D converter is switched to positive logic or negative logic, and the LCD 17 is displayed. Is output. Also, the CPU 11
When the power is turned on, the LED 12 for displaying, the ROM 13 for storing the configuration data, setting data and programs for the personal computer 1 and the personal computer 19, and the RAM 14 for use as a work are connected.

Next, the operation of the display device for an OHP projector according to the present invention will be described with reference to the flowchart of FIG. First, clear the RAM 14 (step 1), then m
ode1 (set as work memory in RAM14)
Is stored in step 3 (step 2). The states of model selection 1 and model selection 2 are read and stored in mode 2 (set in RAM 14 as a work memory) (step 3). Next, the contents of mode1 and mode2 are compared, and if they are the same, the process proceeds to step 11 (step 4). If they are different, go to step 5 and the mode2 status is PC1.
If the state is shown, the process proceeds to step 6. Step 6
Then, the contents of mode2 are stored in mode1, the RST signal is output from the CPU 11, and the FPGA16
Is initialized, and then the CPU 11 sets the configuration data and setting data corresponding to the personal computer 1 in the FPGA (step 7), and proceeds to step 11.

If the state of mode 2 does not indicate the state of the personal computer 1 in step 5, the process proceeds to step 8 and m
If the state of ode2 indicates the state of the personal computer 19,
Go to step 9. In step 9, mode1 is mo
The contents of de2 are stored, and the RST is sent from the CPU 11.
A signal is output and the inside of the FPGA 16 is initialized. After that, the CPU 11 sets the configuration data and setting data corresponding to the personal computer 19 in the FPGA 16 (step 10), and proceeds to step 11.

In step 8, if the state of mode 2 does not indicate the state of the personal computer 19, the process proceeds to step 11. In step 11, DIP SWITCH1 (15)
If the state of (1) is not the state of reversing the display of the LCD 17 in black and white, the port 1 is turned off and the logic conversion is set to the normal rotation state, and the display state of the LCD 17 is changed to the normal rotation display state (step 12 ) And proceed to step 3. In step 11, the state of DIPSWITCH1 (15) is
If the display on the LCD 17 is in the black and white inversion state, the port 1 is turned on to set the logic conversion to the inversion state, and the LCD 17 display state is changed to the black and white inversion state (step 13). move on.

Although the PLL circuit 18, the separator, the A / D converter and the like are used outside the FPGA 16 in the present invention, they may be set inside the FPGA 16. Further, in the present invention, although the personal computer is explained as two models,
It is possible with more than three models.

[0020]

According to the present invention, the display device for the OHP projector is
The input video signal eliminates the need to change the switch, and the circuit can be set automatically, which simplifies the operation and reduces the cost.

[Brief description of drawings]

FIG. 1 is an external perspective view of a first embodiment.

2 is a circuit diagram of FIG.

FIG. 3 is a second external perspective view.

FIG. 4 is a circuit diagram of FIG.

FIG. 5 Flow chart

[Explanation of symbols]

 1 PC 2 Cable 3 Cable 4 CRT 5 OHP Projector 6 OHP Projector Display Device 7 Connector 8 Connector 9 Plug 10 Plug 11 CPU 12 LED 13 ROM 14 RAM 15 DIP SWTCH1 1 16 FPGA 17 LCD 18 PLL Circuit 19 PC 20 Cable 21 Connector 22 Separator 23 Cable 24 Cable

Claims (1)

[Claims] 1. An OH having a liquid crystal controller which inputs a video signal output from an information processing device and constantly outputs the video signal.
A display device for a P projector has a circuit for discriminating the model of the information processing device, and means for changing the circuit of the liquid crystal controller by programming in response to a signal from the model discriminating circuit. With O
Display device for HP projector.