JPH0737108A - Data communication system - Google Patents

Abstract

PURPOSE:To prevent redundant data transfer and to simplify a pipeline processing by preparing the copy of redundant data. CONSTITUTION:A central processing unit (CPU) 101, a main memory 102 accessed by CPU 101, a communication memory 103 connecting a system bus 106 and a graphics processor 104, the graphics processor 104 receiving plotting data through the communication memory 103 and executing a plotting processing, a display 105 displaying a graphic plotted by the graphics processor 104 and a system bus 106 conencting CPU 101, the main memory 102 and the communication memory 103 are provided. All apex data outputted from CPU 101 are transmitted to the graphics processor 104 and data are copied as the attributes of respective apexes without transferring data on the system bus 106 for a mode where a unique attribute is given to an apex string by the rewriting of a mode register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CPU).
The present invention relates to a data communication method for transferring the drawing data generated in (1) to the graphics processing device.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable progress in the development of a device for creating drawing data by a computer and displaying the drawing data on a display device. In addition, many products have been announced in which devising to speed up drawing is performed by causing dedicated hardware to perform graphics processing. At this time, the transfer amount of the system bus for transferring the data greatly affects the speeding up of the processing.

A conventional data communication system will be described below. FIG. 4 is a diagram showing a configuration of a conventional data communication system. In FIG. 4, 401 is a central processing unit (CPU), 402
Is a main memory accessed by the CPU 401, and 403 is a FIFO connecting the system bus 406 and the graphics processing device 404.
An O (first-in first-out) memory, 404 is a graphics processing device that receives drawing data via the FIFO memory 403, and performs drawing processing, and 405 is a graphics processing device 404.
A display that displays the shapes drawn by 406
Is a system bus connecting the CPU 401, the main memory 402 and the FIFO memory 403. In addition, a FIFO memory 403
Will be described in detail. FIG. 5 shows the internal structure of the FIFO memory. In FIG. 5, 501 is a FIFO memory, 502 is a system data bus connected to the FIFO memory 501, 503 is a graphics data bus for transmitting the data output from the FIFO memory 501 to the graphics processing device 404, and 504 is a multiplexer 505. An input counter for outputting a control signal, 505 a multiplexer for transmitting the data input from the system data bus 502 to the storage area 506, 506 a storage area for holding the input data, 5
Reference numeral 07 is an output counter that outputs a control signal to the selector 508, and reference numeral 508 is a selector that selects the data output from the storage area 506 and transmits it to the graphics data bus 503.

The operation of the conventional data communication system configured as described above will be described below. Here, it is assumed that the drawing data is given as a row of vertices forming a figure such as a line segment or a polygon. First, the CPU 401 extracts drawing data from the main memory 402 and outputs the drawing data to the FIFO memory 403. This operation is performed independently of the operation of the graphics processing device 404. CPU401
The operation of the FIFO memory 403 which receives the drawing data from will be described below. In FIG. 5, the system data bus
The FIFO memory 501 receives data from 502. The multiplexer 505 stores the input data in the storage area 506 according to the value indicated by the input counter 504. Further, thereafter, the value of the input counter 504 is incremented. Further, when the next data is input, it is similarly stored in the storage area 506 indicated by the input counter 504, and the input counter 504 is incremented. In this way, drawing data is accumulated in the storage area 506. Next, the graphics processing device 404 connected to the graphics data bus 503.
Output counter 507
The selector 508 selects data in accordance with the value indicated by, the drawing data is extracted from the corresponding storage area, and is output onto the graphics data bus 503.

FIG. 6 is a diagram showing a conceptual operation of the conventional FIFO memory. The data given from the system data bus as shown in FIG.
It is stored in the IFO memory and is output in the above order in accordance with the request of the graphics processing device. In this way, the CPU 401 can transfer data independently of the operation of the graphics processing device 404.

[0006]

However, in the above-mentioned conventional example, attributes such as color data are added to each vertex of a vertex row representing a figure, and only one vertex row representing a figure is identified. If the required amount of data differs between when the attribute is added and when only the required data is transferred to the system bus, the processing flow will be changed by conditioning when the data is received in the graphics processing device. Necessity arises, and as a result, the number of steps increases due to the determination of conditions, which causes an increase in processing programs and processing time. Also, if the graphics processing flow is made single, it is necessary to give redundant data when a unique attribute is added to the vertex row representing a figure, and the data transferred on the system bus There was a problem that the amount would increase. The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a data communication system that prevents redundant data transfer and simplifies pipeline processing.

[0007]

In order to achieve the above-mentioned object, the present invention provides a data communication system that uses a central processing unit (CP).
U), a main memory accessed from the CPU, a graphics processing device accessed from the CPU,
A system bus connecting the CPU, the main memory and the graphics processing device, a communication memory connecting the graphics processing device and the system bus, and a display device for displaying an image signal output from the graphics processing device. The CPU includes means for extracting from the main memory the data of the vertices forming the element to be drawn and outputting the data to the communication memory, and the communication memory includes a plurality of vertex-unit data. A storage area for holding each storage area is provided, and the storage area is output to the system bus for the specified storage area, and means for specifying the storage area according to an address output to the system bus. First mode that requires a means to store data and different attributes for all vertex data , And a means for switching a second mode in which the attribute of the first vertex data is represented as a representative and the second and subsequent vertexes have the attribute serving as the representative. In the first mode, data is transferred from the system bus. Means for holding the attribute data for all the vertices in the storage area,
In the second mode, there is provided means for copying and retaining the attribute of the first vertex for the attribute which is unnecessary in the second vertex data among the attributes of the first vertex data transferred first, In the first and second modes, there is provided means for outputting the vertex data in the storage area according to the address output from the graphics processing device.

[0008]

According to the present invention, with the above configuration, the data transfer amount on the system bus can be reduced by preparing redundant data duplication, and the processing flow of the graphics processor can be unified. . Further, by having a mode switching means, it is possible to deal with the case where different attributes are added to each vertex.

[0009]

EXAMPLE An example of the present invention will be described below. FIG. 1 is a diagram showing a configuration of a data communication system in an embodiment of the present invention. In FIG. 1, 101 is a central processing unit (CPU), 1
02 is a main memory accessed by the CPU 101, 103 is a communication memory that connects the system bus 106 and the graphics processing device 104, 104 is a graphics processing device that receives drawing data via the communication memory 103, and performs drawing processing, 10
5 is a display for displaying graphics drawn by the graphics processing device 104, 106 is the CPU 101, main memory 10
2. A system bus connecting the communication memory 103. The communication memory 103 will be described in detail below. FIG. 2 is a diagram showing the internal structure of the communication memory. In FIG. 2, 20
1 is a communication memory, 202 is a mode register for setting a mode of data transfer, 203 is a system address bus which is a part of the system bus, 204 is a system data bus which is a part of the system bus, and 205 is a graphics processor. A graphics address bus for connection, 206 is a graphics data bus for connecting to a graphics processing device, 207 is an upper address to which a higher value of the system address bus 203 is transmitted, and 208 is a lower value of the system address bus 203. Lower address, 209 is a multiplexer that conveys data from the system data bus 204 to the selected multiplexer 210, 210 is a multiplexer that conveys the data provided from the multiplexer 209 to the selected storage area 212, and 211 is provided from the multiplexer 210-a. Data and other multiplexers 210-b, 210-c, 210-n Selectors from given data selected and transmitted to the storage area 212, a storage area for storing given data 212, 2
13 selects the data stored in the storage area 212,
This is a selector for outputting to the graphics data bus 206.

The operation of the data communication system of the present invention configured as described above will be described below. here,
The drawing data is given as a sequence of vertices forming a figure such as a line segment or a polygon, and the vertex color is given as the vertex attribute. First, the operation in the first mode in which different attributes are added to all the vertices of the vertex row given from the CPU 101 will be described. CPU
101 is the system address bus 20 of the system bus 106
3 outputs the address of the communication memory 201 to the system 3 and simultaneously outputs drawing data (vertex row) to the system data bus 204. In the communication memory 201, the multiplexer 209 determines which multiplexer 210 to transmit according to the upper address 207 and transmits the data. Here, it is assumed that the multiplexer 210-a receives the data. The multiplexer 210-a transfers the data to the storage area 212-a according to the lower address 208. The CPU 101 sequentially outputs the data (each coordinate value) regarding the vertex, and the communication memory 201 stores the data according to the given address. The vertex color is stored in the color position of vertex 1 in the storage area 212-a in FIG.
Further, the CPU 101 outputs data regarding vertex 2. Similarly, the data of the vertex 2 is the multiplexer 209,
It is stored in the storage area 212-b via the multiplexer 210-b. Regarding the color of the vertex 2, the signal output from the multiplexer 210-b is selected by the selector 211 according to the signal from the mode register 202 and stored in the term of the color of the vertex 2 of the storage area 212-b. Hereinafter, similarly, the signal of the multiplexer 210-c is similarly selected by the selector 211-c and stored in the storage area 212-c. The data relating to the vertices stored in the storage area 212 as described above is a line of data as indicated by 301 in FIG. The selector 213 selects the data in the storage area 212 according to the address signal output from the graphics processing device 104 to the graphics address bus 205,
Output to the graphics data bus 206.

Next, if the drawing data output by the CPU is composed of only the vertex row and the attributes for the first vertex, that is, if only one attribute is defined for one vertex row, the second The operation of the modes will be described below. Here, the mode register 202 is some means
It is assumed that the update is performed by (example: rewriting by CPU access). The CPU 101 outputs the address of the communication memory 201 onto the system address bus 203 of the system bus 106 and, at the same time, outputs drawing data (vertex row) to the system data bus 204. In the communication memory 201, the multiplexer 209 determines which multiplexer 210 to transmit according to the upper address 207 and transmits the data.
Here, it is assumed that the multiplexer 210-a receives the data. The multiplexer 210-a transfers the data to the storage area 212-a according to the lower address 208. The CPU 101 sequentially outputs the data (each coordinate value) regarding the vertex, and the communication memory 201 stores the data according to the given address. Further, the color of the vertex is stored in the position of the color of vertex 1 of FIG. 2, and at the same time, the signal of the multiplexer 210-a is selected by the selector 211 according to the instruction of the mode register 202, and the storage area for storing the data of vertex 2 and thereafter. All the color data of the vertex 1 is stored in the color term of 212. Further, the CPU 101 outputs data regarding vertex 2. Similarly, the data of the vertex 2 is stored in the storage area 212-b via the multiplexer 209 and the multiplexer 210-b. The CPU 101 does not need to output the colors after the vertex 2. The data relating to the vertices stored in the storage area 212 as described above has a line like 302 in FIG. This is selected by the selector 2 according to the address signal output from the graphics processor 104 to the graphics address bus 205.
13 selects the data in the storage area 212 and outputs it to the graphics data bus 206.

As described above, according to this embodiment, the CPU
All the vertex data output from the device can be transmitted to the graphics processing device, and data is transferred on the system bus for the mode in which only one attribute is given to the vertex string by rewriting the mode register. The data can be duplicated as the attribute of each vertex without any matter, and the processing contents of the next-stage graphics processing device can be made exactly the same in either mode.

[0013]

As described above, according to this embodiment, the first
By adding the attribute to all the vertices by the mode of, and by switching the mode register, the attribute of the first vertex 1 of the vertex sequence is duplicated and stored as the attribute of all the vertices by the second mode. Since the attributes of other vertices are given without transferring redundant attribute data on the system bus, the amount of data transferred on the system bus can be reduced, and the second mode as well as the first mode can be reduced. However, since the graphics processing device in the next stage is given an attribute for each vertex, it is not necessary to change the flow of processing, and by reducing the number of steps of graphics processing, it is possible to reduce the program size and process at high speed. This has the effect of realizing an excellent data communication method that enables it.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data communication system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a communication memory according to an embodiment of the present invention.

FIG. 3 is a diagram showing an arrangement of data in a communication memory according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional data communication system.

FIG. 5 is a diagram showing an internal configuration of a FIFO memory of a conventional data communication system.

FIG. 6 is a diagram showing an arrangement of data in a FIFO memory of a conventional data communication system.

[Explanation of symbols]

101, 401 ... Central processing unit (CPU), 102, 402 ... Main memory, 103, 201 ... Communication memory, 104, 404 ... Graphics processing unit, 105, 405 ... Display, 106, 406 ...
System bus, 201 ... Communication memory, 202 ... Mode register, 203 ... System address bus, 204, 502 ... System data bus, 205 ... Graphics address bus, 206, 503 ... Graphics data bus, 207 ... Higher address, 208 ... Lower Address, 209, 210, 505 ...
Multiplexer, 211, 213, 508 ... Selector, 212,
506 ... Storage area, 301 ... Data arrangement in mode 1, 302 ... Data arrangement in mode 2, 403,
501 ... FIFO memory, 504 ... Input counter, 507 ... Output counter, 601 ... FIFO memory data.

Claims (1)

[Claims] 1. A system bus connecting a central processing unit (CPU), a main memory accessed from the CPU, a graphics processing unit accessed from the CPU, the CPU, the main memory and the graphics processing unit. And a display device for displaying an image signal output from the graphics processing device and a communication memory connecting the graphics processing device and the system bus, and the CPU configures elements to be drawn from the main memory. Means for extracting the data of the vertices to be output and outputting the data to the communication memory, wherein the communication memory has a storage area for holding a plurality of vertex-unit data, and the storage area is the system. Means for designating the storage area according to the address output on the bus, and further designated storage Means for storing data to be output onto the system bus with respect to frequency, a first mode in which the different attributes for all the vertex data is required,
And a means for switching a second mode in which the attribute of the first vertex data is represented as a representative and the second and subsequent vertices have the attribute serving as the representative. In the first mode, data is transferred from the system bus. The means for holding the attribute data for all the vertices in the storage area, and the attribute which becomes unnecessary in the second vertex data among the attributes of the first vertex data transferred first in the second mode are the first. Is stored in the storage area according to an address output from the graphics processing device in the first and second modes. Data communication method.