JPH07334373A - System and method for emulation - Google Patents

Abstract

PURPOSE:To provide the emulate system for realizing a hardware operable corresponding to the plural instructions of architecture. CONSTITUTION:When a CPU 1 issues the instruction of the first architecture, that instruction is transmitted to a first device control means. When the CPU 1 issues the instruction of the second architecture, this instruction is received by an I/O receiving means 930 inside a sub-controller 100. According to the contents of that instruction, any factor is set in an SMI status 928 and at the same time, an SMI generating means 927 reports SMI to the CPU 1 corresponding to an SMI signal 31. Then, an SMM handler 26 performs prescribed processing corresponding to that factor. Further, an instruction converting means 104 provided with a microcode memory or the like converts the instruction which can be converted by a hardware circuit. Thus, plural instructions is compatible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation system and an emulation method.

[0002]

2. Description of the Related Art In computer systems such as PCs (personal computers), many hardwares having various architectures and softwares corresponding to the respective architectures have been developed according to their applications.
As software assets increase, it is necessary to maintain the original architecture while improving the performance by adopting new devices etc. for the hardware in order to guarantee the operation of the software.

Here, the first computer architecture in which the market size of hardware and software is very large (for example, the architecture used for the personal computer manufactured by IBM) and the second computer architecture in the relatively medium size (for example, Seiko) It is assumed that there is an architecture used for personal computers manufactured by Epson and NEC. Then, it is undeniable that the hardware principle according to the second architecture and the component parts constituting the hardware apparatus have a small software development scale and are not supplied in abundance as compared with the first architecture. Therefore the second
When developing a computer system with the above architecture, it is difficult to supply the component parts at an early stage, and many parts of these component parts have to be developed by themselves.

FIG. 54 is a diagram showing the structure of a conventional hardware. The controller 507, which is a main part, does not use a standard product but depends on its own development. The CPU 501 and the cache memory 503 are connected to the controller 507 by the CPU bus 505. Controller 507
Is designed to correspond to the second architecture, and receives an I / O instruction from the CPU 501 to issue a hardware instruction to the memory batch setting means 513 and the like I / O.
A receiving unit 508, a cache controller 509 that controls the cache memory 503, a RAM controller 511 that controls a RAM 517 that is connected by a CPU bus 505 and operates at high speed, and a PCI bus interface 515 that interfaces with the PCI bus 519.
Etc. are built in. The memory batch setting means 513 includes a RAM 517, a VRAM 521, and a RAM 517 arranged at each address.
Read / write / cache permission / prohibition is set for the OM 531 and memory mapping of the RAM 517 is performed.

The PCI bus 519 is a 32-bit (or 64-bit) bus that has been standardized in the industry with high speed, versatility, and future expandability, and multiplexes addresses and data. ing. PCI bus 51
A VRAM 521 and a HDD 525, which are devices requiring high-speed and large-capacity data transfer, are connected to the device 9. V
The RAM 521 includes a VRAM switching unit 523 that switches VRAM mapping for a specific I / O instruction from the CPU 501. The data in the VRAM 521 is displayed on a display unit (not shown).

The PCI bus 519 is connected via a bridge circuit 527 to a conventional bus 529 which is relatively slow and compatible with conventional devices. And the conventional bus 529
ROM531, FDD535 which stores BIOS etc.
Connected to. A keyboard 537 and an RS232C interface 539 are also connected to the conventional bus 529 via a keyboard controller 536 and a serial controller 538, respectively. Further, the interrupt controller 540 is also connected. The ROM switching unit 533 has a function of changing the mapping of the ROM according to the I / O command from the CPU 501. Also, the keyboard 537
A keyboard unit controller 541 which is a controller on the keyboard side is incorporated therein.

FIG. 55 is a flowchart showing an operation of switching between two kinds of display modes of a first display mode (standard resolution) and a second display mode (high resolution) in the hardware shown in FIG. is there. In S100, C
I / O instruction from PU 501 is I / O address 300H
When it is output to the address, the above-mentioned instruction I
/ O reception means 508 receives and memory batch setting means 5
13, the mapping of the RAM 517 is changed, and read / write / cache for each address is set. The I / O commands are PCI bus 519 and conventional bus 52.
9 through VRAM switching means 523, ROM switching means 5
It is also transmitted to 33 and switches VRAM and ROM. Note that S102 is all performed by hardware logic. In this way, "I / O address 30
Compatibility is maintained by adhering to a second architectural convention such as "0H = data set for switching defined display mode".

[0008]

Now, with the progress of devices such as CPUs, bus systems, and memory systems, R
AM controller 511, cache controller 50
9. The PCI bus interface 515 and the like also need to be designed and changed according to the latest device. However, in such a case, there is a problem that the development schedule and the number of man-hours are very large in order to design the controller 507 according to the second architecture each time. On the other hand, devices that support the first architecture and control the latest CPU and memory systems were developed relatively early,
Available in plenty. Therefore, if the control device developed for the first architecture can be used, such a problem of development schedule and man-hours can be solved.
There is a problem that the device control means cannot be easily used due to compatibility problems such as O and memory map.

In order to solve this problem, an emulation system is desired in which the device control means developed for the first architecture can be used as a component of the hardware of the second architecture. Further, if the idea of such an emulation system is further developed, hardware capable of operating not only the instruction conforming to the second architecture but also the instruction conforming to the first architecture, that is, a plurality of compatible It is desirable to realize various hardware. This is because if such hardware can be realized, not only the second architecture but also the assets of the application program according to the first architecture can be used, and the commercial value of the system is increased. Furthermore,
According to such an emulation system, unlike the case of the software emulation, there is an advantage that both the OS and the first and second architectures can be used.

When operating an application program conforming to the second architecture on the hardware of the first architecture, all the instructions from the application program are converted to the instructions of the first architecture at the stage of OS (operating system). A method of rewriting and executing the program has also been conventionally considered. However, there is a problem that only the dedicated OS can be used and the processing is very slow because it is emulated by software.

Further, as one method for realizing the emulation system, for example, an interrupt called NMI is used as a CP.
A method of performing emulation processing over U can be considered. However, in the NMI, the jump address (the address in which the routine that performs the process corresponding to the interrupt is stored) is stored in the address area that can be easily rewritten by the application program or the like. Therefore, if this address area is rewritten by an application program or the like, emulation processing becomes impossible. Further, in NMI, since the interrupt processing is started in the control mode (real mode, protect mode, virtual 86 mode) at the time of accepting the interrupt, the control mode must be set to the optimum one at the start of the interrupt processing. However, there is a problem that the processing becomes complicated. Further, in NMI, the return address is stacked in the stack area, which may be used by another program. Therefore, if an NMI occurs when there is no room in the stack area, there is a problem that the data stored in the program data area is destroyed. There is also a problem that the stack pointer for setting the stack area is rewritten to an incorrect value by the application program.

[0012] Further, when performing emulation processing for realizing multiple compatibility, how to ensure high speed of the system is a problem, and how to achieve high speed while maintaining compatibility. The issue is how to maintain it.

Further, in order to realize the emulation system, conversion processing of instructions from the CPU is necessary, and this conversion processing is complicated. Therefore, how to realize this with simple hardware while maintaining high compatibility is an issue.

Further, if the emulation system as described above can be realized only by mounting the option board on the personal computer, the commercial value of the system can be increased.

The present invention has been made to solve the above problems, and an object of the present invention is to emulate a hardware capable of operating instructions of a plurality of architectures, that is, a plurality of emulation systems. It is to provide an emulation system that can realize compatibility.

Another object of the present invention is to provide an emulation system capable of maintaining high speed while maintaining compatibility.

Another object of the present invention is to provide an emulation system which can be realized by a simple method such as mounting an option board.

[0018]

In order to achieve the above-mentioned object, the present invention, when the central control means issues an instruction by an instruction system adapted to the first computer architecture, executes the instruction, A second device architecture in which the first device control means controlled by an instruction system adapted to the first computer architecture or means for transmitting to the control target thereof and the central control means are different from the first computer architecture. Means for receiving an instruction and analyzing the instruction when the instruction is issued by an instruction system conforming to, and means for setting factor data indicating the type of the instruction and generating an interrupt to the central control means. , The predetermined process corresponding to the factor, which is activated by the interrupt, is executed at least by the first Device control means or means for executing control target thereof, the control mode of the central control means is shifted to a control mode managed by a predetermined system by the interruption, and the predetermined mode is set in a memory area dedicated to the control mode. It is characterized in that data necessary for the processing of is stored.

According to the present invention, when the instruction issued by the central control means conforms to the first architecture, the instruction is transmitted as it is to the first device control means and the like, and is transmitted to the second architecture. If they match, emulation processing is performed by the execution means. Thereby, multiple compatibility is realized. Further, according to the present invention, the execution means performs the memory management in the unique control mode based on the data stored in the dedicated memory area in the unique control mode without interference from the application program or the like. Is possible.

Further, the present invention is characterized in that the position of an address where data required for the predetermined processing is stored in the memory area can be changed only in the control mode.

According to the present invention, the address position where the data required for the predetermined processing is stored is not rewritten by the application program or the like.
Therefore, it is possible to set the address position at a position desired by the system side, and it is guaranteed that this set position is not changed by an application program or the like.
It is possible to realize a highly compatible emulation system in which malfunction does not easily occur.

According to the present invention, the control mode of the central control means is shifted to a control mode managed by a predetermined system by the interrupt, and the contents of the internal register of the central control means are stored in a memory area dedicated to the control mode. The stored contents of the internal register are returned to the central control means when the control mode ends.

According to the present invention, the contents of the internal register of the central control means when an interrupt occurs are stored in the memory area dedicated to the control mode, and automatically returned to the central control means after the completion of the predetermined processing. Therefore, by the execution means,
If the contents of the internal register are changed, it becomes possible to operate the central control means by the changed contents of the internal register after the end of the predetermined processing.

Further, the present invention is characterized in that the position of the address where the contents of the internal register are stored in the memory area can be changed only in the control mode.

According to the present invention, the address position where the contents of the internal register are stored (stacked) is not rewritten by the application program or the like.
Therefore, it is possible to set the address position at a position desired by the system side, and it is guaranteed that this set position is not changed by an application program or the like.
It is possible to realize a highly compatible emulation system in which malfunction does not easily occur.

Further, according to the present invention, the control mode of the central control means is shifted to a control mode managed by a predetermined system by the interrupt, and the execution means is executed by an instruction system which does not depend on the control mode of the central control means before the interruption. The above-mentioned predetermined processing is performed.

According to the present invention, the predetermined processing can be performed by an instruction system unrelated to the control mode of the central control means before interruption, whereby a program for describing the predetermined processing can be executed. Complication is prevented.

Further, the present invention is characterized in that the interrupt is an SMI interrupt for shifting the central control means to the SMM mode.

According to the present invention, it is not necessary to use the NMI or the normal interrupt INT which is assumed to be already used by many application programs and OS, so that high compatibility can be maintained.

Further, the present invention includes means for controlling a memory device as the first device control means, and means for converting a memory map of the memory device into a memory map adapted to the second computer architecture. It is characterized by

According to the present invention, even if the arrangements of the memory maps are different between the first architecture and the second architecture, a plurality of compatibility can be realized by changing the memory maps.

Further, according to the present invention, when the central control means issues an instruction by an instruction system adapted to the first computer architecture, the instruction is controlled by the instruction system adapted to the first computer architecture. The first device control means or means for notifying the controlled object thereof, and the central control means, when the instruction is issued by an instruction system adapted to a second computer architecture different from the first computer architecture, Means for receiving an instruction and analyzing the instruction;
When the instruction is analyzed as the first type of instruction, the factor data indicating the type of the instruction is set, and a means for generating an interrupt to the central control means, and a means activated by the interrupt to cause the cause Corresponding predetermined processing,
Means for executing at least the first device control means or an object to be controlled by the first device control means, and the instructions so as to be compatible with the first computer architecture when the instructions are analyzed as the second type of instructions. Means for converting and prohibiting bus access of the central control means and issuing the converted instruction on behalf of the central control means.

According to the present invention, for example, the first type of instruction requiring complicated processing is converted by the executing means. Further, for example, for a second type of instruction that requires high-speed processing, instruction conversion processing is performed by a hardware circuit or the like. This allows high-speed emulation processing while maintaining high compatibility.

Further, according to the present invention, when the instruction is the read instruction of the second kind, the processing of the central control means is interrupted, the bus access of the central control means is prohibited, and the converted instruction is converted into the central instruction. It is characterized in that it includes means for issuing the data instead of the control means and transmitting the obtained data to the central control means when the central control means re-executes the processing.

According to the present invention, the data obtained by the converted instruction can be transmitted to the central control means by utilizing the interruption / re-execution of the processing of the central control means.

Further, according to the present invention, when the instruction is the read instruction of the first type, the content of the internal register of the central control means stored in a predetermined memory area can be obtained by the predetermined processing. Means to change based on the data
And a means for returning the changed contents of the internal register to the central control means at the end of the control mode to which the central control means has shifted due to the interrupt.

According to the present invention, the central control means can automatically transmit the data obtained by the emulation processing to the central control means without issuing the read command again.

The present invention further includes means for controlling an interface for data transmission / reception as the first device control means, and the command issued by the central control means is a data transmission / reception command or a status read command. In this case, the instruction is analyzed as the second type instruction, and the conversion processing of the instruction is performed.

According to the present invention, it is possible to convert a data transmission / reception command and a status read command, which require high-speed processing, by a high-speed hardware circuit or the like. Further, the present invention includes means for controlling an interface for data transmission / reception as the first device control means, and when the instruction issued by the central control means is a command write instruction, the instruction is transmitted as the first device control means. 1
It is characterized in that it is analyzed as an instruction of the type, and the conversion processing of the instruction is performed by the predetermined processing of the execution means.

According to the present invention, it becomes possible to execute a conversion process of a command write command, which requires a complicated process, by the execution means capable of describing the process with a predetermined code.

The present invention further includes means for controlling an interface for data transmission / reception as the first device control means, and the instruction issued by the central control means sets a baud rate for data transfer. If it is, the instruction is analyzed as the instruction of the first type, and the baud rate is calculated by the predetermined processing of the executing means.

According to the present invention, for example, even when the baud rate of transmission / reception with respect to the clock is fixed to one by the device control means used in the first architecture,
It is possible to use other types of baud rates.

The present invention further includes means for controlling the data input means as the first device control means, and the command issued by the central control means is a command transmission command, a command write command or a data reception command. The instruction is analyzed as the first type instruction,
The conversion processing of the instruction is performed by the predetermined processing of the execution means.

According to the present invention, it is possible to execute a command transmission command or the like, which requires complicated processing, by executing means capable of describing the processing with a predetermined code.

Further, the present invention includes means for controlling the data input means as the first device control means, and when the instruction issued by the central control means is a status read instruction, the instruction is issued. It is characterized in that it is analyzed as two types of instructions and conversion processing of the instructions is performed.

According to the present invention, the conversion of the status read command, which requires high-speed processing, can be performed by a hardware circuit or the like.

Further, the present invention is characterized in that it comprises means for controlling an interrupt as the first device control means, and a vector conversion means for converting an interrupt vector issued to the central control means. .

According to the present invention, the interrupt vector can be converted according to the first architecture, and the compatibility can be further improved.

Also, the present invention includes means for controlling an interrupt as the first device control means, and when the interrupt acknowledge command is issued by the central control means, the processing of the central control means is interrupted and the central control is performed. It is characterized by including means for prohibiting bus access of the means, newly generating an interrupt acknowledge cycle, and transmitting the converted interrupt vector to the central control means when the central control means re-executes the processing.

According to the present invention, the interrupt vector converted can be transmitted to the central control means by utilizing the interruption and re-execution of the processing of the central control means.

The present invention is also connected to the first bus,
The first bus and the second bus are connected to a sub-controller including means for converting an instruction compatible with the second computer architecture issued from the central control means into an instruction compatible with the first computer architecture. And a bridge circuit for
By controlling a control signal of the first bus input to the bridge circuit, a first device connected to the second bus when an instruction conforming to the second computer architecture is issued. It is characterized by including a means for invalidating the transmission of the command to the control means or its control target.

According to the present invention, the instruction of the second computer architecture can be prevented from being transmitted to the first device control means and the like, and the compatibility can be maintained.

The present invention is also connected to the first bus,
A sub-controller including means for converting a second computer architecture compatible instruction issued from a central control means into a first computer architecture compatible instruction; and a second computer connected to the first bus Second device control means controlled by an instruction system adapted to the architecture, wherein the sub-controller controls a control signal of the first bus input to the second device control means,
When an instruction adapted to the first computer architecture is issued, transmission of the instruction to the second device control means or its control target is disabled, and adapted to the second computer architecture. It is characterized by including means for transmitting the command to the second device control means or its control target when the command is issued.

According to the present invention, it is possible to prevent the instruction of the first computer architecture from being transmitted to the second device control means or the like connected to the first bus.
The instructions of the second computer architecture are communicated. As a result, even if there is a device control means for which this emulation processing is difficult, multiple compatibility can be realized.

The present invention is also connected to the first bus,
A sub-controller including means for converting a second computer architecture compatible instruction issued from the central control means into a first computer architecture compatible instruction; and a first expansion slot connectable to the first bus. And a board that can be inserted into the first expansion slot and that has means for converting a signal of the first bus into a signal of a second bus controlled by an instruction compatible with a second computer architecture. And an expansion slot box including one or a plurality of second expansion slots connectable to the second bus and connected to the board via a cable.

According to the present invention, it is possible to effectively use the hardware resources connectable to the bus of the second computer architecture while minimizing the hardware change of the main unit.

Further, the present invention is an emulation system which, when the central control means issues an instruction by an instruction system adapted to the second computer architecture, converts the instruction into an instruction adapted to the first computer architecture. A microcode memory for storing microcode information including at least command information and emulation address information at an input memory address position; address information included in an instruction issued by the central control means; and the microcode memory. And selector means for selecting any of the emulation address information included in the command information to generate the memory address, the selector means being instructed to continue emulation based on the emulation continuation information included in the command information. The case and generates the memory address selects the emulation address information.

According to the present invention, the emulation cycle can be repeated a desired number of times by instructing the continuation of the emulation by the emulation continuation information, and complicated emulation processing can be easily realized.

Further, the present invention includes data generating means for generating emulation data based on the microcode information from the microcode memory, and the data generating means, based on the emulation continuation information, continues the emulation. Is specified, the generation processing of the emulation data in the (n + 1) th emulation is performed based on the write data from the central control means or the emulation data generated by the nth emulation (n is an integer of 1 or more). Characterize.

According to the present invention, the emulation data generated the previous time can be used to generate the emulation data for the next time, so that a complicated emulation data generation process can be easily realized.

Further, the present invention is an emulation system for converting an instruction into an instruction compatible with the first computer architecture when the central control means issues the instruction according to the instruction system compatible with the second computer architecture. There is a microcode memory for storing microcode information for instruction conversion at a predetermined memory address position, a unit for reading the microcode information from the microcode memory, and based on the read microcode information. Data generating means for generating emulation data, wherein the microcode memory includes at least command information and emulation address information at a first memory address position.
Storing the microcode information, and storing the second microcode information including at least a part or all of the data generation information at the position of the second memory address obtained by converting the first memory address, The read means reads the command information stored in the position of the first memory address in the first memory read cycle, and determines that the data generation processing by the data generation means is necessary based on the command information. If so, the second memory read cycle is activated to read the data generation information stored in the position of the second memory address, and the data generation means reads the data in the first memory read cycle. The read first microcode information and the second microcode read in the second memory read cycle. And performing the data generation process based on the over-de information.

According to the present invention, it is determined whether to activate the second memory read cycle based on the command information read in the first memory read cycle. It can be prevented from occurring.

According to the present invention, the data generation information includes bit definition information, and the data generation means defines the value of each bit of the emulation data based on the bit definition information and performs the data generation process. Is characterized by.

According to the present invention, it is possible to easily realize, for example, bit exchange processing by using the bit definition information.

Further, in the present invention, the first microcode information includes data of a predetermined number of bits, and the command information includes information for instructing to output the data of the predetermined number of bits as emulation data. Is characterized by.

According to the present invention, it is possible to use the data of the predetermined number of bits included in the microcode information as it is as the emulation data.

Further, the present invention is characterized in that the command information includes information instructing that only the address conversion processing is performed and the data conversion is not performed.

According to the present invention, the emulation processing in which the write data of the central control means can be used as it is can be easily realized.

The present invention further includes address decoding means for decoding the address information contained in the instruction issued by the central control means to obtain the memory address, and the address decoding means is issued by the central control means. When the address information included in the instructions is the same, a means for obtaining a different memory address from the same address information is included.

According to the present invention, for example, even when one I / O port is a port capable of reading and writing different data depending on the situation, emulation processing of I / O instructions for the I / O port is performed. Can be realized.

Further, according to the present invention, when the central control means issues an instruction by an instruction system adapted to the second computer architecture, the instruction is converted into an instruction adapted to the first computer architecture, and the first computer architecture is adapted. An emulation system for transmitting information to a first device control means controlled by an instruction system adapted to one computer architecture or a control target thereof, wherein the first device control means generates a first interrupt. In the case of notifying the central control means of the command issuance request, when the first interrupt is generated, the interrupt is received and factor data indicating the type of the instruction is set, and the central control means is set. Means for generating a second interrupt by means of a predetermined interrupt corresponding to the factor that is activated by the second interrupt. And a first execution unit for executing the processing to set the first device control unit or an object controlled by the first device control unit in a state in which an instruction compatible with the second computer architecture can be issued, and the first control unit for the central control unit. And a means for notifying an instruction issuance request.

According to the present invention, the emulation process relating to the device control means for generating the interrupt and requesting the instruction issuance, and even when the complicated process is required, this can be easily realized.

Further, in the present invention, a keyboard controller is included as the first device control means, and the predetermined processing by the execution means converts input data from the keyboard using a data conversion table to perform the central control. The means is a process of storing the converted data in a readable storage means.

According to the present invention, a keyboard input data conversion process that requires complicated processing can be easily realized by using a conversion table.

The present invention further includes a mouse controller as the first device control means, and the predetermined processing by the execution means reads the input data from the mouse by an instruction adapted to the second computer architecture. It is characterized in that it is a process of converting the data into a possible data and storing the converted data in a storage means which can be read by the central control means.

According to the present invention, even if the format of the input data from the mouse is significantly different between the first and second computer architectures, the conversion processing can be easily realized.

The present invention also includes a first sub-controller connected to the first bus to which the central control means is directly connected, said first sub-controller having instructions adapted to the second computer architecture. A first control method adapted to the first computer architecture when the central control means issues an instruction according to the first system
Means for disabling the transmission of the instruction to the device control means or its control target, and converting the instruction issued from the central control means into an instruction compatible with the first computer architecture, Device control means or means for transmitting the converted command to the control target thereof.

According to the present invention, the first bus to which the central control means is connected can be directly controlled by the first sub-controller to perform emulation processing. This makes it possible to provide an emulation system that can be realized simply by mounting an option board or the like. Also, multiple compatibility can be realized even in an information processing device having only the first bus.

Further, according to the present invention, the means for transmitting the command is obtained by the converted command by interrupting the processing of the central control means by controlling the input signal of the central control means and then re-executing the processing. It further comprises means for transmitting data or a control signal from the first device control means at the time of the re-execution.

According to the present invention, for example, the back-off function of the central control means is used to suspend and then restart the processing of the central control means. When a read instruction is issued, the data obtained by emulation is transferred to the write instruction. Sometimes a control signal such as a ready signal can be transmitted to the central control means.

Also, the present invention includes a second sub-controller connected to a second bus different from the first bus, the second sub-controller adapted to the second computer architecture. It is characterized by including a second device control means controlled by an instruction system.

According to the present invention, it is possible to effectively use the second device control means having a function that is not supported by the first computer architecture, for example.

Further, according to the present invention, the first sub-controller connected to the first bus to which the central control means is directly connected, and the second sub-controller connected to the second bus different from the first bus. When the central controller issues a command according to a command system adapted to the second computer architecture,
The second sub-controller includes a means for converting the instruction into an instruction that is not accepted by the first device control means controlled by an instruction system adapted to the first computer architecture or an object to be controlled by the first device control means. A means for converting the instruction issued by the means into an instruction compatible with the first computer architecture, and transmitting the converted instruction to the first device control means or its control target. To do.

According to the present invention, the first bus to which the central control means is connected can be directly controlled by the first sub-controller to perform emulation processing. This makes it possible to provide an emulation system that can be realized simply by mounting an option board or the like. In addition, plural compatibility can be realized even in an information processing device in which only the first bus exists. Moreover, the circuit scale of the first sub-controller connected to the central control means can be reduced, which is advantageous in terms of space.

Further, according to the present invention, in the conversion processing into an instruction in which the first device control means or the control target thereof is not accepted, the information of the address included in the instruction from the central control means is converted into the first device. It is characterized in that it is a process of converting to an address that is not used by the control means or its control target.

According to the present invention, by converting the address of the instruction into an address that is not used by the first device control means or the like, the first device control means or the like can respond to the instruction of the second computer architecture. To be prevented.

Further, according to the present invention, the means for transmitting the instruction is obtained by the converted instruction by interrupting the processing of the central control means by controlling the signal of the second bus and then re-executing it. It further comprises means for transmitting data or a control signal from the first device control means at the time of the re-execution.

According to the present invention, the processing of the central control means is suspended and then restarted by using the retry function or the like realized by the control of the bus signal, and the data obtained by the emulation is written in the case of the read instruction. At the time of an instruction, a control signal such as a ready signal can be transmitted to the central control means.

Further, the present invention is characterized in that the second sub-controller includes second device control means controlled by an instruction system adapted to the second computer architecture.

According to the present invention, it is possible to effectively use the second device control means having a function that is not supported by the first computer architecture, for example.

Further, the present invention is characterized by including means for transmitting an interrupt signal from the second sub-controller to the central control means.

According to the present invention, emulation processing using an interrupt signal is possible in the second sub controller, and an emulation system with higher compatibility can be realized.

Further, according to the present invention, when the first sub-controller has the instruction issued from the central control means conforming to the first computer architecture, the first device control means is provided. Alternatively, it is characterized by including means for transmitting the command to the controlled object.

According to the present invention, when the instruction is compatible with the first computer architecture, the instruction is transmitted without being converted, so that the processing speed can be increased.

Further, according to the present invention, the first sub-controller determines whether or not the instruction issued from the central control means is for the means for controlling the memory device or its control target. , A means for delaying the control start signal of the first bus generated by the central control means.

According to the present invention, it is judged whether or not the memory is accessed, and if the memory is accessed, the bus cycle can be immediately started by the delayed control start signal of the bus. Therefore, it is possible to minimize the decrease in access speed to the memory.

The present invention is also compatible with the second computer architecture B after reset or power up.
A means for activating IOS with priority over a BIOS compatible with the first computer architecture, and whether the instruction issued from the central control means is transmitted without conversion or converted into an instruction compatible with the first computer architecture and transmitted. Means for switching the mode selection based on the instruction from the data input means.

According to the present invention, since the BIOS of the second computer architecture can be activated with priority after a reset or the like, a more compatible emulation system can be realized. Further, since the mode can be selected by the data input means, it is not necessary to provide a switch for selecting the mode. As a result, the casing (the exterior member of the device) having the first architecture can be used.

The present invention also includes a first board having at least a first sub-controller for emulating an instruction issued from the central control means, the first board being the central control means. First connecting means for connecting the first terminal group and the first terminal group of the second socket of the third board having at least the second socket to which the central control means can be attached; A second connecting means for connecting the second terminal group of the central control means and the second terminal group of the second socket via the first sub-controller. .

According to the invention, the central control means is first removed from the second socket on the third board. The first connecting means of the first board allows the first control means of the central control means to operate.
Is connected to the first terminal group of the second socket. Also, the second connecting means connects the second terminal group of the central control means to the second terminal group of the second socket via the first sub-controller. Therefore, it is possible to provide an emulation system which can control a part of the signals from the central control means using the first sub-controller and can be realized only by mounting the first board.

Further, according to the present invention, the first board has a first socket into which the central control means can be mounted and a plurality of pins which can be inserted into a plurality of pin holes provided in the second socket. And a wiring means for connecting the terminal of the first socket, the terminal of the sub-controller, and the terminal of the connection connector.

According to the present invention, the central control means is removed from the second socket and mounted in the first socket,
The emulation system can be realized simply by mounting the connection connector on the second socket.

According to the present invention, the first board may include the central control means, a connector having a plurality of pins that can be inserted into a plurality of pin holes provided in the second socket, and the central control. Wiring means for connecting the terminals of the means, the terminals of the sub-controller, and the terminals of the connection connector are included.

According to the present invention, the first board is provided with the central control means, and the emulation system can be realized only by mounting the connecting connector of the first board in the second socket.

Further, according to the present invention, at least a second sub-controller for performing the emulation processing is provided together with the first sub-controller, and the second sub-controller for connecting to the terminal of the second socket on the third board. It is characterized by including a second board that can be mounted in an expansion slot capable of transmitting a signal between them.

According to the present invention, an emulation system using both the first and second sub-controllers can be realized by connecting the second sub-controller to the expansion slot.

Also, the present invention includes a signal line for transmitting a signal between the first board and the second board, wherein the signal is the second line on the second board.
And an interrupt signal generated from the sub-controller of (1) to the central control means on the first board.

According to the present invention, emulation processing using an interrupt signal is possible in the second sub-controller, and a more compatible emulation system can be realized.

[0109]

EXAMPLES Examples of the present invention will be described below.

(First Embodiment) 1. Description of Overall Configuration FIG. 1 is a block diagram for explaining the hardware of the first embodiment. A difference from the conventional example described in FIG. 54 is that a standard product designed to correspond to the first architecture, that is, a 82434LX (PCMC: trade name) manufactured by Intel Corporation is used as the memory controller 11. (In the conventional example, the original controller 5
07 was used). As described above, in the present embodiment, the memory system (device control means) 11 of the first architecture is mixed in the hardware system adapted to the second architecture. Then, in this embodiment, the sub-controller 25 is provided in accordance with the mixing of the memory controllers 11 as described above, thereby maintaining compatibility.

CPU 1 and cache memory 3 are CP
It is connected to the memory controller 11 by the U bus 5. In the present embodiment, the CPU 1 is an Intel P
A CPU called entium (trademark) is used. This CPU is a CPU whose functionality has been enhanced by pipeline processing or the like. In addition to this, as a bus buffer (not shown), 82433LX LB manufactured by Intel
There is an X, but the explanation is omitted. A cache controller 13 for controlling the cache memory 3 in the memory controller 11, and a RAM controller 1 for controlling a RAM 21 connected by a CPU bus 5 and operating at high speed.
5. A PCI bus interface 19 for interfacing with the PCI bus 23 is provided. Further, in the memory controller 11, a HOLD signal 7 is output to the CPU 1 for weighting, hold weight control means 12 for controlling the operation speed of the CPU 1, and a RESET signal 8 for outputting the RESET signal 8 to the CPU 1. Reset or I to CPU1
A reset register 14 is provided for outputting the NIT signal 9 and performing a soft reset. RAM
Memory setting register 1 provided in the controller 15
7 is R by the operation according to the first architecture.
RAM 21, VRAM 33, ROM 4 mapped to the memory mapping of AM 21 and each memory address
For 3, the read / write / cache availability is set. The memory setting register 17 is the memory controller 11
Is a part of a config register (not shown) for performing various settings of.

The PCI bus 23 is a device that requires high-speed and large-capacity data transfer, that is, VRAM 33 and HDD 3
7 is connected. The VRAM 33 is provided with VRAM switching means 35 for switching the mapping of the VRAM 33 for a specific I / O command from the CPU 1. VRAM
The data of 33 is displayed by a display unit (not shown).
Further, the PCI bus 23 is connected with a sub-controller 25 which is an essential part of the first embodiment. As shown in FIG. 1, the sub-controller 25 has an I / O receiving means 30 for receiving an I / O command from the CPU 1, an SMI status 28 for setting a factor, an SMI generating means 27 for generating an SMI interrupt, SMI mask means 29 for masking the generation of SMI, bus arbiter 70 for arbitrating the PCI bus 23, PC
It includes a PCI bus interface 71 for interfacing with the I-bus 23, reset detection means 73 for detecting reset, speed switching, and power interruption, speed switching detection means 74, power interruption detection means 75, and display switching detection means 76.

Since the memory controller 11 is a controller designed for the first architecture as described above, it cannot receive the I / O instruction based on the second architecture issued from the CPU 1. Therefore, the I / O accepting means 30 in the sub-controller 25 receives the I / O command (the command of the CPU 1 can be passed through the memory controller 11 by itself, thereby the PCI
A device connected to the bus 23 or the conventional bus 41 can directly receive the command), I / O receiving means 3
0 sets a factor in the SMI status 28 according to its contents, and at the same time, the SMI generating means 27 causes the SMI signal 31
Notifies the CPU 1 of the SMI. In other words, the SMI
The CPU 1 is caused to act on behalf of an interrupt process called (system management interrupt). On the other hand, CP
When the instruction from U1 is issued to the device control means of the second architecture, this instruction is directly transmitted to the second device control means. The I / O receiving unit 30 determines whether the command is issued to the first or second device control unit by the CPU.
It is performed by analyzing the instruction from 1. Specifically, the determination is made by decoding the address by the decoder means built in the I / O reception means 30. PCI
The bus 23 is connected via a bridge circuit 39 to a conventional bus 41 which is relatively slow and compatible with conventional devices. Then, the conventional bus 41 has an R for storing BIOS and the like.
It is connected to the OM43 and FDD47. In addition, conventional bus 4
1, a keyboard 49, an RS232 via a keyboard controller 48 and a serial controller 50, respectively.
The C interface 52 is connected. Further, an interrupt controller 54 is also connected to the conventional bus 41. The ROM switching means 45 has a function of changing the mapping of the ROM according to the I / O command from the CPU 1. A keyboard unit controller 55, which is a controller on the keyboard side, is built in the keyboard 49.

FIG. 2 is a diagram for explaining the hardware configuration for switching the memory mapping. RO in Figure 1
Taking the M43 as an example, the ROM main body 66 is composed of a system BIOS that controls the entire hardware and a plurality of expansion BIOS that individually controls peripheral devices such as the HDD 37. Depending on the operating mode of the hardware, these B
Figure 1 shows the assignment of IOS to CPU1 address.
It is changed by the ROM switching means 45. When the I / O command for switching the operation mode is received from the CPU 1, the ROM switching unit 45 switches the internal decoder 62 and the decoder 64 by the switching unit 60. Specifically, the decoder enable signal is generated by the switching signal, and the ROM selection signal is further generated by the selected decoder. The memory setting register 17 and VRAM shown in FIG.
The switching of the memory map in the switching means 35 is performed by the same method.

FIG. 3 is a diagram for explaining the concept of the first embodiment. When an I / O instruction is generated by the application program 80 designed for the second architecture, the OS 82 transmits the instruction to the hardware 84 as it is without being aware of it. Hardware 84 (including BIOS)
Then, the emulation means 86 (the sub-controller 2 in FIG. 1)
5 equivalent to the SMI) emulates the received instruction so that the hardware modification portion 88 (corresponding to the memory controller 11 of FIG. 1) can operate, and the hardware modification portion 88 operates according to the original instruction. Will be possible. When the emulation operation is performed inside the hardware 84 in this way, the compatibility of the second architecture with the application program 80 and the OS 82 can be ensured, and
It also operates faster.

2. Description of SMI Processing Next, SMI processing will be described.

In this embodiment, an interrupt called SMI is used as an interrupt for performing emulation processing. SMI is Intel CPU, SL
Enhanced 486 (trade name), Pentium
This is an interrupt when shifting to SMM (system management mode) supported by (trademark name) or the like. This S
The MI is a function provided in the latest CPU manufactured by Intel Corporation as a special interrupt means for power supply control. The present invention is characterized in that it is used in an emulation system. That is, as one method of realizing the emulation system, for example, a method of performing an emulation process by applying an interrupt called NMI to the CPU can be considered. However, if an attempt is made to implement emulation processing using this NMI, various problems will occur, as will be described later.
On the other hand, the SMI is provided as an interrupt means for power supply control, and there is a problem that it takes a certain time from the input of the SMI signal to the SMI terminal of the CPU until the interruption ends. This is because it is necessary to take a predetermined procedure between the reception of the SMI signal and the end of the SMI processing, and it takes time to perform this procedure. This is not a big problem when using SMI for power control, but there is a problem when performing emulation processing. The inventor first focused on the point that the speed itself of SMI processing does not matter so much for processing such as memory map conversion. Furthermore,
It is thought that this speed problem can be solved by separately handling the emulation processing that requires speed and the emulation processing that does not need it, as shown in a second embodiment described later, and this SMI is used for the emulation processing. It was decided.

Next, the outline of the operation of the SMI processing will be described.

(1) When the system inputs the SMI signal to the CPU, the CPU sends the SMIACT # signal (# is ""
0 "level (indicating that it is asserted) to notify the system to enable SMRAM which is a physical memory dedicated to SMM.

(2) The CPU is in the CPU state (CP
U internal register contents) is the address of SMRAM
Start from location 3FFFFH and save downwards like a stack.

(3) The control mode of the CPU is switched to the processor environment of the SMM (pseudo real mode). This S
The MM is a control mode other than the real mode, protect mode, and virtual 86 mode.

(4) The CPU jumps to the absolute address 38000H of the SMRAM and executes the SMM handler. That is, the SMM handler that operates according to a unique instruction system detects the SMI occurrence factor and executes the designated processing.

(5) The SMM handler restores the CPU state (internal register contents) from SMRAM,
By deasserting the SMIACT # signal, the interrupted program (application program or O
S) execute the RSM instruction that returns control to execution. In addition,
If the setting for relocating SMBASE is performed before executing RSM, the address position where SMRAM is arranged can be changed in the next SMI processing. And in SMI, SMBASE relocate is
It is possible only during SMI processing.

In this embodiment, the SMI described above is used as an interrupt for emulation processing instead of the NMI. The reason is as follows.

(1) Since the SMM handler with the same instruction system can be used in the SMM regardless of the operation mode of the CPU at present, the development is easy. This will be described in more detail below.

That is, in the NMI, the subsequent NMI processing is performed in the control mode (either the protect mode, the virtual 86 mode, or the real mode) of the CPU when the NMI is activated. In the virtual 86 mode and the real mode, the memory address is 16 bits (up to 1 MB), whereas in the protected mode, it is 32 bits (up to 4 G).
B), and the addressing method is naturally different. Therefore, it becomes necessary to program the program so that the program operates normally regardless of which operation mode the NMI processing is performed, and it becomes difficult to develop the program. That is, to change the addressing from 16 bits to 32 bits or from 32 bits to 16 bits in the program, pref
ix may be used. However, it is necessary to set to prefix which one of 16-bit and 32-bit addressing is to be used as a basis in each operation mode. Then, in order to perform this mode setting, it is necessary to write data to the VM bit of EFIAG in the internal register of the CPU. However, this VM bit is protected by the privilege level, and data cannot be written to this VM bit unless it is the highest privilege level.
To set the NMI processing to the highest privilege level, IDT (interrupt descriptor table) is set.
Since it is necessary to specify the DPL value of, the processing becomes more complicated. On the other hand, the SMI does not depend on the control mode of the CPU before the interruption and is always called the SMM called the pseudo real mode.
Enters the mode, and SM with the same command system in SMM
Since the M handler can be used, there is an advantage that the above problem does not occur at all.

Furthermore, when an I / O access is made to the NMI by NMI processing in the protect mode, the I / O
There is a possibility that a trap (I / O of DMA, HDD, etc.) is applied, so if the privilege level is not at the highest level, the correct I
There is a problem that / O access is not possible. Then, in order to set the privilege level to the highest level, the IDT as described above is used.
The process of designating the DPL value of is required.

(2) Further, in the NMI, the jump address for starting an interrupt (the address in which the routine for executing the process corresponding to the interrupt is stored) is an address position which can be easily rewritten by the application program, the OS, etc., for example. It is stored in (0008H to 000BH). Therefore, if this address position is rewritten by an application program or the like,
Interrupt processing becomes impossible. On the other hand, in the SMI, the jump address is SM which is a register in the CPU.
Set to BASE. When the SMI is started, the processing jumps to the start address set by this SMBASE and is executed. In this case, this SMBASE
Can be changed only when returning from SMM by RSM instruction. Therefore, the jump address can be changed in SMM.
If it is not a handler, that is, if it is not in SMM, it cannot be executed. In this respect, SMI has a great advantage over NMI. This will be described in more detail below.

For example, FIG. 4A shows the operation of the NMI processing in the real mode, and FIG. 4B shows the flowchart thereof. When the NMI is accepted (step A1) and the vector 2 is generated (step A2), the interrupt start address (jump address) of the vector 2 is read from 0008H to 000BH of the interrupt pointer table on the main RAM (step A3). And the return address is the main RA
After storing in the stack on M (step A4), jump to the interrupt start address (step A5),
The NMI process is executed according to the routine stored in this interrupt start address. In NMI,
Unlike SMI, the register contents of the CPU are not automatically stored in the stack.

On the other hand, FIG. 5A shows the operation of the NMI processing in the protect mode, and FIG. 5B shows the flowchart thereof. Where main RAM
The start address of the IDT (interrupt descriptor table) stored above is specified by the IDTR which is an internal register of the CPU, and the start address of the GDT / LDT (descriptor table) also stored in the main RAM is the internal register of the CPU. GDTR / L
Specified by DTR. And the IDT has NMI
The offset and the selector for vector 2 generated by are stored, and the GDT / LDT is stored by this selector.
The descriptor stored in is specified. And the upper address and ID specified by this descriptor
An address at which a routine for performing NMI processing is stored according to the lower address specified by the offset on T,
That is, the entry point is designated. The operation in the protect mode is as follows. That is, when the NMI is accepted (step B1) and the vector 2 is generated (step B2), the GDT / LD is selected by the selector in the IDT.
The descriptor in T is designated and read (step B3). Then, the return address is stored in the stack (step B4), the descriptor read in step B3 and the entry point designated by the offset in the IDT are jumped to, and the NMI processing is executed.

As can be understood from the above description, in the real mode, if the interrupt start address (jump address) is not correctly written in (0008H to 000BH), the NMI process should be started from the desired address. However, this interrupt start address is stored in the main RAM and can be easily rewritten by the application program or OS. In NMI, the position where the interrupt start address is stored is fixed, and this position cannot be changed to a position where the application program and the OS cannot access it.

In the protect mode, IDT, G
DT / LDT is the IDTR, GDTR / LD in the CPU
It is located at the address indicated by TR, and these I
DT, GDT / LDT and IDTR, GDTR / LDT
R can be freely set by the application program and OS and can be freely changed. That is, MS-Wi manufactured by Microsoft, which is an OS capable of multitasking
In Windows, each task (window) has an ID
The values of T etc. may differ. Therefore, even if the system side attempts to change the location where this IDT is stored to an address location where an application program or the like cannot access it in order to perform emulation processing, the system side cannot recognize what OS is being used. Therefore, such change processing is impossible. Also, if
Even if the address position is changed, the address position may be rewritten by an application program or the like after that. From the above, it is very difficult to realize the emulation processing as in this embodiment by the NMI.

On the other hand, in the SMI, immediately after the power is turned on or reset, the start address of the SMI process is fixed to the default value 38000H of SMBASE which is an internal register of the CPU. This SMBAS
The default value 38000H of E cannot be rewritten by an application program or the like.
That is, in order to change this 38000H, it is necessary to enter the SMM and use the above-described SMBASE relocate function. Since the SMI can be generated only by a hardware signal called the SMI signal, application programs other than the system cannot enter the SMM. Therefore, the start address of the SMI process is not rewritten by the application program or the like, and in this respect, the SMI is the optimum interrupt used in the emulation process of the present invention.

(3) The status of the CPU (contents of the internal register) is saved in the state save area of the SMRAM at the time of shifting to the SMM, and the contents are C by the RSM instruction.
It is automatically restored to the internal register of PU. As a result, the CPU can be automatically returned to the original state. Further, some registers in this state save area can be read and changed by the SMM handler, and the changed value can be restored to the internal register of the CPU by the RSM instruction. As a result, the contents changed by the SMM handler can be set in the internal register of the CPU.

On the other hand, in the NMI, the return address is automatically stacked in the stack area, but the data in the internal register is not automatically stacked.
In addition, the NMI has the following problems when stacking return addresses and the like in the stack area. For example, in FIG.
As shown in (C), in the stack area, data is sequentially stacked from the address indicated by the stack pointer (SP) toward the smaller address. This stack area may be used not only by the NMI but also by other programs. On the other hand, the program stored in the program data area is executed from the smaller address as shown in FIG. In this case, if
Margin between stack area and program data area (△
When N) occurs when D) becomes smaller than 4 bytes, the data stored in the program data area may be destroyed. Such a collision between the stack area and the program data area can be avoided by, for example, setting the position of the stack pointer (SP) to a position where collision does not occur. However, as shown in FIG. 5C, when the stack area is used by another program or the like and the NMI occurs when the margin between the areas is small, such a collision cannot be avoided. Further, the stack pointer (SP) can be easily rewritten by another application program or the like, and the stack pointer may be rewritten to an incorrect value due to a bug or the like. Further, for example, the following method can be considered as a method of writing a constant in the internal register of the CPU. That is, the stack area is set in the ROM or the like, and (popA, p
data is read from the ROM set as the stack area by an instruction such as opB ...
This is a method of setting the internal registers A, B ... Of the PU. Here, the “popA” instruction means an instruction for reading the data stacked in the stack area and writing it in the A register of the CPU. According to this command, "move"
The program can be simplified as compared with the case of using the instructions such as. However, when this method is used, the stack area is set in the ROM. Therefore, in this state, NMI
When an interrupt occurs due to, the ROM is a non-writable memory, so the return address cannot be written, and therefore the program cannot run out of the NMI and the program may run away. Further, even if the stack area is set in the RAM, the data written in the RAM may be destroyed by the NMI processing.

On the other hand, in the SMI, the contents of the internal register of the CPU are SMRA which is a memory dedicated to the SMI.
Since it is stored in M, the problem that occurred in the above NMI does not occur.

(4) It is assumed that NMI (non-maskable interrupt) and normal interrupt (INT) are used by the application program corresponding to the second architecture, and it is incompatible to allocate other functions unnecessarily. Contrary to maintenance, SMI has a short history and is unlikely to be used by application programs. Also, SMI has a higher priority than NMI and normal interrupts.

(5) When SMI occurs, SMIACT #
The signal is output by the CPU, and the SMI is hardware-based.
It can detect that the routine is entered. For this reason, SMRAM which is RAM for SMI can be arranged at an arbitrary address, and hardware processing can be performed by SMIACT #.
It can also be triggered by a signal.

Next, the operation principle of the SMI processing according to the first embodiment will be described with reference to FIG. In S10, the factor (I
(/ O command) is generated, the I / O receiving means 30 is operated in S11.
Is received by hardware logic
A factor is set in the factor register in the MI status 28, and an SMI is generated in S12. In S13, the SMM mode is entered, the SMM handler 26 (see FIG. 1) reads the factor register (mapping is performed so that all CPUs can read and write the factor register), and processing according to the factor is performed. Return by RSM instruction.

3. Description of Sub-Controller In FIG. 7, the I / O receiving means 3 in the sub-controller 25 is shown.
0, SMI mask means 29, SMI status 28, S
An example of the circuit configuration of the MI generating means 27 is shown. I / O
The accepting unit 30 includes an address latch decoder 200, a timing circuit 202, and AND circuits 204 and 206.
Then, address signals AD15 to AD0 (actually, signals obtained by multiplexing addresses and data) are input to the address decoder latch 200, and AD15 to AD0.
Signal 2 when the address specified by 0 is 200H
14 is "1", and signal 216 is "1" when 300H
become. Further, the timing circuit 202 includes a FRAME
The signal, the CBE3 to 0 signals, and PCICLK are input, and the IOWC signal having a predetermined width is output at a predetermined timing.
That is, when the instruction from the CPU is the I / O instruction and the write mode is set, the IOWC signal becomes "1". Then, the IOWC signal and the signals 214 and 216 generate the IOW200 signal and the IOW300 signal. As a result, the IOW200 signal and the IOW300 signal are asserted when the address input from the CPU is 200H or 300H and the I / O write command.

The SMI mask means 29 includes a mask register 208 and AND circuits 210 and 212. The mask register 208 is a register that stores a signal for masking the SMI, and the timing circuit 20 is connected to the CK terminal.
The write signal 217 is input from No. 2, and the data from AD0 and AD1 is fetched based on the write signal 217. Also, it is reset by PCIRST input to the R terminal. The output of the mask register 208 is input to the AND circuits 210 and 212, whereby the IOW 200
Signals and IOW300 signals can be masked from being transmitted to the subsequent stage.

The SMI status 28 indicates the logic circuit 222.
˜228, factor registers 230, 232, tristate buffers 234, 236. Factor register 23
Reference numerals 0 and 232 are registers for storing the data input from the I / O reception means 30 via the SMI mask means 29 as factor data. For example, if the IOW200 signal is "
If it is 1 ”and the mask is not applied, that is, if the output Q0 of the mask register 208 is“ 1 ”,“ 1 ”is written in the factor register 230. This means that the CPU sends a data write command to the address 200H. This means that the factor of being issued has been set.On the other hand, in order to clear this factor, the output signal 218 of the timing circuit 202 is set to "1" and "0" is set by AD0 and AD1.
According to the present embodiment, it is possible to clear the factor for each of the factor registers 230 and 232, and it is also possible to clear all the factors. The outputs 238, 240 of 232 are tristate buffers 234,
It is controlled by the IORC 40 signal from the factor determination port via 236 and output to the PCI bus 23.
Also, the outputs 238, 24 of the factor registers 230, 232
0 is also output to the SMI generating means 27.

The SMI generating means 27 includes the logic circuits 250-
254, SMI generation register 256. This SMI
The generation register 256 uses the SMI signal 3 when the factor is set in either of the factor registers 230 and 232.
1 is asserted, which interrupts the CPU 1. In addition, the output 24 of the NAND circuits 222 and 224
2, 244 are SMIs through the logic circuits 250 and 254.
It is input to the generation register 256. As a result, when the factors in the factor registers 230 and 232 are cleared, S
The MI signal 31 is also cleared. A PCIRST signal is input to the R terminal of the SMI generation register 256 so that it can be reset.

As described above, in the sub controller 25, when the CPU 1 issues an I / O instruction to the corresponding port, this I / O instruction is stored in the factor registers 230 and 232 as factor data, and at the same time as the SMI.
A signal is generated. Next, the SMM handler (execution means) 26 activated by this SMI signal controls the IORC 40 signal by the factor discriminating port to read these factor data. Then, the SMM handler 26 further executes I / O.
The data of the port such as the address 200H is read to determine the detailed factor. Then, processing corresponding to these factor data and the data written in the port is performed.

The types of factors set in the factor register in this embodiment are roughly classified into the following.

Factor a: emulation of switching display modes, emulation of RAM window, extended RO
I / O port access processing for performing emulation for switching the M area to RAM Factor b: CPU speed switching process Factor c: CPU reset (RESET, INIT) process Factor d: Power off (or power fail) process Above The factor is determined by the first factor register group as shown in FIG. When the factor a is set, more detailed factors (e to h) can be examined by the second factor register group. Similarly, when the factor c is set, a more detailed factor (i, j) can be examined by the third factor register group. As described above, in the present embodiment, the factor register has a hierarchical structure in which the second and third register groups are arranged in the lower order of the first factor register group. It can be done at high speed. That is, if all the factors are arranged in parallel, all the factors must be checked in the first search, but in the present embodiment, four factors can be checked in the first search. Can be fast. Further, in this embodiment, as shown in FIG. 8B, the mask register also corresponds to each factor of the factor register and has a hierarchical structure. For example, if the factor of a is masked (SMI prohibited) by the first mask register, e to
All the factors of h are also masked. On the other hand, when the mask of only the factor a is released in the first mask register (SMI enabled), only the factor corresponding to the bit permitted by the second mask register causes SMI.

FIG. 9 and FIG. 10 show an example of a circuit configuration in the case where the factor register and the mask register have a hierarchical structure as described above. In addition, in FIGS. 11A to 11C, reset detection means 73 and speed switching detection means 7 are shown.
4, an example of a specific circuit configuration of the power failure detection means 75 is shown. Although not shown, the display switching detecting means 76 has the same configuration as these detecting means. CPU1
However, when a predetermined I / O port is accessed, the factors a and factors e to h are set as follows, and an SMI pulse based on these factors is generated. That is, as shown in FIG. 9, the address decode signal from the address latch / decoder circuit 200 and the I / O from the timing circuit 202.
The write pulse IOWC is input to the AND circuits 622 to 625, and the signal 6 which is an SMI pulse due to factors e to h
06-609 are generated. Then, as shown in FIG. 10, these signals 606 to 609 and the output of the second mask register 661 are input to the AND circuits 675 to 678, signals 701 to 704 are generated, and these signals are generated. SMI due to factor a input to OR circuit 679
A pulse is generated. Thereby, it becomes possible to mask each of the factors e to h using the second mask register 661. When an SMI pulse is generated due to any of factors e to h, an SMI pulse is also generated due to factor a. Then, as shown in FIG. 9, the signals 701 to 704 are input to the second factor register groups 654 to 657 via the logic circuits 644 to 647, thereby causing the factors e to h.
Is set. On the other hand, as shown in FIG. 10, the SMI pulse due to the factor a and the output of the first mask register 660 are input to the AND circuit 670, and the signal 70
6 is generated. As a result, when the factor a is masked, the factors e to h are also masked. And
As shown in FIG. 9, the signal 706 is transmitted through the logic circuit 640 to the factor register 6 which is one of the first factor register groups.
It is input to 50, and the factor a is set accordingly.
That is, when the factors e to h are set, the factor a is also set.

In FIG. 11B, when the speed changeover switch 738 is closed or opened and the speed changeover process is started, a D-flip-flop (hereinafter referred to as DFF) is started.
740, 742 and the logic circuit 744 generate a signal 721 that is an SMI pulse due to factor b. As shown in FIG. 10, the signal 721 and the output of the first mask register 660 are input to the AND circuit 671 and the signal 707 is generated. That is, the factor b can also be masked by the mask register. The signal 707 is output to the logic circuit 641 as shown in FIG.
Is input to the factor register 651, which is one of the first factor register group, to set the factor b.

In FIG. 11A, when the reset switch 730 is closed and the hard reset process is started, D
By the FFs 732 and 734 and the logic circuit 736, the factor i
A signal 720, which is an SMI pulse due to On the other hand, when the I / O write processing for the soft reset is performed, as shown in FIG.
Address decoder signal from 00 and timing circuit 20
I / O write pulse IOWC from 2 causes factor j
A signal 605, which is an SMI pulse due to As shown in FIG. 10, these signals 720, 605 and the third
Output of the mask register 662 of the AND circuit 680, 6
81, the signals 710 and 711 are generated, and these signals are input to the OR circuit 682 to generate the SMI pulse due to the factor c. Thereby, it becomes possible to mask each of the factors i and j using the third mask register 662. When an SMI pulse due to any of factors i and j occurs, an SMI pulse due to factor c also occurs. Then, these signals 710, 711
9 is input to the third factor registers 658 and 659 via the logic circuits 648 and 649, whereby the factors i and j are set. On the other hand, as shown in FIG. 10, the SMI pulse due to the factor c and the output of the first mask register 660 are input to the AND circuit 672, and the signal 708 is generated. As a result, when the factor c is masked, the factors i and j are also masked. Then, as shown in FIG. 9, the signal 708 is input to the factor register 652 which is one of the first factor register group via the logic circuit 642, and the factor c is set by this. That is, when the factors i and j are set, the factor c is also set.

In FIG. 11C, when the Power-ok signal from the power supply unit falls and the power-off process is started, the DFFs 748, 750 and the logic circuit 752 are started.
As a result, a signal 722 that is an SMI pulse due to the factor d is generated. As shown in FIG. 10, the signal 722 and the output of the first mask register 660 are input to the AND circuit 673, and the signal 709 is generated. And signal 70
As shown in FIG. 9, the reference numeral 9 designates a first circuit via a logic circuit 643.
Is input to the factor register 653, which is one of the factor register groups, and the factor d is set accordingly.

Finally, as shown in FIG.
˜709 are S through the OR circuit 674 and the logic circuit 691.
It is input to the MI generation register 692, which causes the SMI
The signal 31 is output. The causes of the cause registers 650 to 659 shown in FIG. 9 can be cleared by inputting the I / O write pulses IOWC100, IOWC200, and IOWC300 via the NAND circuits 630 to 639. Then, as shown in FIG.
~ D is cleared, signals 601-6
The logic circuit 690 to which 04 is input also clears the SMI generation register 692, and the SMI signal 31
Is deasserted. Further, the mask data is set in the first to third mask registers 660 to 662 by setting IOW which is an I / O write pulse signal for mask writing.
It will be performed by C400 to IOWC600.

FIGS. 12A and 12B show flowcharts of the above processing. For example, when the I / O write process for the factor e is performed (step C
1) If not masked, the factors e and a are both set in the SMI status (step C2), which causes SMI and shifts to SMM (step C9,
C10). The same applies to the I / O write processing for the factors f, g, and h. Further, when the speed switching detection process of the factor b is performed (step D1), if it is not masked, the factor b is set in the SMI status (step D2). As a result, an SMI occurs and the process proceeds to SMM (step D9). , D10). Further, when the reset switch detection processing is performed (step D3), if not masked, the factors i and c are both set in the SMI status (step D4), which causes SMI and S
The process proceeds to MM (steps D9 and D10). The same applies to the CPU soft reset processing and power-off processing.

As described above, in the present embodiment, the factor register has a hierarchical structure and each factor can be masked, so that the following effects can be obtained.
First, since the first factor search only needs to be performed for the factors a to d, the factor search can be speeded up. Secondly, by masking these factors having a hierarchical structure, it is possible to set priorities for factors and SMI occurrence. As a result, as will be described later, the emulation processing for changes in the operating environment of the system such as power interruption can
The priority may be higher than that of the emulation processing of O port access. Third, depending on the mode of the computer system, there is emulation processing that should not be operated (for example, VRA for high resolution display).
M, IPF), in such a case, by masking the corresponding factors, it is possible to prevent the emulation processing from operating.

FIG. 13 shows an example of a signal waveform diagram for setting factor data. 1 when the FRAME signal is asserted and the PCI bus access cycle is started
At the clock, the address latch / decoder 200 and the timing circuit 202 latch the address signals AD0-31 and the command signals CBE0-3, and assert the IRDY signal. Then, two clocks later, the timing circuit 202 asserts the I / O write pulse IOWC signal, thereby setting the factor in the factor register, and asserting the SMI signal 31 to start the SMI processing. When both the IRDY and TRDY signals are asserted, the bus access cycle ends. In FIG. 13, a process for clearing the cause is performed in the next bus access cycle, which causes the SMI.
The signal 31 will be deasserted.

4. Description of Operation of Entire System FIGS. 14 and 15 are flowcharts showing the operation of the present embodiment after entering the SMM mode. First,
In step E1, SMM mode is entered and SMM handler 2
When 6 starts, the config register of the PCMC 11 is opened, and the setting of prohibiting the Deterbo function of the PCMC 11 is performed. That is, the hold weight control means 1
2 (see FIG. 1) to CPU 1 wait (HOL
The CPU 1 is operated at a high speed by setting the mode in which the D signal 7) is not input. As a result, the CPU 1 operates at the maximum speed in the subsequent emulation processing, and the processing speed can be increased. The operation speed changeover switch of the CPU 1 is a switch provided for an application program that cannot operate at high speed, or an application program that is inconvenient for high speed operation (for example, an action game), and the like. The faster the operating speed of the CPU 1, the better. Therefore, in this embodiment, such a setting is made. In the present embodiment, the change of the operating speed of the CPU 1 is described as changing the operating environment of the system, but the present invention is not limited to this. For example, various changes in the operating environment are conceivable, such as making the I / O port unique to the manufacturer's system visible on the I / O space during the emulation process. That is, during the emulation process, the operation of the application program or the like used by the user is interrupted by an interrupt. Therefore, even if the manufacturer's system-specific I / O port is visible during this period, this I / O
The port is never accessed by an application program or the like. By making the manufacturer's system-specific I / O ports visible in this way, it is possible to increase the number of I / O ports that can be used during emulation processing, thus increasing the degree of freedom in designing the emulation system. Can be increased. The method for changing the operating environment of the system described above is not limited to the emulation system as described in the present embodiment, but can be widely applied to emulation systems by other methods. Further, in this case, the interrupt for entering the emulation processing is also SMI.
Not limited to, NMI may be used.

Next, as shown in step E4, the SMM
The processing for reading the factor register (status) by the handler 26 is performed. Next, at step E5, it is judged whether or not the read factor is the power source interruption factor d.
That is, in this embodiment, the priority is set to the factors that must be processed after entering the emulation.
The power-off factor is given top priority. In this case, the priority of the factor may be set by a physical register or the like as in the present embodiment, or may be set by the processing order of software or the like. If such a power failure occurs, a fatal system error will occur unless it is processed with priority. Therefore, in the present embodiment, a means for masking the emulation processing is provided, the factor register is made to have a hierarchical structure, etc., so that the priority order among factors can be easily set.
Then, the power-off process is prioritized over the I / O emulation process to prevent a system error from occurring.

When the cause of power failure is detected in step E5, the process proceeds to step E6, and processing such as saving of data in the HDD or the like is performed. As a cause of such power interruption, for example, in a portable personal computer, power interruption due to exhaustion of a battery is considered. Further, even when the system is designed such that data is not lost after the power switch is turned off, such a power failure detection process is required. After processing such as data saving is performed, a power OFF command is issued to the power supply unit in step E7, and the system power is turned off. Then, step E8
Then, the reset detection factor c is read (the reset detection becomes the next highest priority factor after the power failure detection), and when the reset is detected, the process proceeds to step E9. The processing after step E9 is shown in FIG. First, in step F1, the factor registers of the next layer (factor registers 658 and 659 in FIG. 9) are read. When the factor is i (hard reset), the process proceeds to step F3, and when the factor is j, the process proceeds to step F9.

In the case of a hard reset, the entire system is initialized, so a process of saving the data in the HDD or the like is performed (step F3). After that, the data on the cache memory is flushed by the WBINVD command to save the data (step F4). In the warm boot of BASIC, the data on the main RAM must be saved even at the time of hard reset. However, in a system that uses a write-back cache (a memory that rewrites only the cache memory and does not rewrite the data in the main RAM when there is a write command from the CPU),
When a hard reset is applied, there is a problem that write back of the cache is disabled and warm boot becomes impossible. Furthermore, there is a case where a write-back cache memory is used in a device such as an HDD. In this embodiment,
In order to solve such a problem, the process shown in step F4 is performed. Then, after setting the RESET command in the reset register 14 in step F5, closing the Config register of the PCMC 11 and issuing the RMS, the RESET signal 8 is output to the CPU 1 (steps F6 to F8). On the other hand, the soft reset is performed by the write operation for the I / O port (FOH). In the first computer system,
The keyboard controller has a similar port but is a different port, and the reset register 14 of the PCMC11
Not using the function of. In this embodiment, since the PCMC function is used, the SMI emulation processing is also performed for soft reset. By the way, in the case of soft reset, since only the CPU 1 needs to be initialized,
No data saving process is required, and the INIT command is set in the reset register 14 in step F9. Then, when the Config register of the PCMC11 is closed and RMS is issued, the INIT signal 9 is sent to the CPU1.
Is output (steps F10 to F12).

Returning to the explanation of FIG. After reading the reset detection factor c, the speed switching factor d is read,
When speed switching is detected, the process proceeds to step E17. Then, the state of the speed switch is read out, and when it is set to the low speed, the process proceeds to step E18,
Process that allows Dembo of PCMC11 (CPU
The process of adding a weight to 1 and reducing the speed is performed. On the other hand, when the speed is set to high, step E19 is directly performed.
, And return by RSM instruction. Step E5,
At E8 and E10, the factor a for the I / O port write is read only when there is no change in the operating environment such as power-off as shown in step E11. Then, when the factor a is set, the factors e to h are read from the factor register of the next layer, that is, the factor registers 654 to 657 in FIG. Then, the emulation processing based on the set factor is performed (steps E13 to E).
16). Then, the process proceeds to step E17, where the state of the speed switch is read. This is step E2, E
Since CPU1 is in the high-speed operation state by 3,
This is a process necessary to return this to the state set by the speed switch.

In the present embodiment, the switching of the external switch is detected by the power interruption detecting means 75, the reset detecting means 73, the speed switching detecting means 74, and the display switching detecting means 76, and the emulation is performed based on the detection results. Processing is being performed. Conventionally, the controller 507 shown in FIG. 54 has an external input terminal for switching these external switches, and therefore, it is not necessary to perform emulation processing for switching these external switches. On the other hand, the PCMC 11 which is the first device control means does not have such an external input terminal. Therefore, in the emulation system in which the first device control means is mixed in the second computer system as in the present embodiment, it is necessary to perform emulation processing for switching these external switches. That is, when there is an external input which is supported by the second device control means but is not supported by the first device control means, a method of emulating these external inputs is necessary. In the present embodiment, in order to realize this emulation processing, first, detection means (where the detection means may be arranged anywhere) is provided in the sub-controller, and a factor is set based on the detection result, and the SMI is set. A handler or the like executes processing corresponding to this factor. That is, the emulation processing is performed so that the processing such as power-off can be executed by utilizing the function of the second device control means.

As the emulation processing for such external switch switching, for example, a switch for contrast adjustment and brightness adjustment of a display unit in a portable personal computer or the like can be considered. Further, the target of the emulation processing of the present embodiment is not limited to such switching of the external switch. That is, when the second device control means is mixed in the first computer system and the external input supported by the first computer system does not exist in the second device control means, this external input is used. With respect to, the emulation processing of this embodiment can be applied. For example, when the bridge circuit 39 is replaced and the device control means of the first architecture is adopted,
If there is an external input that is supported by the bridge circuit 39 but is not supported by the first device control means, the emulation processing of this embodiment can be applied to this external input. As such an external input, not only the input from the external switch described in the present embodiment but also various inputs such as an external input from a sub CPU, a control device, a temperature detection terminal, and the like can be considered.

Next, the operation of the emulation processing of I / O write will be described with reference to FIGS. 16 and 17A to 17C. The I / O address 300H is a port that issues a command to switch the first display mode (standard resolution) and the second display mode (high resolution) by hardware. The detection of the switching of the display mode is performed by the sub controller 25.
This is performed by the display switching detection means 76 inside. When an instruction to switch the display mode is output to the I / O address 300H in step S20 of FIG. 16, the RAM 21, as shown in the memory map of the display mode 1 or the display mode 2 shown in FIGS. The operation of mapping the VRAM 33 and the ROM 43 is started. In step S21, VRA
The M switching means 35 and the ROM switching means 45 directly receive the I / O command of the CPU 1 as in the conventional case, and VR respectively.
The mapping of AM33 and ROM43 is switched. Further, the sub controller 25 receives an instruction from the I / O receiving means 30, sets a factor indicating the display mode switching in the SMI status 28 by hardware, and generates an SMI. In step S26, the process proceeds to SMM, and step S
In S27, the SMM handler 26 reads the SMI status 28 and starts the operation of switching the display mode.

17A to 17C, the memory maps of the display mode 1 and the display mode 2 and the corresponding memory setting register 17 of the memory controller 11 (PCMC) (con for making various settings to PCMC).
(which is a part of the fig register). Second
In the architecture of, the display modes 1 and 2 cause a large change from 0H to 100000H of the memory address as shown in FIGS. 17B and 17C. FIG. 17
(A) shows a register corresponding to the memory setting part of the memory setting register 17, and the left side is display mode 1
The setting corresponding to the display mode 2 is shown on the right side. In FIGS. 17B and 17C, the RAM is a G-VRAM (graphic VRAM) in addition to the RAM 21 of FIG.
And T-VRAM (text VRAM) are equivalent to VRAM 33, and ROM is equivalent to ROM 43.
There is a RAM from 0H to A0000H in display mode 1,
A flag that enables C (cache), W (write), and R (read) is set in the memory setting register corresponding to the RAM (the RAM controller 15 determines that the memory address in which W and R are set = RAM). It also has a function of automatically decoding and allocating the RAM 21). A0
000-C0000H and E0000-E8000H are V
RAM is allocated for four planes, and by specifying access to the PCI bus 23 by the memory setting register 17, the VRAM 33 that has been switched to the display mode 1 mapping in advance is addressed. C000
RO from 0 to E0000H, E8000 to 100000H
Access to the PCI bus 23 is also designated in M by the memory setting register 17, and the ROM 43 is addressed. Also in the display mode 2, the memory setting register 17 is set corresponding to the addresses of the RAM, VRAM, and ROM.
The mode 2 G-VRAM has a bank switching system for 4 planes in order to secure a capacity for high resolution. However, by providing a bank switching control means together with a decoder, it is possible to access without trouble. Returning to the description of FIG. In step S28, CPU1 is co
The nfig register is opened, and the display mode 1 or the display mode 2 is set in step S29 (state A in the figure). The config register is closed in step S30, the RSM instruction is issued in step S37, and the SMM is exited. By the above, (1) VRAM switching means 35 changes VRAM 33 mapping (2) ROM switching means 45 changes ROM 43 mapping (3) Memory controller 11 changes RAM 21 mapping and changes memory address settings The result corresponding to the second architecture is obtained for the I / O instruction.

5. Description of Bus Arbiter Next, the bus arbiter 70 will be described. The bus arbiter 70 performs a process (arbitration) for determining an access right to the PCI bus 23. This decision process is
Memory controller 11 and bus master on PCI (H
DD37) and request signals from the bridge circuit 39: REQ-CPU, REQ-PCI, REQ-BR
G is received, GNT-CPU which is a permission signal,
It is performed by outputting GNT-PCI and GNT-BRG to these. At the time of SMI processing, P of CPU1
It is desirable to increase the priority of the bus access right to the CI bus 23. If this is not done, for example, when the PCI bus 23 is accessed by the HDD 37 or the like during SMI processing, the bus access right is transferred from the CPU 1 to the HDD 37.
This is because the speed of the emulation processing is reduced due to the shift to the like. The following two methods are conceivable as methods for increasing the priority of bus access rights.

The first method is, as shown in FIG. 18, REQ-BRG and REQ- input to the bus arbiter 70.
This is a method of masking PCI with an SMI signal using the logic circuits 760 and 762. As a result, REQ-BR
G and REQ-PCI are not accepted by the bus arbiter 70, and the REQ-CPU from the CPU 1 has priority. In this case, the SMI signal 31 may be directly input to the logic circuits 760 and 762, or the SMM handler 26 sets a predetermined value in a predetermined register at the time of the SMI processing and outputs the output of this register to the logic circuit 760. , 76
You may enter in 2. In this way, the timing of changing the priority of arbitration can be controlled by software.

The bus arbiter 70 according to the second method includes logic circuits 772 to 790 and a DFF 79 as shown in FIG.
2-796, the state transition diagram of this circuit is shown in FIG. As shown in this state transition diagram, this circuit has four states, IDLE, S1, S2, and S3. ID
The LE state is a state immediately after reset by PCIRST and includes REQ-BRG, REQ-PCI, and REQ-CP.
U, GNT-BRG, GNT-PCI, GNT-CPU
Are all "1". And S1, S2, S3
Are REQ-BRG = 0, REQ-PCI = 0,
When REQ-CPU = 0, GNT-BRG = 0, G
It represents a state in which NT-PCI = 0 and GNT-CPU = 0 are returned. In the present embodiment, the SMI signal (S
The MM handler 26 may set a predetermined value in the register to perform the processing), and the priority is changed as follows. That is, when SMI = 1 (deassert),
Priority is REQ-BRG, REQ-PCI, REQ-
Priority is given to REQ-BRG in the order of CPU. On the other hand, when SMI = 0 (assert),
The priority is REQ-CPU, REQ-BRG, REQ-
The order is PCI, and the REQ-CPU has the highest priority. For example, as shown in # 8 of FIG. 20, SMI =
When 0, REQ-CPU has the highest priority, so REQ
-If CPU = 0, the state immediately transits to S3. When REQ-CPU = 0, GNT-CPU = 0
Then (# 12), the bus access of the CPU 1 is permitted. When REQ-CPU = 1 (# 9), I
Return to DLE state. On the other hand, when SMI = 1 (# 7)
Since the order of priority is BRG, PCI, and CPU as usual, the state shifts to the S3 state only when REQ-BRG = REQ-PCI = 1 and REQ-CPU = 0. After entering the S2 state, the following occurs. That is, SMI
When = 0 (# 6), the REQ-CPU has the highest priority, so even if REQ-PCI = 0, R is
S unless EQ-CPU and REQ-BRG are both 1
Do not move to 2. If you move to S2, GNT-P
Let CI = 0. On the other hand, in the case of SMI = 1 (# 5), the priority order is normal, so REQ-BRG = 1.
, And if REQ-PCI = 0, then REQ-CP
The S2 state is entered regardless of the value of U. The transition to the S1 state is exactly the same as above.

The bus arbiter 70 may be built in the bridge circuit 39.

6. SMM area change processing immediately after power-on or reset In SMI processing, immediately after power-on or reset, B
The SMI processing program is stored in the RAM by the IOS.
It is loaded into the MM area. In Pentium etc., in the initial state (immediately after power-on or reset), the address of the SMM area where the SMI processing program is loaded is SMB.
It is fixed at 38000H which is the default value of ASE. Since this area is on the main RAM,
S in the area where the application program is not loaded
The address location of the MM needs to be changed. However, this is not necessary if another memory device is prepared and a back RAM is provided in the area corresponding to 38000H and bank switching is performed. However, preparing another memory device in this manner causes a problem in terms of cost and the like. is there. Therefore, in this embodiment, for example, the address position of the SMM is changed to a 64 Kbyte area in the VRAM (AOOOOOH to BFFFFH) area. This address position is shown in FIG.
As shown in (A), the area is hidden behind the VRAM on the PCI bus 23, and therefore cannot be accessed by the application program. On the other hand, as shown in FIG. 21B, when transitioning to SMM, the PCMC 11 that receives SMIACT # changes VR
Change the area of AM to the area of RAM. Therefore, if this area (A0000 to B0000) is set so as to be the SMRAM address position, the SMRAM address position can be set in the area where the application program is not loaded, and the SMI processing loaded on the RAM is performed. It becomes possible to operate the SMI process normally by the use program. The change of the address position is performed in the following procedure.

(1) BIOS after power-on or reset
Loads the handler for SMBASE relocation to main RAM 38000H. At this time, BIOS is V
Switch the RAM bank, and use SM as the back RAM of VRAM.
Load the M handler.

(2) Next, a dummy SMI is generated.
This dummy SMI is generated by executing an appropriate I / O write instruction that causes SMI to occur. And in this dummy SMI, SMBASE in the CPU
Jump to 38000H according to the default value of. Then, the SMM handler loaded at 38000H in (1) above uses the SMBASE relocation function to rewrite the SMBASE setting at RSM so that the SMM is started from the VRAM.

(3) Subsequent SMI starts processing from the VRAM address set in SMBASE. Normally VRAM appears in the VRAM area, but SM
Bank switching is performed at the same time when I occurs, and SMRAM appears. This makes it possible to start the SMI processing.

In the above (2), the reason why the dummy SMI is generated is that the SMI process is started in order to change the address position where the SMRAM is set, and the SMBAS of the SMI is set.
This is because the relocation function of E must be used. That is, unlike the case of NMI, this address position change cannot be performed by the application program or the like. Also, after changing the address position, SMR
Since the AM is behind the VRAM, the data in the SMRAM will not be rewritten by the application program or the like.

The original SMI processing can be accepted only after the above-described steps are taken. On the contrary, if another SMI process is executed before such a procedure is taken,
The system may malfunction. Therefore, in this embodiment, the SMI masking function is provided, that is, the SMI masking means 29 is provided as described above to prevent such malfunction. That is, the generation of SMI is masked so that SMI does not occur (or a factor is not set) after the power is turned on or reset until the normal reception of the original SMI processing becomes possible.

FIG. 21C shows a memory map when the emulation processing is performed by NMI.
As shown in the figure, the NMI processing program is
It is stored in the BIOS area because it must be placed under the control of S and must be placed in an area where an application program is not loaded. This BIO
The size of the S area is small, and other programs are stored in the S area, so the free area is small. Therefore, N
If an attempt is made to perform emulation processing using MI, the size of the program used for it will be limited. On the other hand, when the SMI is used, the SMI processing program has an SMRAM with sufficient free space.
Since it is stored on the upper side, such a problem does not occur. Therefore, even a long program can be stored and a complicated emulation process can be performed. In the NMI, the interrupt vector for the NMI is the main R as shown in FIG.
If it is on the AM and is freely rewritten by an application program or the like, there is a problem that the NMI processing cannot be started. On the other hand, in SMI, the address position of SMRAM is 3800 after power is turned on.
It is fixed at 0H, and it is impossible to change this address position unless SMI processing is entered. Therefore, depending on the application program etc., SMRA
The address position of the M area is not changed, and
The SMRAM area can be set to an inaccessible area such as an application program as shown in FIGS. As a result, very safe emulation processing can be realized. Further, in the NMI, the return address is placed in the stack area on the main RAM, so that the return address may be rewritten by the application program or the like. On the contrary,
The SMI has an advantage that the return address and the contents of the internal register of the CPU are saved (stacked) in the SMRAM area and are not rewritten by the application program or the like.

7. Others When the PCMC 11 is mixed in the second computer system, the sub-controller 25 of this embodiment also performs the following control. For example, the PCMC 11 has a function called a write buffer. This is because, for example, when the instruction of the CPU 1 has an 8-bit width and the data in the VRAM 33 has a 32-bit width, this write buffer accumulates the instruction from the CPU 1 four times,
This is a function for outputting the accumulated data to the VRAM 33 at once. Although the PCMC 11 has such a function, the bus arbitration is performed by the bus arbiter 70 in this embodiment. When using this write buffer, it is necessary to prevent the access right of the bus from being transferred to another device before all the data stored in the write buffer is discharged. Therefore, in this embodiment, the sub controller 2
5, the data discharge of the write buffer in the PCMC 11 is controlled to solve the above problem. In this embodiment,
In addition to this, the functions of the PCMC 11 such as an upper limit register and a sideband signal are also supported, and compatibility is maintained when the PCMC 11 is mixed in the second computer system.

(Second Embodiment) In the first embodiment, the second
The PCMC 11 is used as an example of the first device control means to be mixed in the computer system of FIG. However, the first device control unit to be mixed is not limited to this. For example, in addition to this, for the bridge circuit 39, the first device control means, for example, SIO (82378IB manufactured by Intel) can be used. When the first device control means is used for the bridge circuit 39, the device control means such as the keyboard controller 48 and the serial controller 50 need to use the first architecture as well. Now, if the idea of the emulation system in which the first device control means is mixed in the second computer system is further developed, it is desired to realize hardware that is compatible with a plurality of devices. In order to realize multiple compatibility, it is necessary for the device control unit and the device to operate normally in response to instructions of multiple architectures issued from the CPU. Thus, for example, in the case of double compatibility among multiple compatibility, it is possible to operate both the application program conforming to the first architecture and the application program conforming to the second architecture on the same hardware. . Further, for example, MS- manufactured by Microsoft Corporation.
Regarding the OS such as DOS and MS-Windows, both of the first and second architectures can be operated on the same hardware.

FIGS. 56 (A) to 56 (C) show various modes of realization that are compatible with each other by the emulation system of the present invention. In FIGS. 56A to 56C, “first (second) architecture compatible” is abbreviated as “first (second)”. Therefore, the description “first application program” means “application program conforming to the first architecture”. In the following description, such a description method is used as appropriate. Also, FIG.
6 (A) to 6 (C) show examples of double compatibility among multiple compatibility, the present invention is not limited to this, and according to the present invention, application programs of three or more architectures, OSes can be operated on the same hardware. In this case, FIG.
The second architecture in (A) means a plurality of second architectures different from the first architecture. Further, the first architecture in FIG. 56B means a plurality of first architectures different from the second architecture. FIG. 56
The same applies to (C).

For example, FIG. 56A shows an example in which all (or most) device control means and devices conform to the first architecture. In this case, in order to realize a plurality of compatibility, in the case of the first mode, that is, when a command is issued by the first application program or OS, the command is directly transmitted to the first device control means or device. Reportedly. On the other hand, in the case of the second mode, that is, the second application program, the OS
When the command is issued by, the command is converted by the emulation process and transmitted to the first device control means and the device. In this case, if the latest device control means and the like were developed relatively early in relation to the market size and were abundantly available, a high-performance and inexpensive information processing device was installed. It becomes possible to develop at an early stage. Further, FIG. 56B is an example of a case where all (or most) device control means and devices conform to the second architecture. In this case, in order to realize multiple compatibility, the relationship is opposite to that in the case of FIG. 56A. In the first mode, the instruction is converted by emulation processing, and in the second mode, the instruction is converted. Should be transmitted to the second device control means and device as it is. In this case, the device control means and the like must use those of the second architecture, which may be inferior to the case of FIG. 56A in terms of performance, development period, cost, and the like. However, the second application program,
Since the instruction by the OS is transmitted to the device control means without being emulated, the performance may be improved when the second application program or the like is mainly operated. Therefore, for example, in the position of more respecting the software assets of the second architecture, as shown in FIG.
The configuration shown in FIG. 6 (B) is desired. FIG. 56C shows an example in which the first and second device control units and devices are mixed on the hardware. In this case, in the case of the first mode, the command is directly transmitted to the first device control unit and the device, and the command is transmitted to the second device control unit and the device via the emulation system. And in the case of the second mode, the opposite is true. Such a hardware configuration is a desirable form, for example, in a transitional period when the second control unit and the like are replaced with the first device control unit and the like.

As described above, there are various modes for realizing a plurality of compatibility, but in the following, the case of FIG. 56 (A) will be described as an example. Further, in the above-described first embodiment, the case where the control target of the device control means is a memory device has been mainly described, but the present invention is not limited to this, and naturally when the control target is an I / O device. Applicable to In the following, the control target of the device control means is I /
The description will be focused on the case of the O device. As described above, the SMI is originally provided as an interrupt for power supply control and has a problem in terms of operation speed. Therefore, in the present embodiment, in order to solve the problem of the operation speed, the following four types of conversion methods are selectively used according to the type of instruction.

1. First Conversion Method The first conversion method is a conversion method adopted when the type of instruction is an I / O write instruction and the instruction must be processed at high speed.

First, as shown in step A1 of FIG. 22, the I / O adapted to the second architecture is executed by the CPU.
When the O write command is issued, the bus access of the CPU is terminated and prohibited as shown in step A2. next,
As shown in step A3, the sub-controller, which is the main part of the present invention, occupies the bus as the bus master. In addition,
The configuration of the sub-controller in this case is different from that of the sub-controller in the first embodiment, but the details of the configuration will be described later.

Next, as shown in step A4, the sub controller executes the converted I / O write command. In this case, the conversion of the I / O write command is performed by, for example, a command conversion unit built in the sub controller. Specifically, the instruction converting means stores (latches) an I / O write instruction (I / O address, data, bus enable, etc.) issued by the CPU, and stores the stored I / O write instruction as a first instruction. Convert to fit the architecture of 1. And this converted I / O
A write command will be issued to the device control means, device of the first architecture.

The first and second architectures differ in the form of I / O instructions.
The emulation process may not be completed completely with the I / O instruction of the number of times. For example, in the second architecture, I / O assigned to one I / O (port) address
The O instruction may be assigned to two I / O addresses in the first architecture. In such a case, as shown in step A4, the I / O write command (or I / O read command) is executed one or more times. Finally, as shown in step A6, the bus is released and the I / O writing ends.

As described above, according to the first conversion method, the CP
I / I adapted from the second architecture issued by U
It becomes possible to convert the O write instruction so as to conform to the first architecture and issue it to the device control unit or device which is the object of the instruction. Since the emulation processing in this method is performed by the hardware circuit, it is most suitable for the processing that requires high speed.

2. Second conversion method The second conversion method is a conversion method adopted when the type of the instruction is an I / O write instruction and the processing is complicated, for example, an I / O read instruction is further required. is there. In such a case, according to the first conversion method, the circuit such as the sub-controller becomes large-scaled and complicated.
A second conversion method using SMI processing as shown in 3 is adopted. First, as shown in step B1, when the CPU issues an I / O write instruction conforming to the second architecture, as shown in step B2, this I / O write instruction is issued.
An O write command (I / O address, I / O data, bus enable, etc.) is stored (latched). Further, as shown in step B3, an SMI signal is generated by the sub-controller, and the SMI processing from step B5 is started. The generation of the SMI signal in this case is performed before the CPU shifts to the next I / O instruction cycle. next,
At step B6, the stored I / O write command is analyzed. Then, a predetermined process based on the analysis result, that is, a process of executing the converted I / O write command (step B8) or a process of executing an I / O read command (step B7) is performed. . Then, the SMI processing is ended by the RSM instruction in step B9.

As described above, according to the second conversion method, I /
SM in which processing according to O command operates with its own command system
It is executed by the M handler. Therefore, the conversion method is effective when the conversion of I / O instructions between the first and second architectures is complicated. 3. Third Conversion Method The third conversion method is a conversion method that is adopted when the type of the instruction is an I / O read instruction and the instruction must be processed at high speed. First, as shown in step C1 of FIG. 23, when the CPU issues an I / O read instruction conforming to the second architecture, the CPU's I / O read processing is interrupted as shown in step C2. This interruption is performed, for example, by performing a retry process when the bus is a PCI bus,
In the case of a local bus called a bus, Ba of the CPU
This is done by asserting the input signal of the ckoff terminal. Next, the sub-controller occupies the bus as shown in step C3. Then, as shown in step C4, the I / O read command converted so as to conform to the first architecture is executed, and the data read by this command is stored in a predetermined storage means. In this case, as shown in step C5, the I / O read (or write) command is executed once or plural times in some cases. The I / O read command executed in step C4 (or C5) is the I / O issued by the CPU.
The instruction (I / O address, bus enable) is stored (latched), and the stored I / O read instruction is converted to conform to the first architecture. Next, after the bus is released as shown in step C6, the CPU I / O read processing is re-executed as shown in step C7. Then, when the processing of the CPU is re-executed, as shown in step C8, the data stored in step C4 is output to the CPU (bus). As a result, the CPU can normally finish the read operation.

According to the third conversion method, the CP
The I / O read command issued by the U is converted and issued to the device control unit or device that is the target of the command, and the CPU normally reads the data read by the converted I / O command. Is possible. Since the emulation processing in this method is performed by the hardware circuit as in the first conversion method, it is most suitable for the processing requiring high speed.

4. Fourth Conversion Method The fourth conversion method is the conversion method adopted when the type of instruction is an I / O read instruction and the processing by this read instruction is very complicated. Step D of FIG. 25
1 to D3, when an I / O read command conforming to the second architecture is issued, this I / O read command (I / O address, bus enable, etc.) is stored and the sub-controller Generates an SMI signal. As a result, the SMI processing after step D5 is started.

Next, as shown in steps D6 to D8,
The stored instruction is analyzed, and predetermined processing based on the analysis result, that is, execution of the converted I / O read instruction,
Alternatively, in some cases, the I / O read instruction is executed a plurality of times. Then, as shown in step D9,
The data read by the I / O read command is SM
Save to the state save area in RAM (stack)
To be done. Then, when the RSM is issued as shown in step D10, the data stored in the state save area is restored to the internal register of the CPU, and the SMI processing is completed.

As described above, according to the fourth conversion method, I /
Since the processing corresponding to the O instruction is executed by the SMM handler, the conversion method is effective when the conversion processing is complicated. Further, in the fourth conversion method, the read data can be automatically restored in the internal register of the CPU by saving the read data in the state save area. To be simplified. That is, in the fourth conversion method, after the SMI is generated in step D3, the I / O read processing by the CPU is temporarily ended in step D4. This means that the CPU reads some data, for example, undefined data on the bus. Then, when the SMI process is started, the undefined data is saved in the state save area on the SMRAM as described above. After that, the data normally read by the predetermined processing shown in steps D5 to D8 is
It is saved in the state save area as shown in 9. As a result, the indefinite data saved in the state save area is rewritten, and normal read data is saved in the state save area. When the RSM is issued in step D10, the normal read data saved in the state save area is restored in the internal register of the CPU as described above. This allows the CPU to recognize that the process of steps D1 to D4 is a normal read process.

FIG. 26 is a block diagram for explaining the hardware of the second embodiment.

Sub-controller 100 of the second embodiment
Is an instruction conversion unit 104, a bus arbiter 970, an SMI.
Including generation means 927, SMI status 928, SMI mask means 929, I / O reception means 930, PCI bus interface 971, reset detection means 973, speed switching detection means 974, power failure detection means 975, and display switching detection means 976. However, the configuration is almost the same as that of the first embodiment except that the instruction converting means 104 is provided.

It should be noted that the I / O accepting means 930 accepts an instruction to determine which conversion method among the first to fourth conversion methods is to be adopted for the instruction issued by the CPU 1. , By judging the type of the accepted instruction. Further, in the instruction converting means 104,
Processing such as converting an I / O instruction from the CPU 1 into an instruction conforming to the first architecture is performed. Further, in the bus arbiter 970, a process (arbitration) of determining an access right to the PCI bus 23 is performed. On the PCI bus 23, AD0-31, C / BE0-3, FRA
Signals such as ME, TRDY, IRDY, STOP, and DEVSEL flow. Then, the I / O receiving means 930 having the timing circuit 902 built therein receives these signals (FRAM).
E, TRDY, STOP, DEVSEL signals, etc.) and a timing signal to the instruction conversion means.

Next, the meaning of the signals flowing on the PCI bus 23 will be described. A multiplexed address signal and data signal flow in the AD0-31 (32-bit) signal line, and in the address phase, the address signal
A data signal flows in the data phase. PCI bus 2
In 3, the transfer of the address signal is performed in the address phase, which is the first phase after the start of access. The data signal is transferred in the data phase following the address phase. C / BE0
The 3 (4 bit) signal means a bus command / byte enable signal, and the bus command signal flows in the address phase and the byte enable signal flows in the data phase on the line of this signal. Here, the bus command signal is a signal indicating the type of address signal flowing through AD0-31. That is, based on this bus command signal, whether the address signal is an I / O write command (hereinafter referred to as I / O write) or an I / O read command (hereinafter referred to as I / O write).
It is possible to judge whether it is a read), a memory read, or a memory write. On the other hand, the byte enable signal is a signal that determines which byte lane carries valid data among the data signals flowing to AD0-31. FRAME, TRDY, IRDY, STO
P and DEVSEL are bidirectional signals. The FRAME signal is a signal indicating the start of access and its period.
The TRDY signal is a signal indicating that the target is ready, and the IRDY signal is a signal indicating that the bus master (initiator) is ready. In the data transfer on the PCI bus 23, one becomes the bus master and the data is transferred to the other target. The STOP signal is a signal that the current target requests the bus master to stop the current processing. Further, the DEVSEL signal is a signal indicating that a device has been selected, and the device selected as the target is the DEVSE signal.
Assert the L signal.

FIG. 27 is a detailed block diagram of the sub controller 100. In FIG. 27, a BE latch register (R-Be) 128 latches a byte enable signal and a bus command signal input from C / BE0-3. In addition, the address latch 13
0, the address latch register (R-Adr) 132,
The address signals input from AD0 to 31 are latched. The latched address signal is converted by the address conversion unit 124 so as to be compatible with the first architecture, and is latched in the converted address latch 134. Similarly, the data latch register (R-Dat
a) 136 is for latching the data signals input from AD0-31. The latched data signal is converted by the data conversion unit 126 and latched by the conversion data latch 138. Two address latches 130 and one address latch register 132 are provided to latch the address signal for the following reason.
That is, on the PCI bus 23, the address signal becomes valid only within one clock period. Therefore, if the valid address signal is latched by the address latch 130 every time, even if it takes time to decode the address signal, the decoding operation can be performed with a margin.

The decoder 120 decodes the C / BE0 to 3 (bus command) signals and the address signal, and determines whether or not the input I / O instruction uses the SMI conversion method. That is, the I / O command issued from the CPU 1 is the same as the first and third conversion methods and the second and third conversion methods.
It is determined which of the fourth conversion methods is used.
Then, the decoder 120, based on this determination result,
A sequence start signal 160 for starting a series of sequences such as I / O command conversion processing is output to the I / O receiving means 930. For example, I / O to 30H
As the sequence start signal 160 for converting write and I / O read, signals such as ST30W and ST30R are output to the I / O receiving means 930. The FRAME signal is also input to the decoder 120 to form the timing of the sequence start signal 160 and the like. In the decoder 120, the address conversion unit 12
4. The control signal 162 for controlling the data conversion unit 126 is also generated. That is, in the address conversion unit 124 and the data conversion unit 126, the conversion method and the presence / absence of conversion are determined by the I / O instruction (address). Therefore, the decoder 120 decodes the C / BE0 to 3 signals and the address signal, and generates the control signal 162 of these conversion circuits. The decoder 120 also generates CSX0 to 2 signals by decoding the address signal and the C / BE0 to 3 signals. These CS
Signals X0 to 2 are BE latch register 128, address latch register 132, and data latch register 1 respectively.
The CSX0 signal, which is a chip select signal for 36, is sent to the three-state buffer 14 via the OR circuit 142.
0 and the CSX1 and CSX2 signals are input to the three-state buffers 144 and 148. And CSX
By asserting the 0 signal, the CPU 1 can read the status of the byte enable and the bus command when the SMI occurs from the BE latch register 128.
Similarly, by asserting the CSX1 and CSX2 signals, the CPU 1 can read the states of the address signal and the data signal when the SMI occurs from the address latch register 132 and the data latch register 136.

The output enable signal 164 is supplied to the three-state buffers 140 and 14 when the sub controller 100 becomes the bus master and drives the PCI bus 23.
This is a signal for enabling 6, 150, 152, 154. By asserting the output enable signal 164, the byte enable (bus command) signal latched in the BE latch register 128, the conversion address latch 134, and the conversion data latch 138, the converted address signal, and the data signal are transferred to the PCI bus 23. Is output to. Further, by asserting the output enable signal 164, the C / C generated by the I / O reception unit 930 is generated.
The BE0-3 signals, the FRAME signal, etc. are output to the PCI bus 23.

The I / O receiving means 930 uses the built-in timing circuit 902 to trigger the sequence start signal 160 from the decoder 120 to trigger TRDY, DE.
It generates signals such as VSEL, STOP, and FRAME.
Further, the I / O command from the CPU 1 is accepted, the cause is analyzed, the cause is set in the cause register in the SMI status 928, and the SMI generating means 927 causes the S
The MI signal is output to the CPU 1. As a result, the SMM handler (execution means) 26 is activated, and predetermined SMI processing is performed. However, if the I / O instruction does not require SMI processing (in the case of the above conversion methods 1 and 3),
No SMI signal is generated. Also, the I / O reception means 93
0 generates a signal 166 and outputs it to the address conversion unit 124, which also performs control when address conversion is required a plurality of times for one I / O instruction. Furthermore, I /
The O reception means 930 also generates a latch signal of each latch in the conversion means 104 by the built-in timing circuit 902. Note that the generation of each signal in the I / O reception unit 930 (timing circuit 902) is complicated,
For example, it can be realized by a logical operation means using microcode or the like.

REQ- which is an input of the bus arbiter 970
The PCI, REQ-BRG, and REQ-CPU signals are signals indicating that the HDD 37, the I / O bridge 39, and the memory controller 11 (CPU 1) want to use the PCI bus 23, respectively. Also, the output of the bus arbiter 970 is GNT-PCI, GNT-BRG, GNT-CP.
The U signal is a bus master on the PCI bus 23, and I /
O bridge 39, memory controller 11 (CPU1)
Is a signal indicating that access to the bus is permitted.

FIG. 28 shows an example of the circuit configuration of the bus arbiter 970. 28, the bus arbiter 970 includes DFFs 170 to 180 and an AND circuit 182.
-190, NOR circuit 192, inverter circuit 194-
197 are included. Then, REQ-PCI, which is a request signal from the agent on the PCI bus 23,
REQ-CPU and REQ-BRG signals are PCICLK
It is input to and held by the DFFs 170 to 174 driven by (the reference clock on the PCI bus 23). Also,
GNT-PCI, GNT-CPU, GNT- which are bus access permission signals to agents on the PCI bus 23.
The BRG signal is held by the DFFs 176 to 180. Then, the logic circuits 182 to 197 determine priorities among these signals. For example, in FIG.
In the example shown in FIG. 8, REQ-PCI has a high priority and RE is
The priority of Q-BRG is set low. The priority order in the bus arbiter 970 can be set arbitrarily.

According to the second embodiment having the above configuration, the above first to fourth conversion methods can be realized. How to perform the instruction conversion for each device control means and the instruction issued to the device will be described in detail in the third to fifth embodiments described below. (Third Embodiment) In the third embodiment, the I / O device is R
S232C interface 52 (hereinafter, simply RS23
2C) and the device control means is the serial controller 50. In this case,
Serial controller used in the first architecture, eg NS165 from National Semiconductor
50A needs to be emulated to operate with the second architecture I / O instructions. Now,
The second architecture uses, for example, the Intel 8251A as a serial controller. Figure 2
9 (A) and (B) have NS16550A and 8251A
Types of registers that are built in and I of these registers
/ O (port) address is indicated. FIG. 29 (A),
As shown in (B), the NS1650A and the 8251A have different I / O addresses and bit arrangements.
Particularly, in the 8251A, the command register (mode register) and the status register are arranged in one I / O address 32H, whereas in the NS16550A, they are arranged in a plurality of I / O addresses 3F9H to 3FEH. Therefore, the first architecture serial controller (N
The problem is how to adapt S16550A) to the second architecture.

1. Emulation of data transmission to RS232C The serial controller 50 converts parallel data input from the CPU 1 into serial data, and RS232C
Data is transmitted to an external device via the
It has two functions of converting serial data input from the 232C to parallel data and receiving the data to the CPU 1. Here, the emulation for the above data transmission will be described. The I / O address of the transmission buffer register is 30H for the 8251A as shown in FIGS.
550A is 3F8H (DLAB = 0), which is different. However, the meaning (function) of each bit of the transmission buffer register is the same, and since RS232C is standardized, it is only necessary to convert the write I / O address. Further, since the writing process of the transmission data needs to be performed at high speed, the first conversion method shown in FIG. 22 is adopted in the third embodiment.

FIGS. 30A and 30B show flowcharts of data transmission in the conventional hardware and this embodiment. In the conventional hardware, when the transmission data is written to the I / O address 30H by the second application software (step E1), the transmission data is written as it is in the transmission buffer register of the 8251A (step E2). This makes RS23
Serial data is output from 2C (step E3).
On the other hand, in this embodiment, when the transmission data is written to the I / O address 30H (step F1), the sub controller 100 changes the I / O address from 30H to 3H.
It is converted to F8H (step F2). Then, next, when the transmission data is written in the converted I / O address 3F8H (step F3), the transmission data becomes NS1.
The data is written in the transmission buffer register of 6550A (step F4), and the serial data is output to RS232C (step F5).

FIG. 31A shows a more detailed flowchart of the emulation processing for data transmission.
FIG. 3B shows a signal waveform diagram for each signal on the PCI bus 23 in this case. When the CPU 1 writes the transmission data to the I / O address 30H as shown in step G1, as shown in step G2, the transmission data,
The byte enable signal is the R-DATA1 shown in FIG.
36, and is latched by R-Be128. Also, the I converted from 30H to 3F8H by the address conversion unit 124
The / O address is latched in the conversion address latch 134. Next, as shown in step G3, the write processing of the CPU 1 is terminated, and access to the bus is prohibited. Specifically, as shown in FIG. 31 (B), the I / O receiving means 930 in the sub-controller 100 has the DEVSEL and T
RDY is generated, and the bus arbiter 970 is the GNT-CPU.
To generate. Then, by asserting DEVSEL, another agent on the PCI bus 23, that is, H
The CPU 1 is notified that the DD 37 and the bridge circuit 39 have been selected before. Also, by asserting TRDY, the access from the CPU 1 is terminated. Furthermore, by deasserting GNT-CPU, C
PU1 is prevented from proceeding to the next I / O access cycle, and bus access of CPU1 is prohibited. From the above,
As shown in step G4, the PCI bus 23 is occupied by the sub controller 100. Next, as shown in step G5, the transmission data latched in the R-Data 136 is written to the I / O address 3F8H. In this case, which byte lane in the transmission data is selected is determined by the byte enable signal latched by the R-Be 128. Further, the transmission data itself simply passes through the data conversion unit 126, and the conversion process for the transmission data is not performed. The assertion of DEVSEL and TRDY in FIG. 31B in this case is performed by the bridge circuit 39 to which the serial controller 50 is connected.

2. Command Write to Serial Controller Emulation As shown in FIGS. 29A and 29B, the command setting registers (mode register, command register) in the 8251A are arranged at one I / O address 32H. The command setting register in the NS16550 is divided into four I / O addresses 3F9H to 3FCH. 33 and 34, NS165 is shown.
A comparison of the functions assigned to the bits of the 50A and 8251A registers is shown, but as is clear from the figure, the functions of these bits are also significantly different. Further, the command in the 8251A is divided into a mode instruction (mode register) and a command instruction (command register) depending on the command mode in which the same I / O address is 8251A. As described above, the conversion process for the command write becomes very complicated. Therefore, in this embodiment, emulation is performed by the second conversion method shown in FIG. Since the hardware of the second architecture does not use the 8251A synchronous mode, emulation of the synchronous mode is not performed.

32A to 32C show the functions assigned to the bits of the mode register, command register and status register of the 8251A. CPU
The parallel data set to 8251A by 1 is
It is converted to serial data in the format specified by the mode command and output to RS232C. For example, in FIG.
2 (A), mode register bits 0, 1
Specifies the baud rate, and bits 2 and 3 specify the character length. Further, the control in the data transfer is shown in FIG.
Use the command register shown in. For example, bit 0 of the command register determines whether it is transmission or reception, and bit 1 sets whether or not the data terminal is ready. The status register is used to confirm the status of transmission and reception during data transfer. For example, it is possible to confirm whether or not the transmission buffer register and the reception buffer register have become empty by using bit 0 and bit 1.

Now, FIG. 35A shows a flow chart of the emulation processing in the case of command write, and FIG. 35B shows a signal waveform diagram in this case. Figure 3
As shown in FIG. 5 (A), when the I / O address 32H (command register, mode register) is written (step H1), the address, data, and byte enable are R-Adr132, R-Data136, R-. Be
It is latched by 128 (step H2), the SMI signal is generated (step H3), and after the writing is completed (step H).
4), the SMI processing is started (step H5). In this case, the SMI signal is TRD as shown in FIG.
It is asserted at the same time as Y is asserted or a few clocks earlier. This prevents the CPU 1 from ending the I / O access and entering the next instruction cycle.

36 and 37 show specific examples of SMI processing. After SMI processing starts (step I1),
First, the SMM handler 26 sends the SMI status 92.
8 is read (step I2). Then, according to the factor data set in the SMI status 928, I / O
It is determined whether or not the SMI is based on O emulation (step I3), and if different, another SMI process is executed (step I4).

Next, it is judged whether or not the address latched in the R-Adr 132 is 32H (step I5), and if different, emulation processing of another I / O instruction is executed (step I6). Next, the C / BE0 to 3 (bus command) latched by the R-Be 128 are read to determine whether or not the instruction is an I / O write (step I7), and if different, I / O read Emulation processing for 32H is performed (step I8). Next, it is determined whether or not Mode = 1, that is, whether or not the relevant I / O instruction is a mode instruction (step I
9), if Mode = 1, the process moves to the emulation process for the mode instruction (step I).
10, FIG. 38). In the 8251A, Mode = 1 is set immediately after reset, and Mode = 0 is set when the mode instruction processing is completed. If IR = 1 in the command instruction, Mod
e is set to 1. Flags for these Modes will be stored at a predetermined address in SMRAM. Next, in step H2 of FIG.
The data latched in a136, that is, the data of the I / O instruction issued by the CPU 1 (contents of the command instruction)
Is stored in the internal register of the CPU 1 (step I
11).

After the above processing is completed, the flow 800, 80
The processes shown in 2, 804, 806, and 808 are executed.
The process of each of these flows 800 to 808 is shown in FIG.
3, corresponding to the processes 900 to 908 in FIG. 34.

In the process of flow 800 (corresponding to 900 in FIG. 34), it is first determined whether or not bit 6 of AL is "1" (step I12). If "1", it is determined that IR = 1 has been set in the command command, and Mode = 1 is set (step I13). Next, the exclusive OR (XOR) of R-Data and OLD-CMD is taken, and the result is stored in AL (step I14). Here, OLD-CMD indicates the content of the previous command data. By taking the exclusive OR in this way, only the changed bit can be rewritten. In the process of flow 802 (corresponding to 902 in FIG. 34), it is first determined whether or not bit 3 of AL is "1" (step I15). Then, in the case of "1", it is determined that SBRK has occurred, and NS16550A
The contents of the 3FBH register are stored in AL (step I16). Next, bit 6 is rewritten to bit 3 of R-Data (step I17), and the content of AL is NS165.
The data is written back to the 3FBH of 50A (step I18), and then the process of step I19 is performed. This makes NS16
The register contents of 3FBH of 550A are rewritten. In the process of flow 804 (corresponding to 904 in FIG. 33), it is determined whether bit 0 or bit 2 of AL is "1" (step I21). When it is "1", bit 2 of R-Data,
The contents of 0 are stored in bits 0 and 1 of AL (step I22). After that, the contents of AL are output to 3F9H,
The process of step I24 is performed. This makes NS1655
The register contents of 3F9H of 0A are rewritten. Flow 8
The process of 06 (corresponding to 906 of FIG. 34) is a process when bit 1 or bit 5 is “1”, and the same process as the flow 804 is performed (steps I25 to I28). This rewrites the register contents of the 3FCH of NS16550A. In the process of flow 808 (corresponding to 908 in FIG. 34), it is determined whether bit 4 is "1" (step I29), and if it is "1", the content of 3FDH is read to AL (step I30). ). In the NS16550A, the error flag is reset by reading 3FDH, so the above processing is performed. Finally, RD
The contents of data are set in OLD-CMD (step 1
31), RSM is issued (step I32). Since the bit 7 of the command register has meaning only in the synchronous mode, the emulation processing is not performed here.

Next, the emulation process of the mode instruction will be described with reference to the flowchart of FIG. In the case of the mode instruction, it is necessary to perform the conversion processing indicated by 910 in FIG. Therefore, as shown in step J2, bit 2 of R-Data,
The contents of 3, 7, 4, 5 are AL bits 0, 1, 2, 3,
4 and then the contents of AL are output to the register of 3FBH of NS16550A (step J3). This enables the NS16550A to perform a desired mode instruction process. In step J4, bits 0 and 1 of R-Data are "0" and "
It is determined whether or not it is 1 ", that is, whether or not the baud rate factor is 16 times (see FIG. 32A). When it is determined that it is not 16 times, DLAB = 1.
After that (step J5), the baud rate and clock ratio to be set are calculated as shown in step J6.
The visor latch (writable when DLAB = 1) is reset (I / O write to 3F8H and 3F9H). This is because the NS16550A has a fixed baud rate of 16 times for transmission and reception with respect to the clock.
If 251A is set to 1x or 64x, Dev
This is because it is necessary to change the contents of the isor latch and control the clock of the NS16550A. And De
After changing the visor latch, the processes of steps J7 and J8 are performed, and the mode is returned to "1" (step J
9), return by RSM (step J10).

By the above processing, command write emulation can be performed.

3. Emulation of data reception from RS232C The I / O address of the reception buffer register is 8251A.
Is 30H and NS16550A is 3F8H (DLAB
= 0). However, since each bit of the reception buffer register has the same meaning, it is only necessary to convert the I / O address (see 917 in FIG. 33). In addition, since the read processing of the received data needs to be performed at high speed,
The third conversion method shown in 4 is adopted.

FIGS. 39 (A) and 39 (B) show flowcharts of conventional hardware and data reception in this embodiment. The difference between FIG. 39 (A) and FIG. 39 (B) is that when the second application software reads I / O from 30H, the sub controller 100 converts the address from 30H to 3F8H, and the conversion is performed. The received data is read from the address 3F8H by I / O.

FIG. 40 shows a more detailed flow chart of the emulation processing of data reception, and FIG. 41 shows the signal waveform diagram of each signal in this case. CPU1 is I
When the received data is read from the / O address 30H (step M1), the byte enable signal and the address signal converted from 30H to 3F8H are respectively R-Be.
128 is latched by the translated address latch 134 (step M2). Then, as shown in step M3, the CPU
The read process 1 is temporarily suspended. Specifically, FIG.
As shown in FIG.
The read process is interrupted by asserting VSEL and TRDY and performing the retry process. This retry process can also be performed by asserting STOP with DEVSEL asserted. In addition, PCI
In the case of the VL bus instead of the bus, Backoff is asserted to apparently end the I / O read, and the CPU 1 performs the same I / O read again to realize this interruption processing. Next, the GNT-CPU is deasserted and the sub controller 100 occupies the bus (step M
4), the received data is read from the register of 3F8H of NS16550A and latched in R-Data 136 (step M5). In this case, the byte enable is R-
From Be128, the address is the conversion address latch 134.
Will be output. Next, GNT-CPU is asserted to release the bus (step M6), and the CPU1 re-executes I / O read (step M7). Then R-Data
The data latched by 136 is output onto the PCI bus 23 (step M8), and the I / O read ends normally (step M9).

4. Emulation of status read from serial controller 8 as shown in FIGS. 29 (A), (B), 33, and 34.
The one corresponding to each bit of the status register of 251A has two addresses 3FDH and 3 in the NS16550A.
It is divided into FEH and the bit arrangement is also different. But,
It is desirable that the read process from the status register be fast. This is the serial controller 50
This is because data is transmitted and received while observing the change of the stator at any time, so if the status read is slow, a problem such as missing of data will occur. Therefore, although the circuit becomes a little complicated, the third conversion method shown in FIG. 24 is adopted.

FIG. 42 shows a flowchart of status read emulation processing. First, the processes of steps N1 to N4 are performed as in the case of data reception shown in FIG. Next, status data is read from the line status register in 3FDH of NS16550A, data exchange processing is performed, and latched in R-Data 136 (step N5). The data exchange processing in this case is performed by the data conversion unit 126. Specifically, FIG.
Data exchange processing as shown in 912 and 914 is performed.
Next, data exchange processing is performed on the status data read from the modem status register in 3FEH, and OR processing is performed with the data latched in the R-Data 136 in step N5 to make one data, and the result is again obtained. Latch in R-Data 136 (step N
6). In this case, the data exchange processing as shown at 916 of 21 is performed. Then, the processes of steps N7 to N10 are performed as in the case of FIG. 40, and the status read is ended.

According to the above processes (1) to (4), in the third embodiment, the device control means (NS16550A) used in the first architecture and the second device are used.
It becomes possible to adapt to the system of the architecture.

(Fourth Embodiment) The fourth embodiment is an I / O
This is an embodiment to which the present invention is applied when the device is the keyboard (KB) 49 and the device control means is the keyboard controller 48. The first architecture uses Intel 8042 as a keyboard controller. In the second architecture, RS23
As in the case of 2C, for example, 8251A manufactured by Intel is used. 43 and 44, 8042 and 8251 are shown.
A comparison of the I / O address of A and the function of each bit is shown. As shown in the figure, the 8042 and 8251A have different I / O addresses and bit arrangements, and also different keyboard input data sent from the keyboard. Therefore, it is necessary to convert these addresses and data by emulation processing.

1. Emulation of sending commands to the keyboard.

In the emulation of the command transmission to the keyboard 49, both the address and the data must be converted, and the parameters must be distinguished, so the processing is relatively complicated. Furthermore, since the frequency of command transmission is low,
The second conversion method shown in 3 is adopted.

FIGS. 45 (A) and 45 (B) show flowcharts of command data transmission to the keyboard 49 in the conventional hardware and this embodiment. here,
LED ON as a command to be sent to the keyboard 49
The / OFF command will be described as an example, but other commands such as the setting of the repeat interval can be emulated by the same method. LED on the keyboard is O
In order to turn it off / on, the second architecture is shown in FIG.
The following processing is performed as shown in steps N1 to N12 of 5 (A). That is, first, after confirming whether the data transmission is possible, the second application software executes 9D
H (code serving as a key when transferring a command to the keyboard) is I / O-written to the I / O address 41H. When this I / O write is acknowledged, it is confirmed whether or not data transmission is possible, and then the second application software writes I / O address 41H with a parameter for instruction execution. . When this I / O light is acknowledged, the LED
Will be turned ON / OFF. In the fourth embodiment, the above process is emulated as shown in FIG.

In FIG. 45B, first, 43H is I / O read by the second application software (step P1), and whether bit 0 or bit 2 is "1", that is, whether transmission is possible or not. Is determined (step P2). In this case, in the fourth embodiment, the sub controller 100
Address and data are converted by (step P
2) Thereby, the status is read from 64H of 8042 (step P3). This allows TXRDY
(Transmission ready), TXE (transmission buffer register is empty)
It becomes possible to judge whether or not is "1" (step P4, see FIG. 32 (C)). Then, it is determined that transmission is possible, and the second
When 9DH is written to 41H by the application software (step P5), unlike the conventional case of FIG. 45 (A), the address and data conversion processing by SMI processing is started (step P6, see FIG. 46). ). As shown in FIG. 46, in this SMI processing, the command is first discriminated, and the address and data conversion processing is performed according to the discrimination result (step Q3). And 9
The contents of EDH obtained by converting DH so as to conform to the first architecture are I / O written to 60H (step Q4). After that, step P in FIG.
As shown in FIG. 7, when data is input from the keyboard unit controller 55 built in the keyboard 49 to the keyboard controller 48, AC is input in step P8.
It is determined whether or not the code of K (acknowledge, 0F8H) has been transferred. Then, if it is not transferred, it is determined to be an error (step P9). As described above, the command transfer process to the keyboard 49 is performed. next,
Similar to steps P1 to P4, it is determined whether data can be transmitted (steps P10 to P13). When it is determined that the command is possible, the parameter transfer process for executing the command is performed as shown in steps P14 to P17. The transfer process of this parameter is performed in step P5.
~ It is performed in the same manner as P8. However, in this case, the parameters are discriminated during the SMI processing, and the address and data conversion processing is performed based on the discrimination result.

By performing the above processing, the LED on the keyboard can be turned on and off.

2. Emulation of Command Write to Keyboard Controller Emulation of command write to keyboard controller 48 is very complicated because the 8042 must perform multiple write operations in response to one write operation to the 8251A (Fig. 43, 92 in FIG.
0, 924). Furthermore, since the command write is executed less frequently, the second conversion method shown in FIG. 23 is adopted. Further, in this embodiment, the emulation processing is not performed for the command bit of 8251A and the mode instruction of 8251A which do not exist in 8042 (see 926 and 928 in FIGS. 43 and 44). 47A and 47B show flowcharts of conventional hardware and command writing in this embodiment. Conventionally (steps R1 and R2), when the I / O write to 43H is performed by the second application software, the command is directly written to the 8251A. On the other hand, this embodiment (steps S1 to S3)
Then, when the I / O write to 43H is performed, the address and the data are exchanged by the SMI process, and the command is written to the 8042.

3. Emulation of reception of data input from the keyboard Data input from the keyboard 49 is very complicated because I / O addresses are different and all input data must be converted. Therefore, the fourth conversion method shown in FIG. 25 is adopted.

48 (A) and 48 (B) show flowcharts of conventional hardware and data input reception in this embodiment. By the processing of steps U1 to U4,
It is determined whether or not bit 1 of the status register is "1", that is, whether or not the data reception is ready (see FIG. 32 (C)). In this case, unlike the conventional case of FIG. 48A, the address and data are converted by the process of step U2. When data reception is ready and 41H is I / O read by the second application software (step U
5), the SMI process is started and the address and data are converted (step U6, see FIG. 49). This gives 80
It is possible to receive keyboard input data from 42 (step U7).

FIG. 49 shows the details of the SMI processing in this case. The conversion processing indicated by 930 in FIG. 44 is executed by this SMI processing. S by steps V1 to V4
When MI processing starts (step V5), R-Adr1
It is determined whether or not the I / O address latched by 32 is 41H (step V6), and if it is not 41H, another I / O emulation process is executed (step V6).
7). Next, it is judged whether or not it is an I / O read by the bus command latched by the R-Be 128 (step V
8) If not I / O read, emulation processing of keyboard command write is executed (step V9). Next, I / O read is performed from the I / O address 60H (step V10), and the read data is converted according to a predetermined conversion table stored in the SMRAM (step V11). Next, the data converted in step V11 is saved in the state save area in which the internal register AL of the CPU 1 is stored (step V12). After that, the RSM is issued and the contents of the internal register of the CPU 1 saved in the SMRAM are returned (step V13).

As described above, in the fourth embodiment, the emulation process for receiving the data input from the keyboard is performed. Then, in this case, the data converted by the SMI process is automatically returned to the internal register of the CPU 1 by the RSM instruction, so that the process is greatly simplified.

4. Emulation of status read from keyboard controller The emulation process of status read is performed in 93 of FIG.
As shown in FIG. 2, the I / O address may be converted from 43H to 64H, and data bit conversion may be performed. Also, FIG.
As shown in 934 of No. 4, emulation processing is not performed because the bits 4 and 3 (FE, OE) of 43H of 8251A are functions that are not included in 8042. Moreover, since the status read needs to be performed at high speed, the third conversion method shown in FIG. 24 is adopted.

FIGS. 50 (A) and 50 (B) show flowcharts of conventional hardware and status read in this embodiment. As shown in FIG. 50B, unlike the conventional case, in the present embodiment, when 43H is read by the second application software (step X1),
The sub controller 100 converts the address and the data (step X2), and the bit-converted data is read from the converted address 64H by I / O (step X).
3). As a result, the status can be read from the 8042 (step X4).

By the processing of (1) to (4) above, in the fourth embodiment, the device control means (8042) used in the first architecture can be adapted to the system of the second architecture. It will be possible.

(Fifth Embodiment) The fifth embodiment is an embodiment relating to interrupt vector conversion. It is desirable to convert the interrupt vector to maintain compatibility. As shown in FIG. 51, the first architecture and the second architecture differ in the allocation of interrupts from each I / O device (timer, keyboard, etc.) to each interrupt vector. Therefore,
Regarding the interrupt controller 54, it is necessary to convert not only the I / O address thereof but also the arrangement of the interrupt lines. The conversion of the interrupt line can be easily realized by the following method. For example, as shown in FIG. 52B, a selector 252 is provided before the interrupt control unit 250. Then, the mode switching signal 254
Thus, the interrupt line is switched between the first (architecture) mode and the second (architecture) mode. As a result, IRQ0 to IRQ15 to IRQ'0
It becomes possible to switch the interrupt line to IRQ'15.
However, when both the interrupt factor generator and the interrupt controller are built in one IC, the above method cannot be used. This is because if the interrupt factor generation unit and the interrupt control unit are built in one IC, the interrupt line does not come out to the outside, and it becomes impossible to exchange the interrupt line. However, in the hardware configuration of the first architecture, the interrupt factor generator and the interrupt controller are built in one IC. Therefore, in the fifth embodiment, when the CPU 1 fetches the interrupt vector in the interrupt acknowledge cycle, a process of converting the interrupt vector on the PCI bus 23 (or VL bus or the like) is performed. Where PCI
The occurrence of an interrupt acknowledge cycle at
It is realized by driving BE0 to BE3 and the FRAME signal.

FIG. 52A shows a flow chart of this emulation processing, and FIG. 53 shows a signal waveform diagram of each signal. This emulation processing is a conversion method similar to the third conversion method shown in FIG. When the CPU 1 generates an interrupt acknowledge cycle (step Y
1), the acknowledge cycle is interrupted by the sub-controller 100 (step Y2). As shown in FIG. 53, this is because the sub controller 100 uses STOP, DE
It is realized by asserting VSEL and TRDY and performing a retry process. Next, the GNT-CPU is deasserted and the sub controller 100 occupies the bus (step Y3). Then, this time, the sub controller 100 generates an interrupt acknowledge, reads the interrupt vector from the interrupt controller, and converts this into a predetermined interrupt vector (step Y4). Next, the bus is released (step Y5) and the CPU 1 again generates an interrupt acknowledge cycle (step Y).
6). Then, at this time, the sub-controller 100 outputs the converted interrupt vector onto the PCI bus 23 (step Y7), whereby the interrupt acknowledge cycle ends normally (step Y8).

With the above processing, the interrupt vector can be converted without using the technique shown in FIG. 52 (B). In this case, for example, there are some that do not exist in the second architecture, such as the FDD controller of FIG.
In this case, for example, a dedicated hardware for interrupt control can be provided in the sub controller 100.

(Sixth Embodiment) 1. Description of Overall Configuration The sixth embodiment is a personal computer system (for example, a PC manufactured by IBM Corp.) adapted to the first architecture.
/ AT, PC / XT) with a built-in sub-controller
This is an embodiment for realizing multiple compatibility by slightly changing the hardware. FIG. 57 shows the overall structure of the sixth embodiment. CP directly connected to the CPU bus 302
A PCMC 304 or the like is connected to the U bus. Also, P
Sub-controller 300, SIO31 on the CI bus
0, a PCI expansion slot 311, an expansion video controller (also having a VGA function) 314, a video controller 316 for 98, and a PCI / IDE 318 as an interface of the HDD 320 are connected. Also, ISA
A buffer 322 and a PCI / ISA expansion slot 324 are connected to the bus, and a BIOSROM 32 is connected to the X bus.
8, RTC330, keyboard / mouse controller 3
32 etc. are connected. In the sixth embodiment, a sub-controller 300, an option board 312, an expansion slot box 326, a video controller 316, etc. are added to a personal computer system (hereinafter referred to as an AT machine or simply AT) conforming to the first architecture. By doing so, multiple compatibility is realized. Sub controller 300
Is an SMI generating unit 340, an SMI status 342,
SMI masking means 344, I / O receiving means 346,
It includes an instruction converting unit 350 and performs emulation processing such as converting an instruction from the CPU 302. FIG. 58 shows an example of the configuration of the instruction converting means 350. The instruction converting means 350 includes a microcode memory 370 and implements emulation processing based on the microcode information read from the microcode memory 370.

The sub-controller 300 outputs the FRAMES signal which is a signal obtained by masking the FRAME signal to the SIO 310 including the bridge circuit. As a result, when the CPU 302 issues an instruction of the second architecture, the instruction is transmitted to the device control unit (PCI / ISA slot 324, keyboard / mouse controller 332, etc.) connected to the ISA bus and the X bus. It is disabled. That is, P to which the CPU 302 is connected
CMC304 is the start signal of PCI bus access, F
When the RAME signal is asserted, the sub controller 300 masks the FRAME signal (see FIGS. 60 and 61).
), The masked FRAMS signal is SIO
It is transmitted to 310. Then SIO310 has FRAM
The E signal is not transmitted, so the SIO 310 is
Cannot respond to the command. This guarantees that the device control means on the ISA bus and the X bus does not respond to the instruction of the second architecture, and multiple compatibility can be realized.
On the other hand, the video controller 316 is a personal computer of the second architecture (for example, PC386, PC486 manufactured by Seiko Epson, PC9 manufactured by NEC).
801, PC9821, etc., and the following 98 machines or simply 9
8)). Since the video controller 316 is required to perform complicated and high-speed processing, in the sixth embodiment, the instruction conversion processing and the like are not performed, and the extended video controller 314 for AT and the video controller 316 for 98 are provided. It is configured to include. Therefore, it is necessary to prevent the video controller 316 from responding to the instruction of the first architecture and, conversely, to respond to the instruction of the second architecture. Therefore, in this embodiment, the sub controller 3
00 to F to the video controller 316 for 98
The RAMEV signal is output. That is, when the instruction of the first architecture converted by the emulation processing is issued, the sub controller 300 causes the FRAME
The signal is masked (see FIGS. 60 and 61) and the masked FRAMEV signal is transmitted to the video controller 316. On the other hand, when the CPU 302 issues the second architecture instruction, the mask processing is not performed F
The RAMEV signal is transmitted to the video controller 316. This ensures that a normal command is transmitted to the video controller 316, and multiple compatibility can be realized. In the present embodiment, the command transmission is invalidated by masking the FRAME signal, but the present invention is not limited to this and may be realized by controlling other bus control signals.

The PCI expansion slot 311 is an expansion slot connected to the PCI bus, and the option board 312 including the conversion unit 313 can be inserted into this expansion slot. The conversion unit 313 converts a PCI bus signal into a 98 bus signal, and the converted bus signal is transmitted via the cable 325 to the 98 expansion slot box 32.
6. That is, as shown in FIG. 59, the option board 312 is inserted into the PCI expansion slot 311 provided in the main device 309, and the bus signal converted for 98 is expanded via the cable 325 to the expansion slot box 32.
Tell 6. The expansion slot box 326 is provided with a plurality of 98 expansion slots 327. Therefore,
If you want to use the option board 329 for 98, insert the option board 329 into this expansion slot 327.
You can insert it in. As a result, the option boards such as the SCSI board, the memory board, and the LAN board which have been developed by many manufacturers can be effectively used, and the past assets can be utilized. On the other hand, an AT machine is equipped with a PCI expansion slot as standard. Therefore, FIG.
With the configuration as shown in FIG. 9, the AT body can be used as the casing of the main body device 309 (exterior member of the device), and the cost can be reduced.

When the instruction of the first architecture is issued, it is necessary to prevent the device control means and device on the 98 option board 329 from responding to this instruction. Therefore, it is desirable to fix the memory space and I / O space that can be used by these device control means and the like by using a configuration register or the like. Also, here, the option board 312 is a PC
Although it is inserted into the I expansion slot 311, the configuration of the conversion unit 313 may be changed so that the option board 312 is inserted into the expansion slot on the ISA bus or the X bus.

2. Description of Operation FIGS. 60, 61, and 62 are signal waveform diagrams and flowcharts for explaining the operation of the sixth embodiment in the write cycle and the read cycle. Next, the operation of this embodiment will be described with reference to these figures. Note that FIG.
In FIG. 61, the portion indicated by the bold line is the sub controller 300.
Represents the part (period) driven by.

In the following, a case where the system of this embodiment is set to the 98 mode (the mode for operating the application program and OS of the second architecture) will be described as an example. Therefore, in this case, the CPU 30
From 2, the instruction of the second architecture is issued. The sub-controller 300 converts this instruction into an instruction of the first architecture and sends it to the first device control means. First, in step S1 of FIG. 62, it is determined whether or not FRAME = L. , B3) which requests I / O read, I / O write, and interrupt acknowledge. When these cycles are requested, the FRAMES signal is masked (C
1, C3 and step S3). This allows ISA
Instructions are prevented from being transmitted to the device control means on the bus or the X bus.

At this time, FRAMEV is not masked (see D1 and D3). Thus, if the second architecture instruction was for the video controller 316, the instruction is conveyed to the video controller 316 for 98. Further, in the AT mode (mode for operating the application program of the first architecture, OS), conversely, FRAMES is not masked and FRAMEV is masked.

Next, another target on the PCI bus is D
EVSEL = L (bus control signal is asserted at L level)
(Step S4), and if another target does not assert by the timing of the slow (the PCI has the timing of the fast, medium, and slow), the sub-controller 300 causes the DEVSEL to
= L, REQ = L (E1, E3 and step S
5). Then, in the case of I / O write, TRDY = L is set and the cycle is normally terminated (F1 and steps S6, S
7), DEVSEL = H and TRDY = H are set (step S8). Then, when GNT = L, the emulation cycle starts (G1 and step S10), and when the emulation ends, REQ = H (H1 and step S11). In the emulation cycle, the FRMAES signal is not masked and the FRAME
The V signal is masked. As a result, the instruction of the first architecture converted by the emulation processing is transmitted to the first device control means on the ISA bus and the X bus. On the other hand, this command is not transmitted to the video controller 316 for 98. If it is an I / O read and not a retry cycle (steps S6, S1)
2), STOP = L (F3 and step S1
6) After that, it becomes the same as the case of I / O write (G
3, H3, etc. and steps S17-S20). On the other hand, in the case of the retry cycle, the target sub-controller 300 masks the FRAMES signal and TRDY =
Respond to the read command of the CPU 302 as L (K
3, L3 and steps S13 to S15). This allows
The data obtained by the emulation processing is stored in the CPU 302.
It becomes possible to tell.

FIG. 63 shows steps S10 and S1 of FIG.
It is a flowchart figure of the emulation cycle of 9. First, in step T1, it is determined whether an emulation request has been issued. This is the ignore bit (bit 28) / continuation bit (bit 3) in the command information (see FIG. 65B) output from the microcode memory.
Judge by 0). That is, when the ignore bit = 1 (indicating that the emulation process is not performed) and the continuation bit = 0 (indicating that the emulation process is not continued), step T2.
Do not move to later. Next, the sub-controller 300
Set RAME = L and set the emulation address to PCI
Output on the bus (M1 to M4, N1 in FIGS. 60 and 61)
~ N4 and step T3). Then, in the case of I / O write, FRAMAE = H is set, and the data to be written is set to PCI.
Output to the bus and set IRDY = L (O1 and step T4). And the target on the PCI bus is DEV
When SEL = L and TRDY = L, the sub controller 3
The write command by 00 ends normally (P1 and steps T5 and T6). Then, IRDY = H, the data bus is set to a high impedance state, which enables the transition to the next emulation cycle (step T
7, T8). When TRDY = L and STOP = L, the target abort occurs and the same emulation cycle is repeated (steps T9 and T1).
0).

When it is judged to be I / O read in step T3, FRAME = H, the address bus is set to a high impedance state, and IRDY = L (O3, O4 and step T11). And the target is DEVSE
When L = L and TRDY = L (P3, P4 and steps T12, T13), the process ends normally, and the sub controller 300 latches the data (see Q3, Q4) output from the target (step T14). CPU30
2 reads this latched data during the retry cycle, and the data obtained by emulation by this is transmitted to the CPU 302 (see R3). Other processes are the same as those for I / O write (steps T15 to T17).

3. Description of Command Converting Unit Next, the configuration of the command converting unit 350 will be described with reference to FIG. The sequencer 352 is a circuit for timing control, and includes an address decoder 360 and a selector 36.
4 and the like, outputs a control signal, receives a status / command signal on the PCI bus, and outputs the output buffer 35.
Control these signals via 4. Address latch 3
56 and a data latch 358 are for latching address data included in an instruction from the CPU 302.
The address decoder 360 decodes and converts the latched address, and the address decoder 362 decodes the emulation address read from the microcode memory 370. The selector 364 selects one of the outputs of the address decoders 360 and 362 and outputs it as the memory address to the microcode memory 370. The microcode memory 370 is a ROM or R
It is composed of AM and stores microcode information at the input memory address position. This microcode information includes information on command data generation (bit data, bit definition) and emulation address.

The microcode information read from the microcode memory 370 is latched in the first code latch 372 in the 1st cycle and latched in the second code latch 374 in the 2nd cycle. The command information latched by the first code latch 372 is transmitted to the sequencer 352 via the decoder 376, and the operation of the entire circuit is determined based on this command information. Also,
The emulation address information latched by the first code latch 372 is output to the address decoder 362, whereby the memory address of the microcode memory 370 is generated. Further, the emulation address information is output on the PCI bus via the selector 386 and the output buffer 388, whereby the address in the emulation cycle is given.

First and second code latches 372, 374
The data generation information (bit data, bit definition) latched by is output to the write data generation unit 378 and the read data generation unit 382. Write data generation unit 378
Generates write data in an emulation cycle based on bit data information, bit definition information, write data from the CPU, and data obtained by emulation. In addition, the read data generation unit 382
Generates read data in the emulation cycle based on the bit data information, the bit definition information, and the data obtained by the emulation. In addition,
The TMP registers 380 and 384 are connected to the data latch 35.
8. It temporarily latches the input data from the input buffer 390.

Next, the operation of the instruction converting means 350 will be described with reference to the flowchart shown in FIG. First,
It is determined whether or not FRAME = L (A1, A3 in FIGS. 60 and 61) (step U1), and the instruction issued by the CPU (see B1, B3) is an I / O read / I / O write / interrupt. It is determined which cycle of acknowledge is required (step U2). If these cycles are requested, the microcode memory 3
70 output enable signal MOE = L, and a memory address is input to the microcode memory 370 (W1, W
3 and step U3), the 1st read cycle of the microcode memory 370 is started. The memory address MA in this case is the address information (B1, B
3) is decoded by the address decoder 360. 1st read cycle (X1, X3)
The microcode information obtained by is latched in the first code latch 372 (step U4). And
The command information included in the latched microcode information is input to the sequencer 352 via the decoder 376, and the sequencer 352 determines whether or not the 2nd read cycle (Y1, Y3) is necessary based on this command information ( Step U5). If it is determined to be necessary, the selector 364 performs the process of changing the memory address MA based on the instruction from the sequencer 352 (step U6). Specifically, this change processing is realized by changing the cycle bit (bit 14 in FIG. 65A) of the memory address used in the first read cycle from 0 to 1.
The microcode information obtained in the 2nd read cycle is latched in the second code latch 374 and then MOE.
= H, MA = HI-Z (step U8). Then, based on the microcode information latched by the first and second code latches 372 and 374, the address and data (N1, N3,
O1, R3) is generated.

In the emulation cycle, the emulation address information input from the first code latch 372 via the address decoder 362 is selected by the selector 364, and the microcode memory 37 is selected.
A memory address of 0 is generated. That is, in this embodiment, the emulation address (N3) becomes the memory address MA (X4) of the microcode memory 370 in the emulation cycle. Even when the second emulation cycle is started, the emulation address (N4) at that time is the memory address MA.
(X5). The instruction conversion means 350 repeats the above operation until the emulation cycle is no longer needed. In this case, whether or not to start the next emulation cycle is determined by the continuation bit (bit 30 in FIG. 65B) included in the microcode information as described later. As described above, according to this embodiment, the address of the memory in the second and subsequent emulation cycles is determined by the emulation address information included in the microcode information read last time. Whether or not to start the next emulation cycle is determined by the command information (continuation bit) included in the previously read microcode information. Therefore, only changing the emulation address information and command information (continuation bit) stored in the microcode memory 370,
Emulation cycles with different emulation addresses can be activated any number of times. This makes it possible to easily implement complicated emulation processing,
The compatibility in multiple compatibility can be improved.

4. Description of Microcode Information Next, the microcode information stored in the microcode memory 370 will be described with reference to FIGS. 65 (A) to (F). FIGS. 65A and 65C show the data format of the memory address input to the microcode memory 370. FIG. 65 (A) shows the 1st cycle,
FIG. 65 (C) is for the 2nd cycle, and both are
Only the value of the cycle bit (bit 14) differs. EA
3 to EA0 and A7 to A0 are obtained by data compression of the address information or the emulation address information included in the instruction from the CPU. The option bits OP0 and OP1 are EA3 to EA0 and A7 to
This is used to obtain different microcode information when A0 is the same. That is, EA3 to EA0, A7
Even if A0 is the same, different memory addresses can be output to the microcode memory 370 by making the option bits different, whereby different microcode information can be obtained. The cycle bit is a bit for distinguishing the 1st cycle and the 2nd cycle, and the R / W bit is a bit for distinguishing whether the activated cycle is a read cycle or a write cycle.

The microcode information output in the 1st cycle includes command / data generation (bit data) / emulation address information, as shown in FIG. 65 (B). Emulation address information A15 to A
0 and data generation information D7 to D0 are for obtaining addresses and data in the emulation cycle. The immediate bits are bits that instruct to use D7 to D0 as emulation data as they are. That is, when the immediate value bit = 1, the write data generator 378 selects the bit data D7 to D0 from the first code latch 372. As a result, the selector 38
6. D7 to D0 are output on the PCI bus as emulation data via the output buffer 388. AD
The bit is a bit instructing to convert only the address. When AD bit = 1, only the address conversion is performed in the emulation, and the data or the like from the CPU is directly selected as the emulation data. At this time, D7 to D0 are used as data for masking data or the like from the CPU. The TMPW bit is a bit instructing to store data in the TMP registers 380 and 384. The through bit is a bit for instructing to output the address and data without conversion. The ignore bit is a bit indicating that the emulation cycle itself is not activated. When the through bit = 1, the instruction from the CPU is transmitted as it is to the device control means on the X bus and the ISA bus. On the other hand, when the ignore bit = 1, FR
Since the AMES is masked, no command from the CPU is transmitted to these device control means. This makes it possible to transmit the command only to the video controller 316 for 98, for example. The INTA bit is a bit for instructing special conversion for the interrupt acknowledge cycle (see the fifth embodiment). The continuation bit is a bit that instructs the activation of the next emulation cycle,
When the continuation bit = 1, the next emulation cycle is activated. By using this continuation bit, it is possible to activate the emulation cycle as many times as desired. The R / W bit is a bit indicating whether the emulation cycle to be activated is a read cycle or a write cycle.

The bit definition information of FIG. 65D is as shown in FIG.
It is used in the emulation data generation process together with the bit data information D7 to D0 of (B). This data generation process is performed after the end of the 2nd (memory read) cycle. Whether or not to activate the 2nd cycle is determined by bits 24, 25, and 2 in the command information of FIG.
7 and 28, activated when all these bits are 0. This is because, for example, when the immediate bit = 1, D7 to D0 become the emulation data as they are, and it is not necessary to activate the 2nd cycle. As described above, in this embodiment, it is determined whether or not to activate the second cycle based on the command information read in the first cycle. Therefore, useless activation of the memory read cycle is prevented. Further, in this embodiment, the data generation information is divided into bit data information read in the 1st cycle and bit definition information read in the 2nd cycle. As a result, both the microcode information of the 1st and 2nd cycles can be set to 32 bits, and the output bus of the microcode memory 370 can be 32 bits.
It can be a bit bus. As a result, memory control can be simplified and the hardware can be downsized.

Next, bit 7 of the emulation data
The data generation process will be described with reference to FIG. For example, when the bit data D7 = 1, the table of FIG. 65 (E) is used. That is, when the definition information of bit 7 (bits 31 to 28 in (D) of FIG. 65) is (0000), bit 7 of emulation data is bit 0 of write data from the CPU or emulation read data. Assigned. Similarly, when the definition information is (0001), bit 1 is assigned. Also, the definition information is (100
0), that is, when the inversion bit is 1, an inverted version of bit 0 is assigned to bit 7. In addition, CPU
Whether to allocate the write data or the emulation read data is determined by the write cycle or the read cycle. On the other hand, when D7 = 0, FIG.
When (F) is used and the definition information is (0000), bit 7 is fixed to 0 and when it is (0001), it is fixed to 1. When the definition information is (0010), the emulation data generated last time is assigned. The processing when the definition information is (0011) to (1111) is shown in FIG.
This is as shown in (F). The decoding expansion of FIG. 65 (F) is used when the mode is set in the parallel controller.

5. Specific Example 1 Next, a specific example in the case of performing the emulation process for the serial controller in the sixth embodiment will be described. Third
As described in the above embodiment, as the serial controller, 8251A is used for 98 machines and NS16 is used for AT machines.
550A (8250A) is used. The I / O (port) addresses of these serial controllers are 0030h to 0032h for 98 machines and 03F8h to 03FFh for AT machines. In the 98 machine, the I / O address of the status register of the serial controller is 0032h. Then, as shown in FIG.
The SR is arranged in bit 7 of 0032h in the 98 machine and in bit 5 of 03FEh in the AT machine. Also, SYNC
/ BRK is arranged in bit 6 of 0032h in the 98 machine and in bit 7 of 03FDh in the AT machine. Therefore, 003
When the I / O port of 2h is read, the sub-controller 300 detects two I / Os of 03FEh and 03FDh.
Need to read port. The procedure at this time is shown in FIG.
This will be described using 7, 68.

(1) When 0032h is read by the CPU (see A1 in FIG. 67), the FRAME signal is asserted and the 1st (memory read) cycle of the microcode memory 370 is activated. In the read cycle, bit 15 (R / W bit) = 1 in FIG. 65 (A). Therefore, the address 0032h from the CPU is decoded by the address decoder 360, and the memory address becomes 8032h (see B1 in FIG. 67). Microcode information C07F03FDh is stored in this memory address (see C1). Command information is C
Since it is 0h, bits 24, 25, 27, 28 (Fig. 65)
(See (B)) are both 0, and it is determined that data generation is necessary. This activates the 2nd cycle. The memory address of the 2nd cycle becomes C032h because only the bit 14 (cycle bit) of the memory address 8O32h of the 1st cycle becomes 1. (D1
reference). The data 0731605h is stored at this address (see E1). The data CO7F03FDh, 0731605 obtained as described above
h is latched by the first and second code latches 372 and 374.

(2) I / O of 0032h on the PCI bus
DEV because there is no target with O address
The SEL signal is not asserted. As a result, the sub-controller 300 is set to DEVSE at the timing of subtraction.
When the L signal and the STOP signal are asserted, the PCI cycle started by the CPU ends with a retry.

(3) This time, the sub-controller 300 becomes the master and the SIO 310 becomes the target to start the emulation cycle (see F1). In the 1st cycle, from the command information of the data C07F03FDh (see C1) latched by the first code latch 372, the read cycle (bit 31 in FIG. 65B) is read.
= 1), there is a next emulation cycle (bit 30 = 1), and the emulation address is 03.
It can be seen that it is FDh (bits 15-0). This 0
As shown in FIG. 66, the 3FDh has 98 units of 0032h.
Is the I / O address of the AT machine corresponding to. The emulation data is generated by bit data information 7Fh read in the 1st cycle (see C1) and bit definition information 0731605h (E read in the 2nd cycle).
1)) and emulation read data 61h (see G1) read by the 3FDh read operation. That is, the bit data information and the bit definition information are input from the first and second code latches 372 and 374, and the emulation read data is input from the input buffer 390 to the read data generation unit 382. The read data generation unit 382 generates emulation data from these pieces of information. FIG. 68 shows the generation method. Bit 7 has bit data information of 0 and bit definition information of 0, so 0 is assigned from the table of FIG. 65 (F). Bits 6 to 0 have bit data information of 1
Since the bit definition information is 7, 3, 1, 2, 6, 0, 5, the bits 7, 3, 1, 2, 6, 0 of the emulation read data 61h can be seen from the table of FIG. ,
5 is assigned. As a result, the generated emulation data becomes 07h. This 07h is held in the read data generation unit 382 and used to generate the next emulation data.

(4) Simultaneously with the operation of (3), the read cycle of the microcode memory for the next emulation cycle is activated. The memory address 81FDh (see H1) at this time is generated from the emulation address 03FDh (see I1). In this case, in this embodiment, the upper 8 bits of the memory address are 4
Bits (bits EA3 to EA0 in FIG. 65A) are encoded to save the capacity of the microcode memory. Therefore, the upper byte 03h of the emulation address 03FDh is encoded into 1h, and as a result, the memory address becomes 81FDh. The data 808003FEh is stored at this address (see J1). Command information is 80h and bit 2
Since 4, 25, 27 and 28 are all 0, it is necessary to generate emulation data and the 2nd cycle is activated. The memory address at this time is C1FDh (see K1). Data of 5222222h is stored at this address (see L1).

(5) Next, the sub controller 300
Start the second emulation cycle. 8080
From the command information 80h of 03FEh (see J1), this cycle is the last emulation cycle (bit 30 = 0), and the read cycle (bit 31 = 1) for the I / O address 03FEh (bit 15-0).
I understand. The emulation data includes bit data information 80h (see J1), bit definition information 5222222h (see L1), and I / O address 0.
Emulation read data 20h from 3FEh
(See M1) and the emulation data 07h generated last time. FIG. 68 shows the generation method. Bit 7 has bit data information of 1 and bit definition information of 5 (0101), so that FIG.
According to the table, bit 5 of the emulation read data 20h is assigned. Since bits 6 to 0 have bit data information of 0 and bit definition information of 2 (0010), bits 6 to 0 of the emulation data 07h generated last time are assigned from the table of FIG. 65 (F). To be This 07h is stored in the read data generation unit 382. As a result, the emulation data 87h is generated.

(6) When the second emulation cycle of (5) above is completed, the sub-controller 300 makes R
The EQ signal is deasserted, and the bus access right is given to the CPU. As a result, the CPU retries the read instruction of 0032h (see N1). In response to this read command, the sub controller 300 outputs the emulation data 87h (see O1) obtained in (5) above. Through the above processing, the CPU can read the emulated data.

6. Example 2 Two 8259 interrupt controllers in 98 machines
A is used, and the I / O addresses of the master interrupt controller are 0000h and 0002h. On the other hand, the AT machine also uses two 8259A, and the master I / O addresses are 0020h and 0021.
It is h. In addition, as shown in FIG.
The assignment of the interrupt factor to the interrupt line (interrupt vector) is different between the 8 machine and the AT machine. In the AT machine, the interrupt controllers 305 and 307 are built in the SIO 310 as shown in FIG. Therefore, as described in the fifth embodiment, it is impossible to change the allocation of the interrupt factor to the interrupt line by changing the hardware. So IRQ2 and I
An emulation process for exchanging RQ7 (exchanging the position of the slave) is required.

As shown in FIG. 69B, in the 8259A, even if the I / O address is the same, the accessed register and the like differ depending on the state at that time. For example, even if a read operation is performed on the I / O address 0000h (in the case of 98 machines), access to the IRR register or access to the ISR may occur depending on the state at that time. Also, it is necessary to perform the initialization sequence immediately after reset, and at this time, four types of ICW (Init
ialization Command Word) 1 to 4 are set in order.
Further, in FIG. 69B, IRR and ISR are registers for notifying the current interrupt status, and IMR is a register for setting an interrupt mask. Also, OCW (Op
eration Command Words) 1 to 3 are commands that can be sent to the 8259A after the initialization sequence. The reason why IRQ2 and IRQ7 must be exchanged because the assignment of the interrupt factor to the interrupt line differs between the 98 machine and the AT machine is ICW.
3, OCW1, OCW2, IRR, ISR, IMR 6
Is one. The procedure at this time will be described with reference to FIGS. 70 and 71.

(1) After reset, the 8259A has ICW1
Therefore, the application program (or OS) first receives an IC at 0000h.
Write W1. The write data from the CPU at this time is 11h, which is the same for both 98 and AT machines. The memory address of the 1st cycle at this time is 000.
It is 0h, and the data 00FF0020h is stored at this address (see P1 in FIG. 70). At this time, since the command information is 00h, the 2nd cycle is started, and the memory address of the 2nd cycle is 4000.
h. 76543210h is set to this memory address
Is stored (see Q1 in FIG. 70).
The generation of the emulation data at this time is performed by using the bit data information FFh from the first code latch 372 and the second bit data information FFh.
Definition information 76543 from the code latch 374 of
Based on 210h and the CPU write data 11h from the data latch 358, it is performed by the write data generation unit 378. In this case, the bit data information is all 1 as shown in FIG. 71, and the bit definition information 7, 6, 5,
4, 3, 2, 1, 0. Therefore, as shown in FIG. 71, the emulation data is exactly the same as the CPU write data. Therefore, only the address is converted into 0020h, and the same emulation data 11h as the write data of the CPU is written (see R1 in FIG. 70).
That is, for ICW1, only the I / O address is converted because the exchange process of IRQ2 and IRQ7 is not required.

(2) When ICW1 is set, the application program next sets ICW2. CP
The write address of U is 0002h, and the data is 08
h. The memory address at this time is 0002h,
The data obtained is 02FF0021h. Since the command information is 02h and the AD bit (bit 25 in FIG. 65B) is 1, only address conversion is performed. Therefore, the 2nd cycle is not activated. As a result, in the emulation cycle, the data of 08h is written to the I / O address of 0021h (see S1 in FIG. 70). As described above, in this embodiment, the read cycle of the microcode memory is divided into two, and the command information (AD.
Since it is determined whether to activate the second memory read cycle based on the immediate value / through / ignore bit), useless activation of the memory read cycle is prevented. That is, in the above (1), two memory read cycles are required to perform the process of changing only the address and not the data. However, in (2), this is performed once by using the AD bit. It's done in cycles.

(3) Next, the ICW3 is set. IC
W3 determines the slave position, and the application program for 98 writes 80h to 0002h. As shown in FIG. 72, this is done by setting bit 7 = 1 (80h) in ICW3 to set the slave position to IRQ.
This is because it can be set to 7. However, as described above, in the AT machine, the slave position is IRQ2 (see FIG. 69).
(See (A)), this cannot be changed by changing the hardware. Therefore, when setting ICW3, 04h
Emulation processing for writing (bit 2 = 1) is required. The memory address at this time is 0002h.
However, the address when setting the ICW2 in the above (2) is also 0002h. Therefore, if the memory address is set to 0002h, which is the same as in (2) above, the same microcode information will be read, and ICW2, IC
The emulation processing for W3 cannot be distinguished. Therefore, in this case, the option bit (see FIG.
Bits 12 and 13 of (A) are used. Specifically, O
With P1 = 1, 2002h is generated as a memory address, and the data 01040021h is stored in this memory address. Then, since the command information is 01h and the immediate value bit is 1, the data generation information D7 to D
0 becomes the emulation data as it is. As a result, 04h of the bit data information is directly written to the address 0021h (see T1 in FIG. 70). Also, 2
The nd cycle is not activated.

(4) The end of the initialization sequence is the setting of ICW4. ICW4 I / O address is 0
It is 002h. However, the write data is 1 for 98 machines.
It is Dh, and bit 3 = 0 and bit 2 = 0 are set in the AT machine (in order to enter the non-buffer mode). The memory address in this case also needs to be distinguished from the memory address used for emulation of ICW2 and ICW3. Specifically, OP1 = 1 and OP0 = 1 are set, and the read operation is performed at the memory address 3002h. The data 02F30021h is stored in this memory address. In this case, the command information is 02h, the AD bit is 1, and the bit data information D7 to D0 is F3h.
Becomes Therefore, as shown in FIG. 71, emulation data in which bits 7 to 4 and bits 1 and 0 are the same as CPU write data and bits 3 and 2 are 0 are generated. This allows the I
The data 11h is written to the / O address 0021h (see U1 in FIG. 70).

(5) After this, the 8259A enters the normal operation mode. OCW1 is a command for canceling the interrupt mask. For example, 7Fh must be written to 0002h to enable the slave interrupt. At this time, OP0 = 1 and the memory address is 1002h. The data 00FF0021h is stored in this memory address. In this case, the command information is 0
Since it is 0h, the 2nd cycle is started. The memory address of the 2nd cycle is 5002h, and the stored data is 26543710h. The bit data information is FFh and the bit definition information is 2654371.
Since it is 0h, a process of exchanging bit 2 and bit 7 is performed as shown in FIG. This makes 0021h
FBh is written to (see V1 in FIG. 70). FIG. 73
In OCW1 shown in (1), the interrupt of IRQ7 is enabled when bit 7 = 0 and the interrupt of IRQ2 is enabled when bit 2 = 0. When performing the process of permitting the slave interrupt, the application program for 98 considers that the instruction is issued to 98 machines, and outputs the data 7Fh (bit 7 = 0).
Write IRQ7). Then, the emulation system of the present embodiment converts this 7Fh into FBh (bit 2 = 0 permits IRQ2) and sends it to the hardware of the AT machine. As a result, the AT machine can be operated by the application program for 98, and compatibility can be maintained.

(6) OCW2 returns E during interrupt processing.
This is a command used when issuing an OI (End Of Interrupt). When issuing an EOI to a slave,
The application program is I / O address 0000
The data 67h is written in h. This is an instruction to end the interrupt of IRQ7, but I
The RQ2 interrupt must be terminated. Therefore, it is necessary to change the data to 62h. The memory address in the 1st cycle is 0000h, which is the same as in (1) above, and the obtained data is 00FF0020h. On the other hand, in the 2nd cycle, OP0 = 1, the memory address becomes 5000h, and the obtained data is 76543A1.
It will be 8h. Since the bit data information is FFh, FIG.
Use the table in (E). Then, as shown in FIG. 71, bits 7 to 3 and 1 of the emulation data are directly assigned with the CPU write data. On the other hand, since the inversion bit = 1, the bits 2 and 0 are assigned the data obtained by inverting the bits 2 and 0 of the CPU write data. From the above, 62h is written to the I / O address 0020h (see W1 in FIG. 70).

(7) IMR is a port for reading the mask information written by OCW1, and its I / O
The O address is 0002h. Therefore, the memory address becomes 8002h, and the obtained data is 80FF00.
21h. Also, the memory address of the 2nd cycle is C002h, and the obtained data is 2654371.
It becomes 0h. Since the command information is 80h, it becomes a read cycle, and the data FBh (see X1 in FIG. 70) read at the I / O address 0021h is input to the read data generation unit 382. This read data FBh,
Bit data information FFh and bit definition information 26543
Emulation data is generated by 710h. In this case, the process of exchanging bit 7 and bit 2 is performed as shown in FIG.
Fh is obtained. Then, during the retry operation, the CPU
Will read this 7Fh (see Y1 in FIG. 70). IRR and ISR are interrupt request information,
The method of conversion processing by the boat for reading the service information is the same as in the case of IMR. As described above, the application program for 98 can be operated in the AT machine. (Seventh embodiment) Input data from a keyboard (hereinafter referred to as keyboard data), input data from a mouse (hereinafter referred to as mouse data)
Is very complicated to convert from the one adapted to the first architecture to the one adapted to the second architecture. Therefore, in this case, the emulation processing is performed by the SMI processing as described in the fourth embodiment without using the microcode memory or the like. The seventh embodiment is an embodiment of this conversion process.

First, the emulation processing for reading keyboard data will be described. In the AT machine, Fig. 74
As shown in (A), a one-chip microcomputer 8042 is used as the keyboard / mouse controller 392, and serial communication is performed between this and the one-chip microcomputer 395 in the keyboard 394. Two ports are used for data communication between the CPU and the keyboard / mouse controller 392. The I / O addresses of these ports are 0060h and 0064h, and the port of 0060h is a data port.
The h port is the command and status register port. In the 98 machine, as shown in FIG. 74 (B), the serial controller 8251A is used as the keyboard controller 398, and serial communication is performed between this and the 1-chip microcomputer 401 in the keyboard 400. CPU and keyboard controller 398
Data communication is performed using two I / O boats, but the command of 8042 and the command of 8251A are completely different. In both the AT machine and the 98 machine, when a key on the keyboard is pressed, an interrupt is generated and the CPU is notified of the request to issue the read command. The interrupt is cleared when data is read by the CPU.

Next, the configuration and operation of the seventh embodiment will be described with reference to FIG. In the AT mode, the switch means 410 is on, and when a KBIRQ interrupt occurs, the interrupt controllers 305 and 307.
An INTR interrupt is generated for the CPU 302 under the control of. On the other hand, in the 98 mode, the switch means 41
0 is off, and when the KBIRQ interrupt occurs, the sub controller 300 accepts it and the CPU 3
SMI interrupt to 02. SMM handler (SMBIOS) 301 activated by SMI
Reads the keyboard data from the keyboard / mouse controller 392 when it judges that the cause of the SMI is the keyboard. As a result, the interrupt KBIRQ from the keyboard / mouse controller 392 is cleared. A
The formats of keyboard data (make data, break data, key code table, etc.) are completely different between the T machine and the 98 machine. Therefore, the SMM handler 301 converts the data read from the keyboard / mouse controller 392 using a predetermined conversion table. Next, the SMM handler 301 writes the converted data to the first register 414 in the sub controller 300. When the data is written in the first register 414, the sub controller 300 issues an interrupt KBIRQ ′ to the SIO 310. This allows SIO3
The interrupt controller in 10 generates an INTR interrupt and notifies the CPU 302 of a request to issue a read command. At this time, the SMI processing is completed. CPU30
2 (application program for 98) is INT
Since the R interrupt has occurred, the data register of the keyboard / mouse controller 392 is read. The I / O address of this data register is the sub controller 3
00 has been converted into the I / O address of the first register 414. As a result, the keyboard data converted for 98 is read by the CPU 302. When the first register 414 is read, the interrupt KBIRQ '
Is cleared.

As described above, the keyboard data converted for 98 is read from the keyboard / mouse controller 392 which is the device control means of the AT machine.

[0275] Next, the emulation processing related to the reading of mouse data will be described. In the AT machine, Fig. 74
As shown in (A), serial communication is performed between the keyboard / mouse controller 392 and the one-chip microcomputer 397 on the mouse 396 side. Then, when the operator moves the mouse, a mouse IRQ interrupt occurs. On the 98 machines, the mouse (bus mouse) 408 is the movement amount counter 4
02, the movement amount counter 402 counts the movement amount, and the count value is transmitted to the CPU 302 via the mouse interface (8255A) 406. Further, the timer 404 has a predetermined interval (8 msec-64
msec) generates a mouse IRQ interrupt. Then, the CPU 302 reads the count number counted by the movement amount counter 402 within the predetermined interval each time an interrupt occurs. As a result, the amount of mouse movement is
It is transmitted to 302.

Next, the operation of this embodiment when mouse data conversion is performed will be described. The switch means 412 is ON in the AT mode, but OFF in the 98 mode. When the mouse 396 moves and the keyboard / mouse controller 392 causes a mouse IRQ interrupt, the sub-controller 300 accepts the interrupt and the CP
Generate an SMI interrupt to U302. The SMM handler 301 activated by the SMI reads mouse data from the keyboard / mouse controller 392 when it determines that the cause of the SMI is a mouse. This clears the mouse IRQ interrupt. Next, the SMM handler 301 converts mouse data for 98. That is, as shown in FIG. 76A, the mouse data in the AT machine is composed of 8-bit X information, Y information, and button information. On the other hand, in the 98 machine, as shown in FIG. 76 (B), the data format has a set of 4 bits. Therefore, it is necessary to perform processing for converting the format so that the application program for 98 can read it. In addition to this, conversion processing regarding mouse sensitivity is also required. Next, SMM handler 3
01 writes the converted data to the second register 416 in the sub controller 300. Further, a timer 417 is built in the sub controller 300, and the timer 417 generates an interrupt of the mouse IRQ 'at predetermined intervals. This interrupt causes the CPU 302
The application program for 98 reads the amount of movement of the mouse, but since the I / O address has been converted, the data stored in the second register 416 is read. As a result, the mouse data converted for 98 is read by the CPU 302.

(Eighth Embodiment) An eighth embodiment is a CPU.
It is an example concerning an emulation system in which a sub-controller is provided on a bus. The reason why such an emulation system is necessary is as follows.

(1) In order to further enhance the commercial value of the emulation system, it is desired to have a system which can realize a plurality of compatibility only by mounting an option board in which a sub controller is arranged on the main body device. However, there are the following problems in realizing such an emulation system. That is, as described in the sixth embodiment,
In the emulation system in which the sub-controller 300 is provided on the PCI bus, F is set so that the command from the CPU is not transmitted to the device control means on the ISA bus / X bus.
It was necessary to mask the RAME signal. However, A
The FRAME signal cannot be masked in an emulation system that realizes multiple compatibility simply by mounting an option board on the main unit without changing the main unit of the T machine. Furthermore, an SMI signal is required for emulation by SMI processing, but there is a problem that the PCI expansion slot does not have a terminal for extracting the SMI signal.

(2) 486 chip set or Pent
For the ium chipset, the ones aimed at low prices and those developed for notebook PCs are PCI
Many things cannot be emulated above. First, as shown in FIG. 77A, there is no PCI bus itself (for example, ACC2056 manufactured by Intel).
Secondly, as shown in FIG. 77 (B), although there is a PCI bus, instructions from the CPU 302 do not necessarily pass through the PCI bus. That is, in the configuration of FIG. 77 (B),
When an instruction is issued from the CPU 302 to the device control means on the ISA bus, this instruction is transmitted to the device control means on the ISA bus without passing through the PCI bus. Therefore, in this case, the sub controller on the PCI bus sends the CPU 3 to the device control means on the ISA bus.
It is impossible to prevent the command from 02 from being transmitted. Particularly, in the future, as the cost of the system is reduced, the system having the configuration shown in FIGS. 77A and 77B may become mainstream. Therefore, even in these cases, the CPU
A configuration in which a sub controller is provided on the bus is effective.

According to the emulation system in which the sub controller is provided on the CPU bus, the above problems (1) and (2) can be solved. FIG. 78 (A) shows an example of the configuration of such an emulation system. Note that FIG.
8 (B), the sub-controller 3 only on the PCI bus
The configuration of the emulation system with 00 is shown.
In FIG. 78 (A), the first sub-controller 424 is C
This first sub-controller 4 provided on the PU bus
A second sub-controller 431 that performs emulation processing together with 24 is provided on the PCI bus. Here, the first sub-controller 424 controls the signal from the CPU 302, and the second sub-controller 431 includes a video controller for 98 and the like. This first sub-controller 424 is connected to the first option board 42
0 and the second sub-controller 431 is arranged on the second option board 430, a plurality of compatibility can be realized only by mounting the option board on the main unit.

FIG. 79A shows an example of an option board mounting method in this case. First, the CPU 30
1st socket (PGA socket etc.) 4 to which 2 can be attached 4
22 and a first option board 420 including a first sub-controller 424 is prepared. In addition, the second option board 43 including the second sub-controller 431
Prepare 0. This second sub-controller 431
Video controller 4 for BIOS ROM 432,98
34, FM sound controller 436, RTC438
Etc. These are necessary for operating the application program for 98 using the AT machine. The second option board 430 can be connected to a PCI expansion slot 429 provided on the main board 426. Further, a second socket 428 to which the CPU 302 can be attached is provided on the main board 426. The first option board 420 is mounted as follows. That is, first, the CPU 302 is pulled out from the second socket 428 on the main board 426. Next, the plurality of pins 425 on the lower portion of the first option board 420 are inserted into the pin holes 429 of the second socket 428. Then, the pin hole 423 of the first socket 422
A plurality of pins 427, which are terminals of the CPU 302, are inserted into. A signal from the first pin hole group forming the pin hole 423 is transmitted to the first pin group forming the pin 425. On the other hand, the signal from the second pin hole group forming the pin hole 423 is transmitted to the second pin group forming the pin 425 via the first sub-controller 424. Thereby, the first signal group from the CPU 302 is transmitted to the main board 426, and the second signal group from the CPU 302 (for example, ADS signal etc.) is controlled by the first sub-controller 424.
You can turn off the transmission to 6.

As described above, the first option board 420 is mounted, and the PCI expansion slot 429 is secondly mounted.
The emulation system is realized by mounting the option board 430 of.

FIG. 79B shows an example of the structure of the first sub controller 424. The first sub controller 424 includes a CPU bus interface unit 440, an instruction conversion unit 442, and an SMI control unit 446. The CPU interface means 440 controls the CPU bus and the like, and the details will be described later. The instruction converting means 442 converts an instruction by a hardware circuit and includes, for example, a microcode memory.
The SMI control means 446 is a circuit for performing SMI processing, and includes SMI generation means, SMI status and the like.

Next, the operation of the eighth embodiment immediately after RS (reset) (or immediately after power-on) will be described with reference to FIGS.
This will be described using 1 (A) to (C). As shown in the flowchart of FIG. 80, in this embodiment, after RS, the BIOS ROM 432 on the second option board 430 is used.
Start from 98-BIOS stored in (steps V1, V2). AT-BIO which is the BIOS of the AT machine
S is on the X bus (or ISA bus). Therefore, the second
Sub-controller 431 is faster than SIO310
98-BIOS can be prioritized by asserting the EVSEL signal. However, AT-BIOS and 98-
When the ROMs storing the BIOS are on the same bus, for example, both are on the ISA bus or the CPU bus, 98-BIOS cannot be prioritized by the above method. Therefore, in this case, 98
-Priority is given to BIOS. FIG. 81A is a flowchart for explaining the operation of this method. First, RS
Immediately after that, the CPU is FFFFFFF0h (A in FIG. 81B).
1) is accessed (step W2). Next, CP
The U interface unit 440 masks the ADS signal, and the masked signal LADS is transmitted to the device control unit. As shown in FIG. 81 (C), this mask processing is performed based on a mask signal that is set when RS = L and reset when BRDY = L. The ADS signal is an address and a bus cycle definition signal (M / IO,
D / C, W / R) is a valid signal,
This signal indicates that the CPU has started the bus cycle. Therefore, when the ADS signal is masked, other circuits on the CPU bus do not respond to the first CPU command. Next, the first sub-controller 424 (JMP 1FFF
F0h) command is issued (see B1 in FIG. 81C),
BRDY (ready signal) is enabled. Then, as shown in FIG. 81 (B), a jump to 1FFFF0h is performed and 98-BIOS is executed. Also, AT-B
IOS is disabled, 98-BIOS is E80
Moved from 00 to FFFFFh. This guarantees normal operation thereafter. Next, E8000-FFFF
The 98-BIOS moved to Fh is executed (step W5). As described above, 98-BIOS is prioritized and executed.

Returning to the description of FIG. After the start from 98-BIOS, initial setting processing is performed (step V
3). Next, it is determined whether or not the special key is input (step V4), and if it is input, the menu screen is displayed (step V5). This menu screen enables selection of AT mode or 98 mode (step V6). Whether or not the special key is input is determined by, for example, whether or not a predetermined key combination (key combination) is input. If the special key is not input, the process proceeds to step V7 and the previous setting becomes valid. As a result, even after the power is turned on or the hardware is reset, the operation is performed in the previously set mode, and the trouble of mode selection can be saved. When the AT mode is selected, the CPU jumps to AT-BIOS (step V8), and when 98 is selected, 98-BIOS is continuously executed (step V9). When the emulation system is realized by using the hardware of the AT machine, it is desirable to use that of the AT machine as the casing (exterior member of the device). However, when the casing of the AT machine is used, there arises a problem that the mode selection switch cannot be provided near the front of the user who operates the apparatus. Therefore, this embodiment solves this problem by enabling mode selection by a special key.

Next, the processing when software reset is performed will be described. Some AT machines may not have a hardware reset switch. In this case, the device must be reset by software. While the BIOS for emulation is operating, a key combination for mode switching can be prepared to display a mode switching menu. However, the AT machine has only one type of key combination for software reset. Therefore, there is a problem that the 98 mode cannot be switched while the AT-BIOS is being executed. Therefore, in the present embodiment, in order to solve this, a routine for generating an SMI is included in the software reset routine in the AT-BIOS. Since the BIOSROM is almost always a flash memory, such rewriting is easy. Then, in the SMM activated by the SMI, a menu for selecting the software reset or the change to the 98 mode is displayed. For hardware reset and mode selection at power-on, S
It can be performed by MI processing. Furthermore, SMI
It is also possible to prepare an I / O port for generating the I / O address at a position of an accessible I / O address in the DOS (OS) operating on the AT. In this way DOS
By inputting "CG98" or the like with a command, a specific I / O port is accessed and an SMI occurs. This makes it possible to shift to the 98 mode. In this case, a plurality of I / O ports that generate SMI can be prepared. This allows not only mode switching but also a plurality of processes to be performed after switching. As the processing after this switching, a specific program (word processor, etc.)
It is conceivable to perform a process for operating. For example, if a 98 program activation command is prepared and this command is executed on the AT machine, the I / O port designated by the command is accessed and an SMI occurs. Then the SMM is 98
Write the program name in the autostart file for.
Then, the desired program is started immediately after switching to the 98 mode.

Furthermore, when a specific key combination is input in the 98 mode, hardware reset may be executed by emulation by SMI. This is effective when emulating an emulation system using an AT machine without a hardware switch.

FIG. 82 shows an example of a circuit diagram of the CPU interface means 440. Also, FIG. 83 and FIG.
4 shows a flowchart showing the operation of this embodiment,
FIG. 85 shows a signal waveform diagram. Hereinafter, the configuration and operation of the present embodiment will be described in detail with reference to these drawings.

First, in the AT mode, the signal EN98 =
Then, the high speed switch 471 shown in FIG. 82 is turned on. As a result, the ADS signal from the CPU 302 is directly transmitted to the device control means, and the AT machine can be operated at high speed. On the other hand, in 98 mode, EN
98 = L, and the high speed switch 471 is turned off. next,
It is determined whether HADS (host ADS signal) = L (step W1 in FIG. 83). Thereafter, it is determined whether or not M / IO = L, and when M / IO = H (in the case of memory access), the DADS signal, that is, the signal obtained by delaying ADS by one clock (see A1 in FIG. 85) is LADS. The signal is transmitted to the device control means, which is the command destination of the CPU (step W8). This guarantees that the memory access is delayed by only one clock, and the system can operate at high speed. On the other hand, M / IO
= L, that is, when the CPU instruction is an I / O instruction, the DADS signal is masked. As a result, the DADS (LADS) signal is not transmitted to the device control means, and the transmission of the command from the CPU to the device control means is invalidated. As another method of invalidating the instruction in this way, the DADS signal is transmitted as it is without being masked, and the bus control signal (M / IO, D /
A method of converting C, W / R) is also conceivable. For example M /
With IO = H, D / C = H, W / R = H, the bus cycle is set to a special cycle, and BE7 to BE0 = (111
11011), the device control unit considers that the CPU has executed the HALT instruction and terminates the access from the CPU without performing an extra operation that causes a malfunction. This makes it possible to invalidate the instruction of the CPU. However, BE
Even if the bus cycle is set to the special cycle without fixing 7 to 0 to the above value, the purpose of not allowing the device control means to respond to the instruction of the CPU can be achieved.

Then, as shown in step W4, it is determined whether or not the conversion processing by the instruction converting means 442 is necessary.
When it is determined that the conversion processing is not necessary, the DDADS signal which is a signal obtained by delaying DADS by one clock is transmitted to the device control means (step W9). One clock is delayed here because it takes time to determine whether conversion is necessary. Therefore, in some cases, it may be delayed by two clocks or more. Then SMI
It is judged whether or not conversion by
I is generated and SMI processing is performed (step W10).
~ W12). These processes are performed by the SMI control means 4
At 46. In the SMI processing, instruction conversion processing by software is performed. On the other hand, the instruction conversion means 4
HBOFF when conversion processing by 42 is required
(Back-off signal) = L (B1 in FIG. 85). This causes the CPU to release control of the bus. And CPU
Remains in the bus hold state until HBOFF = H. After that, the I / O instruction is analyzed, the conversion processing of the I / O instruction is performed, and the converted I / O instruction is executed (FIG. 8).
3 steps W6, W7).

Next, the operation described above will be described with reference to the circuit diagram of FIG. When EN98 = L, DFF47
The set terminal of 2 = H. Therefore, HADS (AD
S) signal is sampled by DFF 472 and DFF4
From 72, the signal DADS which is a delay of HADS by one clock
Is output. When M / IO = H (for memory access), one input of the logic circuit 476 is L
Since EMSTART = L, emulation does not start. Further, the DADS signal is sent to the logic circuit 47.
8,480,482, resulting in HA
DADS, which is a signal obtained by delaying DS by one clock, is transmitted to the device control means. This enables high-speed memory access. On the other hand, when M / IO = L (I / O
In the case of an instruction), the DADS signal is transmitted as an EMSTART signal to the instruction converting means 442 via the logic circuit 476. This starts the instruction conversion process. on the other hand,
Since the output of the logic circuit 478 is fixed to L, DADS is not transmitted to the device control means. When the instruction conversion process is started, the instruction conversion unit 442 firstly outputs CBOFF =
Let L. As a result, the high speed switches 497 and 498 are turned off, and the signal input to the CPU 302 is cut off. Further, the CBOFF signal is transmitted to the CPU 302 via the tri-state buffer 486, whereby the CPU 30
2 enters a back-off operation and stops bus access. Then, the instruction conversion means 442 makes a bus access this time. Then, I / O instruction is analyzed, and if necessary, I / O
The address and data included in the O instruction are converted.
Further, the instruction converting means 442 operates as a master of the CPU bus instead of the CPU and drives HA0 to 15 and HBE0 to 7 through the buffers 492 to 495. In the write cycle, HD0 to 31 are also driven. In this way, the instruction conversion unit 442 executes the converted I / O instruction.

FIG. 84 is a detailed flowchart showing the operation at the time of instruction analysis / conversion and instruction execution (steps W6 and W7 in FIG. 83). First, in step X1, the instruction conversion means 442 drives HA0 to 15 etc.
Set DS = L (D1 in FIG. 85). Then, in the case of I / O read, it is monitored whether LBRDY = L (step X3), and when LBRDY = L (E1 in FIG. 85), the data output to the HD (host data bus, CPU bus) is checked. The data is stored in R-RG (a save register in the instruction conversion means) and data conversion processing is performed (step X4). After that, it waits until the device control means of the command destination releases the bus, and sets HBOFF = H (steps X5, X6 and C1 in FIG. 85). As a result, the CPU executes the invalidated bus cycle again. This operation is the same as the retry on the PCI bus. Then, when the CPU re-accesses, the R-RG data is output to the HD (steps X7, X8 and F1 in FIG. 85). Then HBR
Set DY = L (step X9). Further, in the case of I / O write, by outputting the converted data to the HD, this data is given to the device control means, and when the device control means sets LBRDY = L, the HD is set to high impedance (step X10-X10). X12). Then, after that, HBOFF = H is set and the CPU is re-accessed (steps X13 and X14). As described above, in this embodiment, the HBOFF (back off) signal of the CPU is asserted even in the case of I / O write. This is some I /
At O port, C at least until LBRDY = L
This is because it is necessary to stop the PU. However, L
As another method of stopping the CPU until BRDY = L, a method of using the HOLD signal can be considered. However, according to the method using the HOLD signal, it is necessary to control different signals at the time of reading and at the time of writing, and the circuit becomes complicated and large-scaled. Therefore, in this embodiment, HB
The CPU is stopped using the OFF signal. And
The current cycle is ended by setting HBRDY = L when the CPU re-accesses. By doing so, the operation of the CPU can be stopped without using the HOLD signal.

In the sixth embodiment and the like, the PCI retry is used only in the read cycle. However, the retry can be used also in the case of the write cycle as described above. Also in this case, the CPU is stopped until at least TRDY = L is set by the device control means which has provided the converted data. Then, when the CPU is re-accessed, the bus cycle of the CPU may be ended by setting TRDY = L. Further, the HBOFF signal is often used by device control means other than the first sub-controller 424. Therefore, it is necessary to take measures when the HBOFF signal is asserted simultaneously by the first sub-controller 424 and other device control means. Therefore, in this embodiment, when LBOFF = L as shown in FIG. 82, the outputs of the tri-state buffers 482 and 491 to 495 are set to the high impedance state. Further, the logic circuit 496
Fixes ICLK to L. As a result, the first sub-controller 452 is integrated with the CPU 302,
The CPU 302 performs the same operation as when the CPU 302 is in the back-off state, and the compatibility is maintained.

(Ninth Embodiment) FIG. 86 shows a ninth embodiment of the present invention.
An example of the configuration of the embodiment is shown. The difference from the eighth embodiment is that the first sub-controller 452 does not include the instruction conversion means and the SMI control means, and these are included in the second sub-controller 462. Further, the first and second option boards 450 and 460 are provided with connectors 456 and 459, respectively, and the SMI signal and the EMIO signal are transmitted via the cable 458, which is also different. The circuit configuration of the CPU interface unit 454 is as shown in FIG. 87, which is a circuit configuration different from that of the instruction conversion unit of the eighth embodiment.

CPU in first sub-controller 452
The interface unit 454 receives an instruction from the CPU I
In the case of the / O instruction, it is converted into an instruction that cannot be accepted by other device control means, that is, an instruction of an address that is not normally accessed. Specifically, M / IO = H,
The conversion for setting A31 = H is performed. Then, the instruction converting means 464 in the second sub-controller 462 is A31
A signal, an EMIO signal transmitted via a cable, or the like is used to determine whether or not the I / O instruction requires emulation processing. However, it is also possible to make this determination only with A31 (in this case, the EMIO signal is not necessary),
It is also possible to make a determination based on A30 or the like. When it is determined that the I / O instruction requires emulation processing, the instruction conversion means 464, the SMI control means 466, etc. perform emulation processing. The option board 46
When the SMI control means 466 is provided in the 0, means for transmitting the SMI signal, for example, the cable 458 or the like is required.

The advantage of the ninth embodiment over the eighth embodiment is that the circuit provided on the first option board 450 can be downsized. For example, in the case of a circuit of the scale shown in FIG. 87, it is possible to configure the first sub-controller 452 with a one-chip PAL (programmable logic array). If the circuit can be downsized in this way, the first option board 450 can also be made smaller, which is advantageous when the space around the first option board 450 is narrow. Further, although the sub-controller 300 is provided on the PCI bus in the sixth embodiment, the circuit of the sub-controller 300 and the second sub-controller 448 can be shared by the configuration of the ninth embodiment. . This can shorten the development period.

Next, the configuration and operation of the CPU interface means 454 will be described in detail with reference to FIGS. First, when EN98 = H, the operation is almost the same as a normal AT machine as in the eighth embodiment. On the other hand, when EN98 = L, the signal DADS obtained by delaying HADS by 1 clock is output from the DFF 562. When M / IO = H (memory access), the output of the logic circuit 566 is fixed at L. Also, the logic circuit 5
The DADS signal is transmitted to the device control means via 68, 580 and 582, and the high speed operation of memory access can be maintained. On the other hand, when M / IO = L (for I / O access), a signal obtained by delaying HADS by 3 clocks is transmitted to the device control means via the logic circuits 566, DFFs 585 and 586, and logic circuits 580 and 582. (H1 in FIG. 88). When EN98 = L, the high speed switch 5
97 is off and the high speed switch 598 is on. Therefore, LM / IO is always at H level. And DAD
When S = L, EM is generated by the logic circuits 587 to 590.
IO = L (I1 in FIG. 88), high-speed switch 593
Turns off and the high speed switch 594 turns on. Therefore, A31 = H (J1 in FIG. 88). Also, LBR
When DY becomes L, DFF591 etc. cause EMIO =
It becomes H and A31 is not fixed at H level (Fig. 8).
8 K1). As described above, according to this embodiment, the emulation processing can be realized by using the small-scale CPU interface means.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, in the above embodiment, considering that the market size occupied by hardware and software is very large worldwide as the first computer architecture,
As the second computer architecture, we thought of ones in which these markets are relatively medium in size but want to respect software assets. However, the first and second computer architectures of the present invention are not limited to these, and the present invention can be naturally applied even in the case of a relationship opposite to the above. In this case, for example, the emulation processing of the serial interface may be performed so that a predetermined application can be executed on the 8251A. Further, the emulation process for the keyboard may be performed so that a predetermined application can be executed on the 8251A.
It is obvious that the emulation processing in this case can be performed by the same method as described in the above embodiment. Further, the second computer architecture in the present invention means one or a plurality of computer architectures different from the first computer architecture. Similarly, the first computer architecture differs from the second computer architecture 1
Or, it means multiple computer architectures.

Also, when operating a program for an Apple Macintosh computer using an AT machine or 98 machine, or conversely, when operating a program for AT or 98 using a Macintosh computer, The principles of the present invention are applicable. Furthermore, the principle of the present invention can be applied to the case where all the programs for AT, 98, and Macintosh are operated using a computer of one architecture, for example, an AT machine.

Further, the method of analyzing the instruction and setting the factor data in the present invention is not limited to the above-mentioned embodiment, and any kind of method can be considered.

Further, in the above embodiment, the bus arbiter was built in the sub-controller, but the present invention is not limited to this, and the bus arbiter may be arranged outside the sub-controller.

In the case where the sub-controller or the like is arranged on the option board, the program such as the SMM handler is loaded on the floppy disk or the CDROM, for example.
It may be stored in an external storage device such as the above and loaded into the RAM of the personal computer system to execute a predetermined process by the SMM handler. Also, SMR
For the AM, the RAM of the personal computer system of the first architecture may be diverted, or a unique storage device may be provided on the board and used as the SMRAM.

In the above embodiment, the Pentium having the pipeline processing function is used as the CPU, but any other CPU (for example, S manufactured by Intel Corporation) is used.
LEnhanced486, POWER PC manufactured by Motorola / IBM, etc.) can of course be used. Also, in this Pentium, when SMI occurs,
There is a possibility that CPU processing is proceeding to the next instruction due to a pipeline or the like. In such a case, the CPU may be retried so that the SMI is generated after the desired instruction.

The control device of the first architecture, such as the memory controller 11, is RA-dependent according to its specifications.
Although it is assumed that the address setting of the externally connected device such as M cannot match the address used by the second architecture, it is possible to sufficiently cope with it by inserting an appropriate decoder circuit.

Further, in the present invention, depending on the architecture to be selected, the processing may be very complicated, and it may be difficult to perform emulation processing due to the demand for high speed. In such a case, a plurality of minimum required hardware may be provided in the information processing device. For example, the video controller, the FDD controller, and the like may have a plurality of architectures built in the information processing apparatus.

Further, in the above embodiment, S is used as the interrupting means.
Although the MI is used, the interrupting means to be developed in the future can be used in the same manner as long as it has the same characteristics as the SMI described above.

The configuration of the present invention using the microcode can be applied not only to a plurality of compatibility but also to various emulation systems.

The structure in which the sub controller is provided on the CPU bus is not limited to those shown in FIGS. 78 (A) and 86. For example, in FIG. 78A, all the components included in the second sub-controller 431 may be included in the first sub-controller 424, and the second sub-controller 431 may not be provided. Alternatively, it is possible to include only a part of them, such as the RTC, in the first sub-controller 424. The configuration of the first board is also shown in FIG.
9A is not limited to that shown in FIG. 9A, means for connecting the terminals of the CPU and the terminals of the second socket on the main board, and C
It is sufficient that there is a means for connecting the terminal of the PU and the terminal of the second socket via the first sub-controller. For example, in FIG. 89 (A), on the first option board 1000,
A first socket 1004 to which the CPU 1002 can be attached and a first sub controller 1006 are provided. Also,
A connection connector 1008 is provided on the back surface of the first option board 1000, and the connection connector 1008 is attached to the second socket 1010 on the main board. First socket 1004, first sub-controller 1000
6. The connector 1008 is connected by a predetermined wiring line. Further, in FIG. 89B, the first option board 1012 has a multilayer wiring board structure, the first socket 1004 and the first sub-controller 1006 are provided thereon, and the back surface of the first option board 1012 is provided. A connection connector 1014 is provided. The cross-sectional view is shown in FIG. 89 (C). With this configuration, the option board can be made smaller. Further, in FIG. 89 (D), the CPU 1022 is a first device such as a TCP (tape carrier package)
It is mounted on the option board 1020. With this configuration, the CPU 1022 is always mounted on the first option board 1020, so the manufacturer side
It is necessary to supply 22 as well. However, with this configuration, the mounting area can be reduced. In addition, FIG. 89 (E)
Is an example in which the ODP socket 1026 in which the ODP (overdrive processor) 1028 is mounted is the second socket. In this case, the ODP 1028 is removed from the ODP socket 1026, and the first option board of the present invention is attached to the ODP socket 1026. And
The removed ODP1028 is mounted on the first option board. Therefore, in this case, the ODP 1028 corresponds to the central control means in the present invention. The ODP 1028 may be mounted by TCP or the like as shown in FIG. 89 (D).

Furthermore, the first and second boards of the present invention need not be optional boards. Further, the third board is not limited to the main board and may be a board called a CPU board.

[0311]

As described above, according to the present invention, the first
It is possible to maintain compatibility of application programs, OS, etc. developed for the
Multiple compatibility can be realized. In addition, it becomes possible to perform memory management in a unique control mode, and it is possible to easily realize complicated processing that requires the use of a conversion table.

Further, according to the present invention, it is possible to effectively prevent a situation in which the address position where the data necessary for the predetermined processing is stored is rewritten by the application program or the like and the predetermined processing cannot be executed. .

Further, according to the present invention, for example, the data read by the instruction converted by the emulation processing can be automatically restored in the internal register of the central control means, and the processing is simplified. To be done.

Further, according to the present invention, it is possible to realize an emulation system which is highly compatible and hardly malfunctions, and the reliability of the system can be improved.

Further, according to the present invention, the program development can be facilitated, and the program development cost and the development period can be reduced.

Further, according to the present invention, there is no need to use NMI or INT, and a system having high compatibility and high reliability can be provided.

Further, according to the present invention, even when there are a plurality of display modes such as a standard resolution mode and a high resolution mode, switching between these modes can be easily performed.

Further, according to the present invention, since the method of emulation processing is changed depending on the type of instruction, the problem of slowing down the processing in software emulation and the problem of deterioration of compatibility in hardware emulation. Can be solved.

Further, according to the present invention, the data can be properly transmitted to the central control means by utilizing the functions such as retry and back-off.

Further, according to the present invention, the data obtained after the emulation processing can be automatically transmitted, and the processing can be simplified.

Further, according to the present invention, conversion of instructions can be performed at high speed by using a microcode memory or the like, so that it is possible to prevent loss of data or the like.

Further, according to the present invention, emulation processing is performed so that instructions cannot be converted by mere bit rearrangement processing, or processing such as command instruction and mode instruction has to be divided into two. It is also possible to realize various emulation processing.

Further, according to the present invention, for example, even when the baud rate is fixed to one by the first device control means, another type of baud rate can be used. Further, according to the present invention, for example, a complicated emulation process in which a command or a parameter is discriminated and the emulation process is performed based on the discrimination result, or the data conversion is performed based on a predetermined conversion table. Will also be feasible.

Further, according to the present invention, instruction conversion can be performed at high speed using a microcode memory or the like.

Further, according to the present invention, even when the interrupt line cannot be exchanged, for example, when the interrupt factor generating unit and the interrupt controller unit are built in one IC, it is possible to emulate the interrupt. Rate processing is possible.

Also, according to the present invention, the interrupt vector converted can be transmitted to the central control means by utilizing the interruption and re-execution of the processing of the central control means.

Further, according to the present invention, it is possible to prevent the instruction of the second computer architecture from being transmitted to the first device control means or the like by a simple method of controlling the control signal of the bus.

Further, according to the present invention, even if there is a device control means such as a video controller which is difficult to emulate, a plurality of compatibility can be realized.

Further, according to the present invention, it is possible to use, for example, the case of the first architecture as the casing (exterior member) of the main body device, which makes it possible to reduce the cost of the device and the effectiveness of past assets. It can be used.

Further, according to the present invention, it is possible to realize a complicated emulation process such that it is necessary to repeat the read cycle and the write cycle a plurality of times.

Further, according to the present invention, complicated emulation data of various patterns can be generated.

Further, according to the present invention, it is possible to prevent useless memory read cycles from occurring, and speed up the emulation processing.

Also, according to the present invention, various data conversions such as bit exchange processing, data fixed value conversion, and decoding expansion can be performed using the bit definition information.

Further, according to the present invention, by simply storing desired data in the microcode memory, the data can be used as it is as emulation data.

Further, according to the present invention, emulation processing only by address conversion can be realized at high speed.

Further, according to the present invention, for example, one I /
Even when the O port is a port that can read or write different data depending on the situation, the emulation processing of the I / O instruction for the I / O port can be realized.

Further, according to the present invention, emulation processing which requires complicated data conversion processing such as keyboard input data and mouse input data can be easily realized.

Further, according to the present invention, the keyboard input data conversion processing which requires complicated processing can be easily realized by using the conversion table.

Further, according to the present invention, even if the format of the input data from the mouse is significantly different between the first and second computer architectures, the conversion processing can be easily realized.

Further, according to the present invention, it is possible to provide an emulation system which is realized only by mounting an option board or the like, and it is possible to enhance the commercial value. Further, it is possible to provide an optimum emulation system for a low-priced information processing device such as a laptop computer having a simple bus configuration.

Further, according to the present invention, it becomes possible to transmit emulation data and the like to the central control means by using, for example, the back-off function of the central control means.

Further, according to the present invention, it is possible to effectively use the device control means such as the video controller and the FM sound controller which are not supported by the first computer architecture.

Further, according to the present invention, the circuit provided on the first board can be miniaturized, and for example, one chip PAL can be used.
It is possible to provide the emulation system most suitable for the information processing apparatus in which the first board has to be made small due to the space problem.

Further, according to the present invention, it is possible to convert into a command which the first device control means or the like cannot accept, by a simple method.

Further, according to the present invention, it is possible to transmit the emulation data and the like to the central control means by using the retry function and the like.

Further, according to the present invention, for example, a video controller, an FM sound controller, etc. can be effectively used.

Further, according to the present invention, it is possible to realize an emulation system utilizing the interrupt even when there is no interrupt signal terminal in the expansion slot.

Further, according to the present invention, the processing speed can be increased when the instruction is compatible with the first computer architecture.

Further, according to the present invention, it is possible to minimize the decrease in access speed to the memory.

Further, according to the present invention, a more compatible emulation system can be realized and the cost of the device can be reduced.

Further, according to the present invention, it is possible to provide an emulation system which can be realized only by mounting the first board.

Also, according to the present invention, an emulation system can be realized by a simple mounting method.

Further, according to the present invention, the emulation system can be realized by using the first board on which the central control means is mounted by TCP or the like.

Further, according to the present invention, by providing two sub-controllers, it is possible to provide an emulation system which is more compatible and rich in variety.

Further, according to the present invention, it is possible to realize an emulation system utilizing the interrupt even when there is no interrupt signal terminal in the expansion slot.

[0356]

[Brief description of drawings]

FIG. 1 is a block diagram illustrating hardware of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a hardware configuration for switching memory mapping.

FIG. 3 is a diagram illustrating the concept of the present invention.

FIG. 4A is an NMI in real mode.
It is a figure which shows operation | movement of a process, FIG.4 (B) is the flowchart.

FIG. 5A is a diagram illustrating N in a protect mode.
It is a figure which shows operation | movement of MI processing, and FIG.5 (B) is the flowchart. Further, FIG. 5C is a diagram illustrating a stack area.

FIG. 6 is a flowchart illustrating the operating principle of SMI processing.

FIG. 7: I / O reception means in sub-controller, SMI
It is an example of a circuit configuration of a mask means, an SMI status, and an SMI generating means.

8A and 8B are diagrams for explaining a hierarchical structure of a factor register and a mask register.

FIG. 9 is an example of a circuit configuration when the factor register and the mask register have a hierarchical structure.

FIG. 10 is an example of a circuit configuration when the factor register and the mask register have a hierarchical structure.

11A to 11C are examples of circuit configurations of a reset detection unit, a speed switching detection unit, and a power interruption detection unit.

12A and 12B are flowcharts showing the operation of a sub-controller having a hierarchical structure.

FIG. 13 is an example of a signal waveform diagram for setting factor data.

FIG. 14 is a flowchart showing the operation of this embodiment after entering the SMM mode.

FIG. 15 is a flowchart of reset processing.

FIG. 16 is a flowchart showing an operation of I / O write emulation processing.

FIG. 17 is a diagram showing a part of setting states of a memory map and a memory setting register corresponding to two display modes.

FIG. 18 is a diagram showing an example of a configuration of a bus arbiter.

FIG. 19 is a diagram showing an example of a configuration of a bus arbiter.

FIG. 20 is a state transition diagram showing the operation of the bus arbiter.

21A to 21C show SMI processing and N.
It is a memory map figure for demonstrating MI processing.

FIG. 22 is a flowchart of a first conversion method.

FIG. 23 is a flowchart of a second conversion method.

FIG. 24 is a flowchart of a third conversion method.

FIG. 25 is a flowchart of a fourth conversion method.

FIG. 26 is a block diagram of a second embodiment.

FIG. 27 is a detailed block diagram of a sub controller.

FIG. 28 is an example of a circuit configuration of a bus arbiter.

29 (A) and 29 (B) are diagrams showing types of registers incorporated in the serial controller and I / O port addresses.

30 (A) and 30 (B) are flowcharts of data transmission in the conventional hardware and the third embodiment.

31A is a flowchart of emulation processing for data transmission, and FIG. 31B is a signal waveform diagram of each signal in this case.

32A to 32C are mode registers,
It is a figure which shows the content of a command register and a status register.

FIG. 33 is a diagram showing the arrangement and contents of each register of two serial controllers.

FIG. 34 is a diagram showing the arrangement and contents of each register of two serial controllers.

FIG. 35 (A) is a flow chart of command write emulation processing, and FIG. 35 (B) is a signal waveform diagram of each signal in this case.

FIG. 36 is a detailed flowchart of the command write emulation processing.

FIG. 37 is a detailed flowchart of command write emulation processing.

FIG. 38 is a detailed flowchart of emulation processing of mode instructions.

39A and 39B are flowcharts of data reception in the conventional hardware and the third embodiment.

FIG. 40 is a detailed flowchart of emulation processing for data reception.

FIG. 41 is a signal waveform diagram of each signal for emulation processing of data reception.

FIG. 42 is a flowchart of status read emulation processing.

FIG. 43 is a diagram showing the arrangement and contents of each register of 8042 and 8251A.

FIG. 44 is a diagram showing the arrangement and contents of the registers 8042 and 8251A.

45 (A) and 45 (B) are flowcharts of command transmission to the keyboard in the conventional hardware and the fourth embodiment.

FIG. 46 is a detailed flowchart of emulation processing for command transmission.

47 (A) and 47 (B) are flowcharts of command writing in conventional hardware and the fourth embodiment.

48 (A) and 48 (B) are flowcharts of data reception in the conventional hardware and the fourth embodiment.

FIG. 49 is a detailed flowchart of emulation processing for data reception.

50A and 50B are flowcharts of status read in conventional hardware and the fourth embodiment.

FIG. 51 is a diagram showing a comparison of interrupt vectors between the first architecture and the second architecture.

52A is a flowchart of emulation processing for interrupt vector conversion, and FIG.
FIG. 6 is a diagram for explaining a method for switching interrupt vectors by mode switching.

FIG. 53 is a signal waveform diagram of each signal in emulation processing of interrupt vector conversion.

FIG. 54 is a diagram showing a configuration of conventional hardware.

FIG. 55 is a flowchart showing an operation of switching between two display modes in conventional hardware.

56 (A) to (C) are diagrams showing a plurality of compatible implementation modes.

FIG. 57 is a diagram showing an overall configuration of a sixth embodiment.

FIG. 58 is a diagram showing an example of a circuit configuration of instruction converting means.

FIG. 59 is a diagram showing a relationship between a main body device and an expansion slot box.

FIG. 60 is a signal waveform diagram for explaining the operation of the sixth example in the write cycle.

FIG. 61 is a signal waveform diagram for explaining the operation of the sixth example in the read cycle.

FIG. 62 is a flowchart showing the operation of the sixth embodiment.

FIG. 63 is a flowchart showing an operation of the sixth example in the emulation cycle.

FIG. 64 is a flowchart showing the operation of the instruction converting means.

65 (A) to (F) are diagrams for explaining microcode information.

FIG. 66 is a diagram showing the contents of the status register of the serial controller.

FIG. 67 is a specific example 1 of the emulation processing according to the sixth embodiment.
It is a figure for explaining.

FIG. 68 is a diagram for explaining a method of instruction conversion.

69 (A) is a diagram showing assignment of interrupt factors to interrupt lines, and FIG. 69 (B) shows 825.
It is a figure for demonstrating the I / O port of 9A.

FIG. 70 is a specific example 2 of the emulation processing according to the sixth embodiment.
It is a figure for explaining.

FIG. 71 is a diagram for explaining a method of instruction conversion.

FIG. 72 is a diagram for explaining ICW1 to ICW4.

FIG. 73 is a diagram for explaining OCW1 to OCW3.

74 (A) and (B) are diagrams for explaining a keyboard controller and a mouse controller.

FIG. 75 is a diagram showing the configuration of the seventh exemplary embodiment.

76 (A) and (B) are diagrams showing a data format of mouse data.

77A and 77B are diagrams for explaining the relationship between the CPU, the bus, and the bridge circuit.

78A is a diagram showing a configuration in the case where a sub controller is provided over the CPU bus, and FIG.
(B) is a diagram showing a configuration in the case where a sub-controller is provided only on the PCI bus.

79 (A) is a diagram showing a mounting method of an option board, and FIG. 79 (B) is a diagram showing an example of a configuration of a first sub-controller.

FIG. 80 is a flowchart showing the operation of the eighth embodiment immediately after reset.

81 (A) to (C) are the eighth diagrams immediately after resetting.
6 is a detailed flowchart, a memory map, and a signal waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 82 is a diagram showing an example of a circuit configuration of CPU interface means.

FIG. 83 is a flowchart showing the operation of the eighth embodiment.

FIG. 84 is a flow chart showing the operation of the eighth embodiment.

FIG. 85 is a signal waveform diagram representing an operation of the eighth embodiment.

FIG. 86 is a diagram showing an example of the configuration of the ninth embodiment.

FIG. 87 is a diagram showing an example of a configuration of CPU interface means.

88 is a signal waveform diagram showing an operation of the ninth embodiment. FIG.

89 (A) to (E) are diagrams showing various configurations of the first option board.

[Explanation of symbols]

 1 CPU 3 cache memory 5 CPU bus 7 HOLD signal 8 RESET signal 9 INIT signal 11 memory controller 12 hold weight control 13 cache controller 14 reset register 15 RAM controller 17 memory setting register 19 PCI bus interface 21 RAM 23 PCI bus 25 sub-controller 26 SMM handler 27 SMI generating means 28 SMI status 29 Mask register 30 I / O receiving means 31 SMI signal 33 VRAM 35 VRAM switching means 37 HDD 39 Bridge circuit 41 Conventional bus 43 ROM 45 ROM switching means 47 FDD 48 Keyboard controller 49 Keyboard 50 Serial Controller 52 RS232C interface 54 Interrupt controller 55 keyboard unit controller 60 switch means 62 decoder 1 64 decoder 2 66 ROM body 70 bus arbiter 71 PCI bus interface 73 reset detection means 74 speed switching means 75 power failure detection means 76 display switching detection means 80 application program 82 OS 84 hardware 86 emulation means 88 hardware change part 100 sub controller 104 instruction conversion means 120 decoder 124 address conversion part 126 data conversion part 128 BE latch register (R-Be) 130 address latch 132 address latch register (R-Adr) 134 conversion address latch 136 Data Latch Register (R-Data) 138 Conversion Data Latch 300 Sub Controller 326 Extended Slot To box 310 SIO 350 instruction conversion means 370 microcode memory 392 keyboard / mouse controller 414 first register 416 second register 417 timer 420 first option board 422 first socket 424 first sub-controller 426 main board 428 second 2 socket 430 2nd option board 431 2nd sub-controller 440 CPU bus interface means 442 Command conversion means 450 1st option board 452 1st sub-controller 454 CPU interface means 460 2nd option board 462 2nd Sub-controller 464 Command conversion means 902 Timing circuit 927 SMI generation means 928 SMI status 929 SMI mask means 930 I / O reception means 970 Bus arbiter 971 PCI bus interface 973 Reset detection means 974 Speed switching means 975 Power interruption detection means 976 Display switching detection means

Claims (54)

[Claims] 1. A first device in which, when the central control means issues an instruction by an instruction system adapted to the first computer architecture, the instruction is controlled by the instruction system adapted to the first computer architecture. Control means or means for transmitting the control target, and when the central control means issues an instruction according to an instruction system adapted to a second computer architecture different from the first computer architecture, the central control means receives the instruction At least means for analyzing the instruction, means for setting factor data indicating the type of the instruction and generating an interrupt to the central control means, and a predetermined process activated by the interrupt and corresponding to the factor, The first device control means or means for executing the control target The control mode of the central control means is shifted to a control mode managed by a predetermined system by the interrupt, and data necessary for the predetermined processing is stored in a memory area dedicated to the control mode. And emulation system. 2. The emulation system according to claim 1, wherein a position of an address in the memory area where data necessary for the predetermined processing is stored can be changed only in the control mode. . 3. A first device controlled by the instruction system adapted to the first computer architecture, when the central control means issues the instruction according to the instruction system adapted to the first computer architecture. Control means or means for transmitting the control target, and when the central control means issues an instruction according to an instruction system adapted to a second computer architecture different from the first computer architecture, the central control means receives the instruction At least means for analyzing the instruction, means for setting factor data indicating the type of the instruction and generating an interrupt to the central control means, and a predetermined process activated by the interrupt and corresponding to the factor, The first device control means or means for executing the control target The control mode of the central control means is shifted to a control mode managed by a predetermined system by the interrupt, the content of the internal register of the central control means is stored in a memory area dedicated to the control mode, and the control is performed. An emulation system, characterized in that upon termination of the mode, the contents of the stored internal register are returned to said central control means. 4. The emulation system according to claim 3, wherein a position of an address where the contents of the internal register are stored in the memory area can be changed only in the control mode. 5. When the central control means issues an instruction by an instruction system compatible with the first computer architecture, the first device is controlled by the instruction system compatible with the first computer architecture. Control means or means for transmitting the control target, and when the central control means issues an instruction according to an instruction system adapted to a second computer architecture different from the first computer architecture, the central control means receives the instruction At least means for analyzing the instruction, means for setting factor data indicating the type of the instruction and generating an interrupt to the central control means, and a predetermined process activated by the interrupt and corresponding to the factor, The first device control means or means for executing the control target The control mode of the central control means is shifted to a control mode managed by a predetermined system by the interrupt, and the predetermined processing by the execution means is performed by an instruction system that does not depend on the control mode of the central control means before the interruption. An emulation system characterized by being exposed. 6. A first device controlled by the instruction system adapted to the first computer architecture, when the central control means issues the instruction according to the instruction system adapted to the first computer architecture. Control means or means for transmitting the control target, and when the central control means issues an instruction according to an instruction system adapted to a second computer architecture different from the first computer architecture, the central control means receives the instruction At least means for analyzing the instruction, means for setting factor data indicating the type of the instruction and generating an interrupt to the central control means, and a predetermined process activated by the interrupt and corresponding to the factor, The first device control means or means for executing the control target An emulation system, characterized in that the interrupt is an SMI interrupt for shifting the central control means to an SMM mode. 7. The memory map according to claim 1, further comprising means for controlling a memory device as the first device control means, the memory map of the memory device being adapted to the second computer architecture. An emulation system including means for converting to. 8. When the central control means issues an instruction by an instruction system compatible with the first computer architecture, the first device is controlled by the instruction system compatible with the first computer architecture. Control means or means for transmitting the control target, and when the central control means issues an instruction according to an instruction system adapted to a second computer architecture different from the first computer architecture, the central control means receives the instruction A means for analyzing the instruction; a means for setting factor data indicating the type of the instruction when the instruction is analyzed as a first type instruction and generating an interrupt for the central control means; A predetermined process corresponding to the factor is activated by an interrupt, and at least the first device control is performed. Control means or means for executing the controlled object, and if the instruction is analyzed as the second type instruction, the instruction is converted so as to be compatible with the first computer architecture, and the central control means And a means for issuing a converted command instead of the central control means. 9. The method according to claim 8, wherein the instruction is the read instruction of the second type,
The processing of the central control means is interrupted to prohibit the bus access of the central control means, the converted instruction is issued on behalf of the central control means, and the obtained data is centralized when the processing is re-executed by the central control means. An emulation system comprising means for transmitting to a control means. 10. The method according to claim 8, wherein the instruction is the read instruction of the first type,
A means for changing the contents of the internal register of the central control means stored in a predetermined memory area based on the data obtained by the predetermined processing; and an end of the control mode transferred to the central control means by the interrupt. And a means for returning the changed contents of the internal register to the central control means. 11. The instruction according to claim 8 or 9, further comprising means for controlling an interface for data transmission / reception as the first device control means, and the instruction issued by the central control means is a data transmission / reception instruction. Alternatively, when it is a status read command, the emulation system is characterized in that the command is analyzed as the second type command and conversion processing of the command is performed. 12. The device according to claim 8, further comprising means for controlling an interface for data transmission / reception as the first device control means, wherein when the instruction issued by the central control means is a command write instruction. An emulation system characterized in that an instruction is analyzed as the first type instruction, and the conversion processing of the instruction is performed by the predetermined processing of the execution means. 13. The device according to claim 8, further comprising means for controlling an interface for data transmission / reception as the first device control means, and the instruction issued by the central control means sets a baud rate for data transfer. If the command is the command, the command is issued as the first command.
The emulation system is characterized in that it is analyzed as an instruction of the type, and the baud rate is calculated by the predetermined processing of the execution means. 14. The method according to claim 8, further comprising a means for controlling a data input means as the first device control means, and the instruction issued by the central control means is a command transmission instruction or a command write instruction. Alternatively, when it is a data reception command, the command is analyzed as the command of the first type, and the conversion process of the command is performed by the predetermined process of the execution means. 15. The method according to claim 8 or 9, further comprising means for controlling a data input means as the first device control means, and the instruction issued by the central control means is a status read instruction. The emulation system characterized in that the instruction is analyzed as the second type instruction and conversion processing of the instruction is performed. 16. The vector conversion unit according to claim 8, further comprising a unit for controlling an interrupt as the first device control unit, for converting an interrupt vector issued to the central control unit. An emulation system characterized by including. 17. The central control means according to claim 8, further comprising means for controlling an interrupt as the first device control means, wherein the central control means is operable to issue an interrupt acknowledge command when the central control means issues an interrupt acknowledge command. It includes means for interrupting the processing, prohibiting the bus access of the central control means, newly generating an interrupt acknowledge cycle, and transmitting the converted interrupt vector to the central control means when the central control means re-executes the processing. Characterized emulation system. 18. A sub-controller connected to the first bus and including means for converting instructions issued by the central control means adapted to the second computer architecture into instructions adapted to the first computer architecture, A bridge circuit for connecting the first bus and the second bus, wherein the sub-controller controls a control signal of the first bus input to the bridge circuit, whereby the second bus When a command adapted to the computer architecture is issued, the device further includes means for invalidating the transmission of the command to the first device control means connected to the second bus or its control target. And emulation system. 19. A sub-controller connected to the first bus and including means for converting instructions issued by the central control means adapted to the second computer architecture into instructions adapted to the first computer architecture; A second bus connected to the first bus and controlled by an instruction system adapted to the second computer architecture;
The sub-controller controls a control signal of the first bus input to the second device control means, so that an instruction conforming to the first computer architecture is issued. If the instruction is transmitted, the transmission of the instruction to the second device control unit or its control target is disabled, and the second device is issued when the instruction conforming to the second computer architecture is issued. An emulation system comprising a control means or means for transmitting the command to a control target thereof. 20. A sub-controller connected to the first bus and including means for converting instructions issued by the central control means adapted to the second computer architecture into instructions adapted to the first computer architecture; A first expansion slot connectable to the first bus, and a first expansion slot insertable into the first expansion slot for controlling signals on the first bus controlled by instructions compatible with a second computer architecture; A board having means for converting into a signal of two buses, and an expansion slot box including one or a plurality of second expansion slots connectable to the second bus and connected to the board via a cable. An emulation system characterized by that. 21. An emulation system for converting an instruction into an instruction conforming to a first computer architecture when the central control means issues an instruction by an instruction system conforming to a second computer architecture, the emulation system comprising: A microcode memory that stores at least the command information and microcode information including emulation address information at the position of the memory address, address information included in the instruction issued by the central control means, and the microcode memory included in the microcode memory. Selector means for selecting any one of the emulation address information and generating the memory address, wherein when the selector means is instructed to continue the emulation based on the emulation continuation information included in the command information, An emulation system which selects emulation address information and generates the memory address. 22. A data generating means for generating emulation data based on microcode information from the microcode memory according to claim 21, wherein the data generating means generates emulation data based on the emulation continuation information. If you are instructed to continue,
Write data from the central control means or nth (n is 1)
An emulation system characterized by performing emulation data generation processing in the (n + 1) th emulation based on the emulation data generated by the above (integer) emulation. 23. An emulation system for converting an instruction into an instruction conforming to a first computer architecture when the central control means issues the instruction by an instruction system conforming to a second computer architecture, the emulation system comprising: A microcode memory for storing microcode information for conversion at a predetermined memory address position, a unit for reading the microcode information from the microcode memory, and generation of emulation data based on the read microcode information Data generating means for performing processing, wherein the microcode memory stores first microcode information including at least command information and emulation address information at a position of the first memory address, and stores the first memory address. Obtained by converting The second microcode information including at least a part or all of the data generation information is stored at the position of the second memory address, and the read means stores at the position of the first memory address by the first memory read cycle. When the command information is read out and it is determined based on the command information that the data generating process by the data generating means is necessary, the second memory read cycle is activated to save the second memory address of the second memory address. The data generation information stored in a position is read, and the data generation means reads the first microcode information read in the first memory read cycle and the second microcode read information in the second memory read cycle. An emulation system characterized by performing the data generation process based on second microcode information. Temu. 24. The data generation information according to claim 23, including bit definition information, and the data generation means defines a value of each bit of emulation data based on the bit definition information and performs the data generation process. An emulation system characterized by that. 25. The method according to claim 23, wherein the first microcode information includes a predetermined number of bits of data, and the command information outputs the predetermined number of bits of data as emulation data. An emulation system characterized by including instructing information. 26. The emulation system according to any one of claims 23 to 25, wherein the command information includes information indicating that only an address conversion process is performed and data conversion is not performed. 27. The address decoding unit according to claim 21, further comprising an address decoding unit that decodes address information included in an instruction issued by the central control unit to obtain the memory address. When the address information included in the instruction issued by the central control means is the same,
An emulation system including means for obtaining a different memory address from the same address information. 28. When the central control means issues an instruction according to an instruction system adapted to the second computer architecture, the instruction is converted into an instruction adapted to the first computer architecture, and the first computer architecture. Controlled by a command system adapted to
Of the device control means or its control target, wherein the first device control means generates a first interrupt to notify the central control means of a command issuance request. In this case, when the first interrupt is generated, it receives the interrupt, sets factor data indicating the type of instruction, and generates a second interrupt to the central control means, Execution means that is activated by an interrupt, executes a predetermined process corresponding to the factor, and sets a state in which an instruction suitable for the first device control means or the control target thereof can be issued in accordance with the second computer architecture; A means for generating the first interrupt and notifying a request for issuing an instruction to the central control means. Rate system. 29. The keyboard controller as the first device control means according to claim 28, wherein the predetermined processing by the execution means converts input data from the keyboard using a data conversion table, An emulation system, characterized in that the control means stores the converted data in a readable storage means. 30. The mouse controller according to claim 28, further comprising a mouse controller as the first device control means, wherein the predetermined processing by the execution means adapts input data from a mouse to a second computer architecture. An emulation system, which is a process of converting the data into readable data by an instruction and storing the converted data in a readable storage unit by the central control unit. 31. A central control means includes a first sub-controller connected to a first bus to which the central control means is directly connected, said first sub-controller being centrally controlled by an instruction system adapted to a second computer architecture. A central control unit for invalidating the transmission of the command to the first device control unit controlled by the command system adapted to the first computer architecture or its control target when the unit issues the command; Means for converting the instruction issued from the means into an instruction compatible with the first computer architecture, and transmitting the converted instruction to the first device control means or its control target. And emulation system. 32. The means for transmitting an instruction according to claim 31, wherein the processing of the central control means is interrupted by controlling the input signal of the central control means and then re-executed, and the converted instruction is obtained. An emulation system including means for transmitting data or a control signal from the first device control means during the re-execution. 33. The second bus according to claim 31, which is connected to a second bus different from the first bus.
An emulation system, wherein the second sub-controller includes second device control means controlled by an instruction system adapted to the second computer architecture. 34. A first sub-controller connected to a first bus to which the central control means is directly connected, and a second sub-controller connected to a second bus different from the first bus. And the first sub-controller is controlled by the instruction system adapted to the first computer architecture when the central control means issues the instruction by the instruction system adapted to the second computer architecture. An instruction that includes a first device control unit or a unit that converts the control target into an instruction that cannot be accepted, wherein the second sub-controller issues the instruction issued from the central control unit to the first computer architecture. And means for transmitting the converted command to the first device control means or its control target. Emulate a system that. 35. The conversion processing to an instruction in which the first device control means or its control target is not accepted according to claim 34, wherein information of an address included in the instruction from the central control means is changed to the first information. An emulation system characterized by a process of converting to an address which is not used by a device control means or its control target. 36. The means for transmitting the command according to claim 34 or 35, wherein the processing of the central control means is interrupted by controlling the signal of the second bus and then re-executed to be converted. An emulation system including means for transmitting data obtained by the command or a control signal from the first device control means at the time of the re-execution. 37. The device according to any one of claims 34 to 36, wherein the second sub-controller includes second device control means controlled by an instruction system adapted to the second computer architecture. Emulation system to do. 38. The emulation system according to claim 34, further comprising means for transmitting an interrupt signal from the second sub-controller to the central control means. 39. The method according to any one of claims 31 to 38, wherein when the first sub-controller has the instruction issued from the central control means that conforms to the first computer architecture. An emulation system comprising a first device control means or means for transmitting the command to a control target thereof. 40. The method according to any one of claims 31 to 39, wherein the first sub-controller is a means for controlling a memory device or a control target of the instruction issued from the central control means. The emulation system includes means for delaying the control start signal of the first bus generated by the central control means for making the above judgment. 41. The means according to any one of claims 31 to 40, which, after resetting or power-on, boots a BIOS compatible with the second computer architecture with priority over a BIOS compatible with the first computer architecture. Means for switching the mode selection of whether the instruction issued from the central control means is transmitted without conversion or converted into an instruction compatible with the first computer architecture and transmitted, based on an instruction from the data input means. Characterized emulation system. 42. A first board having at least a first sub-controller for emulating an instruction issued by the central control means, the first board comprising: a first terminal of the central control means. First connecting means for connecting the group to a first terminal group of the second socket of a third board having at least a second socket to which the central control means can be attached; An emulation system comprising: a second connection group for connecting a second terminal group and a second terminal group of the second socket via the first sub-controller. 43. The plurality of pins according to claim 42, wherein the first board is insertable into a plurality of pin holes provided in the first socket to which the central control means can be mounted and the second socket. An emulation system, comprising: a connection connector having a connector; and a wiring means for connecting the terminal of the first socket, the terminal of the sub-controller, and the terminal of the connection connector. 44. The first board according to claim 42, wherein the first control means, a connection connector having a plurality of pins insertable into a plurality of pin holes provided in the second socket, and the center. An emulation system comprising: wiring means for connecting the terminals of the control means, the terminals of the sub-controller, and the terminals of the connection connector. 45. The second sub-controller according to claim 42, further comprising at least a second sub-controller for performing the emulation processing together with the first sub-controller. An emulation system including a second board attachable to an expansion slot capable of transmitting a signal to and from a terminal of the socket. 46. The signal line of claim 45, further comprising a signal line for transmitting a signal between the first board and the second board, wherein the signal is the second line on the second board. An emulation system including an interrupt signal generated from two sub-controllers to the central control means on the first board. 47. (A) When the central control means issues an instruction by an instruction system adapted to the first computer architecture, the instruction is controlled by the instruction system adapted to the first computer architecture. A step of transmitting the instruction to one device control means or its control target; and (B) when the central control means issues an instruction by an instruction system adapted to a second computer architecture different from the first computer architecture. Receiving the instruction and analyzing the instruction, (C) setting factor data indicating the type of the instruction and generating an interrupt to the central control means, (D) activated by the interrupt A predetermined process corresponding to the factor, at least the first device control means or Of the control target of the central control means is transferred to the control mode managed by a predetermined system by the interrupt activated in step (D). An emulation method characterized in that data necessary for the predetermined processing is stored in a memory area. (A) When the central control means issues an instruction by an instruction system adapted to the first computer architecture, the instruction is controlled by the instruction system adapted to the first computer architecture. A step of transmitting the instruction to one device control means or its control target; and (B) when the central control means issues an instruction by an instruction system adapted to a second computer architecture different from the first computer architecture. Receiving the instruction and analyzing the instruction, (C) setting factor data indicating the type of the instruction and generating an interrupt to the central control means, (D) activated by the interrupt A predetermined process corresponding to the factor, at least the first device control means or And a step of executing the control target of the central control means by the interrupt activated in step (D), and the control mode of the central control means is shifted to a control mode managed by a predetermined system. The emulation method is characterized in that the content of the internal register of the central control means is stored in the area, and the stored content of the internal register is returned to the central control means when the control mode ends. (A) When the central control means issues an instruction by an instruction system adapted to the first computer architecture, the instruction is controlled by the instruction system adapted to the first computer architecture. A step of transmitting the instruction to one device control means or its control target; and (B) when the central control means issues an instruction by an instruction system adapted to a second computer architecture different from the first computer architecture. Receiving the instruction and analyzing the instruction, and (C) setting factor data indicating the type of the instruction when the instruction is analyzed as the first type instruction, and for the central control means. Generating an interrupt, and (D) a predetermined process that is activated by the interrupt and corresponds to the cause. To at least the first device control means or its controlled object, and (E) conforms to the first computer architecture when the instruction is analyzed as a second type instruction. And converting the instruction to prohibit bus access of the central control unit and issuing the converted instruction on behalf of the central control unit. 50. An emulation method for converting an instruction into an instruction compatible with a first computer architecture when the central control means issues the instruction by an instruction system compatible with the second computer architecture,
(A) From a microcode memory storing microcode information including at least command information and emulation address information at a position of an input memory address,
Reading the microcode information, and (B) selecting one of the address information included in the instruction issued by the central control means and the emulation address information read from the microcode memory to select the memory address. Generating the memory address by selecting the emulation address information when the continuation of the emulation is instructed based on the emulation continuation information included in the command information in the step (B). Emulation method characterized by. 51. An emulation method for converting an instruction into an instruction compatible with a first computer architecture when the central control means issues the instruction by an instruction system compatible with the second computer architecture,
(A) First microcode information stored at a first memory address position of the microcode memory and including at least command information and emulation address information,
A step of reading by activating a first memory read cycle; and (B) activating a second memory read cycle if it is determined based on the command information that generation processing of emulation data is necessary, A second obtained by converting the first memory address
Reading the second microcode information stored at the memory address position and including a part or all of the data generation information; and (C) the first microcode information read in the first memory read cycle. And the second
Emulation data generation processing is performed based on the second microcode information read in the memory read cycle of. 52. When the central control means issues an instruction by an instruction system adapted to the second computer architecture, the instruction is converted into an instruction adapted to the first computer architecture, and the first computer architecture. Controlled by a command system adapted to
(A) The first device control means generates a first interrupt to send an instruction issuance request to the central control means. In case of notification
Receiving the interrupt when the first interrupt is generated, setting factor data indicating the type of instruction, and generating a second interrupt to the central control means, and (B) the second interrupt A step of being activated by an interrupt, executing a predetermined process corresponding to the factor, and setting a state in which an instruction conforming to the second computer architecture can be issued to the first device control unit or its control target; (C) a step of generating the first interrupt and notifying a request to issue an instruction to the central control means. 53. An emulation method used in an information processing apparatus including a first sub-controller connected to a first bus to which a central control means is directly connected, comprising: (A)
When the central control means issues an instruction by the instruction system adapted to the second computer architecture, the first device control means controlled by the instruction system adapted to the first computer architecture or its control target Disabling the transmission of commands, (B)
Converting the instruction issued from the central control means into an instruction compatible with the first computer architecture, and transmitting the converted instruction to the first device control means or its control target. Emulation method characterized by. 54. A first sub-controller connected to a first bus to which the central control means is directly connected, and a second sub-controller connected to a second bus different from the first bus. An emulation method used in an information processing apparatus including: (A) when a central control means issues an instruction by an instruction system adapted to the second computer architecture, the instruction is transmitted to the first computer architecture. A step of converting the first device control means controlled by an adapted instruction system or a control target thereof into an instruction that cannot be accepted; and (B) adapting the instruction issued from the central control means to the first computer architecture. And converting the converted instruction to the first device control means or its control target. Characterized emulation method.