JPH07326670A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To ensure a high speed operation of an integrated circuit, keeping high integration by resducing wiring capacitance among multi-layered wirings formed in a semiconductor integrated circuit, and narrowing an interval between the adjacent wirings. CONSTITUTION: An insulating film 3 is deposited on a wiring layer under conditions where a gap 4 can be produced between finely processed adjacent wirings, and a gap of low dielectric is permitted to be existent between the adjacent wirings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a narrow gap between metal wirings.

[0002]

2. Description of the Related Art For example, a state of a conventional metal wiring is shown in FIG. The semiconductor substrate 11 is made of single crystal silicon, an insulating layer 12 of silicon oxide is formed on the surface thereof, and a lower layer metal wiring 13 is patterned on the surface thereof. A semiconductor integrated circuit having the silicon oxide films 14 and 16 functioning as an interlayer insulating film of the lower metal wiring and the upper metal wiring 17 and the SOG film 15 contributing to the flattening of the insulating film is a prior art. Conceivable. For example, Japanese Patent Laid-Open No. 5-218028 and the like are publications relating to multilayer wiring.

[0003]

In many of the conventional multilayer wiring structures, the relative permittivity of the silicon oxide film 14 is about 4, and the spacing between the lower layer metal wirings 13 is increased as the circuit becomes highly integrated. In recent semiconductor devices having a size of 1 micron or less, the capacitance between wirings increases, so that the electrical characteristics of the semiconductor integrated circuit device are beginning to be adversely affected, especially by delaying the propagation speed of electrical signals.

However, in the above-mentioned prior art, when determining the film thickness and material of the interlayer insulating film, alpha rays and flatness are taken into consideration, but in order to reduce the wiring capacitance between the adjacent metal wirings. As for measures, sufficient measures were not taken.

Further, in order to avoid the delay of the propagation speed of the electric signal, the allowable interval between the predetermined wirings and the allowable range of the threshold voltage of the MOS transistor are narrowed. As a result, a certain limit occurs in the manufacturing process of the semiconductor integrated circuit. Has reached.

The present invention has been made in view of the above problems, and its purpose is to provide a metal or single crystal silicon.
It is an object of the present invention to provide a technique capable of effectively reducing the wiring capacitance between wirings made of strips.

Another object of the present invention is to provide a technique capable of improving the operating speed of a semiconductor integrated circuit device. Another object of the present invention is to provide a technique capable of relaxing restrictions on the manufacturing process of a semiconductor integrated circuit device. The novel structure and effect of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below.

According to the semiconductor device of the present invention, the gap between the metal wirings to be miniaturized has a very small relative dielectric constant of about 1, so that the capacitance between the metal wirings can be reduced and the electrical characteristics of the integrated circuit can be reduced. It is intended to improve the characteristics. Specifically, in a wiring process of a semiconductor device, fine metal wirings are formed, and voids are formed between adjacent metal wirings by using a CVD method or a sputtering method between grooves between the metal wirings. An insulating film is formed under the conditions. Furthermore, if a material having a relative dielectric constant of the insulating film lower than that of the silicon oxide film, for example, a polyimide resin is selected, it is possible to further reduce the capacitance between the metal wirings.

[0010]

According to the above invention, by arranging the void having a low dielectric constant between the adjacent wirings, the dielectric constant between the wirings can be effectively reduced. Furthermore, it is possible to improve the yield by integrating the semiconductor device without lowering the reliability of the circuit and the wiring layer formed on the void.

As a result, the time required for the electric signal to charge or discharge the metal wiring can be shortened as compared with the conventional case, so that the propagation speed of the electric signal can be increased.

[0012]

1 to 4 show a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. The metal wiring for the semiconductor integrated circuit of this embodiment is a finely processed DRA.
It can be applied to M, MPU, mask ROM, gate array, etc.

First, FIG. 1 shows a mode in which an insulating film 1 is formed on a semiconductor substrate, and a metal wiring 2 is patterned on the insulating film 1. For example, in the present embodiment, the space between the metal wirings is 0.04 μm in the case of 64 MDRAM and 0.025 μm in the case of 256 mDRAM.
Can be patterned. However, if the wiring density is not severe, it is not necessary to particularly provide a low dielectric void. FIG. 2 shows a mode in which the insulating film 3 is then deposited on the metal wiring 2 and the insulating film substrate 1 by using the CVD method. At this time, the insulating film 3 is deposited under the condition that it is deposited along the upper corner of the metal wiring 1. In Figure 3,
When the films are deposited under this condition, the films on the adjacent metal wirings are brought into contact with each other before the grooves between the adjacent wirings are filled with the insulating film, and the voids 4 are formed. At this time, a void having a relative dielectric constant of about 1 can be formed, and a means for reducing the capacitance between adjacent wirings can be provided. FIG. 4 shows a step of forming a metal wiring 5 after forming a contact hole (see FIG. 9) for connecting the metal wiring 1 and the metal wiring 2. If the insulating film 3 has a low dielectric constant, the capacitance between the metal wiring 2 and the metal wiring 5 can be reduced.
Examples of the CVD method include a method of reacting monosilane and oxygen to form silicon oxide, a method of adding SiF ₄ or C ₂ F ₆ to ordinary TEOS-CVD to dope fluorine into a silicon oxide film, and a CVD method. There is a method of depositing a polyimide insulating film.

5 to 8 are sectional views in order of the steps of a semiconductor integrated circuit device according to the second embodiment of the present invention.

First, in FIG. 5, a metal wiring 2 is formed on the insulating film 1.
6 is a cross-sectional view in which the insulating film 6 is deposited on the metal wiring 2 and the insulating film 1 by a sputtering method, and FIG. The film can be deposited under conditions such that a conformal film is deposited. FIG. 7 is a process cross-sectional view in which the films on the adjacent metal wirings are in contact with each other before the trenches between the adjacent wirings are filled with the insulating film and the voids 4 are formed when the films are deposited under this condition. At this time, the capacitance between adjacent wirings can be reduced by forming a void having a relative dielectric constant of about 1. In FIG. 8, after forming contact holes (see FIG. 9) for connecting the lower metal wiring 2 and the upper metal wiring 5,
The sectional view which formed the metal wiring 5 is shown. If the insulating film 3 has a low dielectric constant, the metal wiring 2 and the metal wiring 5
The capacity between and can also be reduced. At this time, a silicon oxide film, a silicon oxide film (SiOF) doped with fluorine, polyimide, polytetrafluoroethylene (PTFE), or the like can be appropriately selected and used as the film to be sputtered.

In addition to the above-mentioned fluorine-containing silicon oxide, the insulating film may be formed of a low dielectric constant material such as silicon oxide containing an organic substance or Teflon. FIG. 9 shows a cross section of a main part of a semiconductor memory according to another embodiment of the present invention. Although the above embodiment has described the mode of reducing the capacitance between the lower metal wirings, this embodiment is applied to the DRAM using the three-layer metal wiring. That is, using the same process as in the above embodiment, first, the first level B / L 20 made of tungsten which is a refractory metal is formed, and then the second level Y select line 5 made of tungsten is formed. Finally, by forming W / L2 having a laminated structure of aluminum and titanium nitride, the capacitance between the metal wirings at the same level is reduced by the voids 4, 4 ′, 4 ″, and the upper or lower layer is formed. The capacitance between the metal wirings can be reduced by the interlayer insulating films 1, 3, and 6. It goes without saying that the capacitance between the memory cell plate electrode and the metal wiring can also be reduced by the interlayer insulating film. In particular, since no radioactive substance that emits alpha rays contained in the material can exist in the void portion 4, it has an adverse effect on the charge storage node 22 of the DRAM capacitor. It is advantageous in that there is no possibility that occur.

Furthermore, if the height of the void is made higher than the thickness of the metal wiring, the wiring capacitance can be further reduced. In this case, each patterned metal wiring 2, 5, 2
After the insulating layers 6, 3, 1 existing between 0 are etched back to dig a groove deeply, a low dielectric constant material is deposited in the same manner as in the above process to increase the thickness of the metal wiring to a larger void. Is formed.

In the above description, the case where the present invention is mainly applied to the metal wiring of the DRAM has been described, but the present invention is not limited to this and, for example, SRAM, EEPROM, EPROM,
It can also be applied to a semiconductor integrated circuit device having multi-layer wiring such as a microprocessor.

[0019]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows. That is, by forming a void having a very small relative dielectric constant (about 1) between the metal wirings to be thinned, the capacitance between the metal wirings can be reduced. Specifically, a conformal (c) is formed on the upper corner of the metal wiring of the adjacent wiring by CVD or sputtering.
If a film is deposited under such a condition that an (normal) film is deposited, a groove between adjacent wirings can be brought into contact with each other before being filled with an insulating film, and a void can be formed, and a wiring of a semiconductor integrated circuit device can be formed. It is possible to reduce the capacitance between them.
Therefore, it is possible to improve the electrical characteristics such as the operating speed of the integrated circuit.

If the film deposited by the CVD method or the sputtering method has a low dielectric constant, the capacitance between the wirings can be further reduced, and the capacitance with the upper metal wiring can be reduced at the same time. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a metal wiring for a semiconductor integrated circuit that is a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a wiring process which is the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a void portion between wirings, which is the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of upper and lower wirings for a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a sectional view of metal wiring for a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view of a wiring process which is a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a void portion between wirings, which is a second embodiment of the present invention.

FIG. 8 is a cross-sectional view of essential parts of upper and lower wirings for a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 9 is a combination of front and rear sectional views of a main part of a dynamic semiconductor memory according to another embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional multilayer wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating film substrate 2 Metal wiring 3 Insulating film deposited by CVD method 4 Void portion 5 Metal wiring 6 Insulating film deposited by sputtering method 11 Single crystal silicon 12 Silicon oxide 13 Lower metal wiring 14 Silicon oxide 15 SOG film 16 Oxidation Silicon 17 Upper layer metal wiring 19 Source / drain 20 Tungsten wiring layer 21 Capacitor plate electrode 22 Charge storage node 30 Word line

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Claims (5)

[Claims] 1. An interconnect for forming a semiconductor integrated circuit formed on a semiconductor substrate, comprising: a plurality of metal interconnects; and a low dielectric constant void located in a groove between the metal interconnects.
A semiconductor integrated circuit device including an insulating film deposited on the void and the metal wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is deposited by a CVD method. 3. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is deposited by a sputtering method. 4. The semiconductor integrated circuit device according to claim 1, wherein the relative dielectric constant of the insulating film is lower than the relative dielectric constant of the silicon oxide film. 5. The insulating film comprises silicon oxide containing fluorine, silicon oxide containing organic matter, polyimide,
2. A semiconductor integrated circuit device according to claim 1, wherein one of low-dielectric materials such as Teflon is selected, or these materials are included.