JPH07321076A - Manufacture of semiconductor device and abrasive device - Google Patents

Abstract

PURPOSE:To lessen a difference between the abrasive wears of the peripheral part and the central part of a wafer to conduct a flattening of the peripheral part and the central part and to prevent the generation of a short-circuit between wirings by a method wherein grooves are provided in an abrasive cloth adhered on the platen of an abrasive device in a radial form from the center of the cloth for improving the drainage of an abrasive liquid. CONSTITUTION:The structure of an abrasive cloth is constituted of a several mm-thick polyurethane 11 and about 1mm-thick abrasive pads 12 adhered oh the surface of the polyurethane 11. The fan-shaped abrasive pads 12 are adhered on the surface of the polyurethane 11. Intervals of 2mm or thereabouts are respectively provided between the pads 12 so that an abrasive liquid flows well, whereby grooves 13 are provided in the abrasive cloth in a radial form from the center of the abrasive cloth. Thereby, the abrasive liquid flows from the central part of a platen to the outer periphery of the platen via the grooves provided in the abrasive cloth by a centrifugal force which is generated by the rotation of the platen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a polishing apparatus, and more particularly to a semiconductor device manufacturing method and a polishing apparatus which require a planarization technique.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor elements and multi-layering of wiring formed in the elements have been advanced. Therefore, it is required to improve the planarization technique in order to planarize the surface of a semiconductor substrate (hereinafter referred to as a wafer) and promote miniaturization and multilayer wiring. In this planarization technology, CMP (Chemical and M
The echanical Polishing method is regarded as an effective technique in terms of its effect and cost. The CMP method is a method of polishing a material to be polished by chemically imparting the ability to chemically etch the material to be polished, and mechanically polishing the material to be polished by particles contained in the polishing liquid.

Next, the structure of the polishing apparatus used in the CMP method will be described with reference to FIG. The polishing apparatus has a polishing table, a wafer holding part for fixing a wafer, and a part for supplying a polishing liquid. The polishing table has a platen 101 (a surface plate) and a polishing cloth 102 attached on the surface thereof. Further, the wafer holder fixes the wafer by sucking the wafer 104 through the vacuum hole 103. The portion for supplying the polishing liquid has a slurry nozzle 105 and a pure water nozzle 106.

The wafer flattening step is performed by rotating both the wafer holder and the platen, lowering the wafer holder, and bringing the surface of the wafer into contact with the polishing cloth on the platen and applying pressure thereto. In this step, it is important to consider the surface condition of the wafer and optimize the balance between the etching amount of chemical polishing and the pressure of mechanical polishing. The amount of chemical polishing is determined by conditions such as the type of polishing liquid, pH and composition. The amount of mechanical polishing is determined by conditions such as the type and concentration of particles contained in the polishing liquid, polishing cloth, pressure, rotation speed, rotation direction and the like.

However, it is not easy to control the above conditions, and the polishing amount varies between wafers or within the same wafer. In particular, the variation in the polishing amount within the same wafer is that the polishing amount is large in the central portion of the wafer. The cause is that the polishing liquid easily accumulates in the central portion of the wafer, and therefore the polishing amount in the central portion of the wafer is large. This is because the central part of the wafer is rapidly polished due to the increase in the amount. There are few effective measures to prevent this, and its control is difficult. Therefore, the following problems arise in the manufacturing process of the semiconductor device.

First, as a first example, a case of applying the CMP method in the step of flattening the interlayer film in the step of manufacturing a semiconductor device will be described with reference to FIG. Figure 5
As shown in (a), the first interlayer film 152 is formed on the surface of the wafer 151, and in order to form the first wiring layer 153, an Al film of 6000 angstrom is formed and patterned. To do.

Subsequently, as shown in FIG. 5B, the Al film 1
A silicon oxide film having a film thickness of 10000 angstrom is formed as a second interlayer film 154 on the surface of 53 and the exposed surface of the first interlayer film 152. After this, CMP
Is used to planarize the second interlayer film.

In the central portion of the wafer after the flattening process, a large amount of polishing liquid is accumulated and the polishing amount is increased.
As shown in (c), the second interlayer film 153 on the first wiring layer 153 may be excessively polished and the surface of the first wiring layer 153 may be exposed.

When an Al film is formed on the surface as the second wiring layer 155 in this state, as shown in FIG. 5D, the first wiring layer 153 and the second wiring layer 15 are formed in the central portion of the wafer.
There is a problem that the first wiring layer and the second wiring layer are short-circuited by the contact of the wirings 5.

Even if the surface of the first wiring layer 153 is not exposed in the central portion of the wafer, the polishing amount of the second interlayer film 154 is different between the central portion and the peripheral portion of the wafer.
A difference occurs in the film thickness of the interlayer films 152 and 154 from the wafer 151. When a contact with the wafer 151 is to be formed in this state, it is difficult to control etching by the RIE method at the central portion and the peripheral portion of the wafer 151, and the interlayer films 152 and 154 have a thicker peripheral portion. At the same time, when etching is performed, the etching reaches the wafer 151 in the central portion where the interlayer films 152 and 154 are thin, and the wafer is damaged. On the contrary, the interlayer film 1
If etching is performed in accordance with the central portions of the thin films 52 and 154, it is difficult to form contacts having sufficient depth in the interlayer films 152 and 154 in the peripheral portions of the thick interlayer films 152 and 154. Becomes

As a second example, in the step of flattening the buried element isolation layer in the manufacturing process of the semiconductor device,
A case where the CMP method is applied will be described with reference to FIG. First, as shown in FIG. 6A, a polycrystalline silicon film 163 having a film thickness of 2000 angstroms is formed as a stopper film on the surface of the wafer 161 through an oxide film 162 having a film thickness of 500 angstroms to form an element isolation layer. The polycrystalline silicon film 163, the oxide film 162, on the planned formation region,
The wafer 161 is etched by the RIE (Reactive Ion Ecthing) method to form a trench 164 having a depth of about 6000 angstroms.

Subsequently, as shown in FIG. 6B, an oxide film 16 having a film thickness of 10000 angstrom is used as a filling material.
5 is formed in the trench and on the surface of the polycrystalline silicon film 163. After that, the oxide film 165 is planarized by the CMP method.

At the peripheral portion of the wafer where the flattening process is completed, the polycrystalline silicon film 163 which is a stopper film is left, and the flattening process is completed, but in the central portion of the wafer, as shown in FIG. In addition, since the polishing liquid is large and the polishing amount is large, the polycrystalline silicon film 163 may be completely polished and the wafer 161 may be polished.

If the semiconductor device is manufactured in this state as usual, the surface of the wafer is exposed at the central portion of the wafer during the etching for removing the polycrystalline silicon film 163 and the oxide film 162. , Wafer 161
Is damaged and damaged. Therefore, FIG.
As shown in (d), defects may occur and dislocations 167 may occur in the wafer in the central portion of the wafer, particularly in the boundary portion with the element isolation layer. When the ion implantation process for forming the impurity region 166 is performed, the dislocation 16
No. 7 has a problem of generating a junction leak current.

Therefore, in order to prevent the wafer 161 from being over-polished, a variation in the polishing amount between the central portion and the peripheral portion of the wafer is considered, and the larger the variation, the thicker the polycrystalline silicon film 163 becomes. There is a need.

However, when the polishing amounts of the polycrystalline silicon film 163 and the oxide film 162 are different between the central portion and the peripheral portion of the wafer 161, if these are removed, the periphery of the oxide film 165 formed as a buried element layer is removed. , A difference in height occurs between the central portion and the peripheral portion of the wafer 161. For example, when a conductive film such as WSi is deposited on the wafer 161 and is patterned, the conductive film remains on the side wall of the step in the peripheral portion of the wafer 161 where the step is high. Problems such as short circuit occur.

CM using the conventional polishing apparatus as described above
In the manufacturing process of the semiconductor device by the P method, a large amount of polishing liquid for polishing the material to be polished remains in the central portion of the wafer, and the polishing amount differs between the peripheral portion and the central portion of the wafer. Therefore, for example, when the step of flattening the interlayer film is performed, the interlayer film is excessively polished in the central portion of the wafer, and a short circuit occurs between wirings.
When forming a contact, the contact may not be formed to a sufficient depth, or conversely, the wafer may be etched.

Further, when the buried element isolation film is flattened, the wafer is polished in the central portion of the wafer, which causes dislocations in the wafer, and when an impurity region is formed, a junction leak due to the dislocation in the wafer causes a junction leak. When this occurs, or when the conductive film formed on the buried element layer is patterned, this conductive film may remain and a short circuit may occur.

[0019]

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a polishing apparatus that does not cause a difference in the polishing amount between the peripheral portion and the central portion of a wafer, and a short circuit between wirings using the polishing apparatus. Another object of the present invention is to provide a method for manufacturing a semiconductor device that prevents generation of a junction leak current due to dislocation.

[0020]

To achieve the above object, in the present invention, in order to prevent a large amount of polishing liquid from accumulating in the central portion of the wafer, a polishing cloth attached on the platen of the polishing apparatus is provided with a radial pattern. A structure is provided in which grooves are provided to improve the removal of the polishing liquid, and a difference in the polishing amount between the peripheral portion and the central portion of the wafer does not occur. At the same time, using this polishing apparatus, a step of flattening the interlayer film on the wafer and a step of flattening the embedded element isolation film are performed.

[0021]

According to the present invention, in a semiconductor device manufacturing process, when a polishing device is used to perform a flattening process of an interlayer film on a wafer or a flattening process of a buried element isolation film, a platen of the polishing device is used. By providing the polishing cloth to be adhered to the substrate with radial grooves in order to improve the brushing of the polishing liquid, the difference in the polishing amount between the peripheral portion and the central portion of the wafer can be reduced and planarization can be performed. Therefore, in the step of flattening the interlayer film, the interlayer film is not excessively polished, and a short circuit between wirings can be prevented. Further, in the step of flattening the element isolation film, the wafer is not polished, and it becomes possible to prevent the generation of junction leak due to the dislocation of the wafer. Further, it is possible to suppress variations in processing caused in subsequent steps due to variations in the residual film after polishing.

[0022]

Embodiments of the present invention will be described with reference to the drawings. First, a top view of the polishing cloth in the first embodiment of the polishing apparatus of the present invention is shown in FIG. 1 (a), and a lateral view thereof is shown in FIG. 1 (b). Further, the polishing apparatus other than the polishing cloth is the same as the conventional one, and the illustration is omitted. The material of the polishing cloth is the same as the conventional one.

The structure of the polishing cloth comprises a polyurethane 11 having a thickness of several mm and a polishing pad 12 having a thickness of about 1 mm attached to the surface of the polyurethane 11, and the surface of the polyurethane 11 has a central angle of 20 degrees of 16 degrees. 1 fan-shaped polishing pad
2 is attached. The fan-shaped polishing pads 12 are spaced from each other by about 2 mm so that the polishing liquid can be easily removed. Therefore, a total of 16 grooves 13 are provided radially from the center of the polishing cloth. As a result, the polishing liquid flows from the center of the platen to the outer circumference through the grooves between the polishing cloths due to the centrifugal force generated by the rotation of the platen.
It is possible to solve the problem that a large amount of polishing liquid does not accumulate in the central portion of the wafer on which the flattening process is performed, and a difference in the polishing amount occurs between the peripheral portion and the central portion of the wafer.

Subsequently, a top view of the polishing cloth in the second embodiment of the present invention is shown in FIG. 1 (c), and a lateral view thereof is shown in FIG. 1 (d). The second embodiment is made of the same material as the first embodiment, but the shape of the groove of the polishing pad is different.
The polishing pad 22 on the surface of the polyurethane 21 in the second embodiment has radial grooves 23 curved in a certain direction, and is composed of 12 polishing pads having a central angle of 20 degrees as in the first embodiment. 2 mm between each polishing pad
The grooves are spaced apart from each other, so that a total of 16 grooves are formed in a radial pattern curved from the center of the polishing cloth. Although the same effect as that of the first embodiment can be obtained, by forming the groove curved in the direction opposite to the rotation direction of the platen indicated by the arrow A, the polishing liquid can be more easily removed.

In the above embodiment, the polishing cloth is composed of two layers of polyurethane and a polishing pad, but the polishing cloth may be composed of one layer of the polishing pad. In this case, the depth is 0.5 on the polishing pad having a thickness of about 1 to 2 mm.
Form a groove of about 1 mm. The number of grooves formed by the polishing pad and the interval between the grooves are not limited to the number and angle shown above, and the rotation speed of the platen and the wafer support, the state of the surface to be polished, the polishing liquid It is possible to carry out various modifications depending on the kind and the concentration.

Further, in the second embodiment, an example in which the groove formed by the polishing pad is curved is shown. However, regarding the degree of curvature, the rotation speed of the platen and the wafer supporting portion and the type of polishing liquid are also shown. It is possible to carry out various modifications depending on the difference in concentration and the like.

Next, an embodiment in which a flattening step is performed in a semiconductor device manufacturing process using the above-described polishing apparatus will be described with reference to the drawings. First, as a first embodiment of the manufacturing method, as shown in FIG. 2A, a first interlayer film 52 is formed on the surface of a wafer 51, and a first wiring layer 53 is formed. , 6000 angstrom Al film is formed, and this is etched and patterned.

Subsequently, as shown in FIG. 2B, an Al film 5 is formed.
A silicon oxide film having a film thickness of 10000 angstrom is formed as a second interlayer film 54 on the surface and the exposed surface of the first interlayer film 52. After that, the wafer is set in the polishing apparatus according to the present invention and operated to flatten the second interlayer film by the CMP method.

In the central portion and the peripheral portion of the wafer after the flattening process, a large amount of the polishing liquid is not accumulated in the central portion of the wafer due to the function of the groove formed in the polishing pad, and the central portion and the peripheral portion of the substrate are prevented. The difference in the polishing amount is reduced, and it is possible to obtain a structure in which the second interlayer film 54 remains on the surface of the first wiring layer 53 as shown in FIG. 2C at both the central portion and the peripheral portion of the wafer. .

Subsequently, as shown in FIG. 2D, the second wiring layer 55 is formed by forming an Al film. Since the interlayer film 54 is formed on the first wiring layer 53,
The desired breakdown voltage between the wirings is maintained.

Next, as a second embodiment of the manufacturing method, a case of applying the CMP method in the step of flattening the buried element isolation layer in the manufacturing step of the semiconductor device will be described with reference to FIG.

First, as shown in FIG. 3A, the wafer 61
As a stopper film for polishing, a film having a thickness of 2000 is formed on the surface through an oxide film 62 having a film thickness of 500 Å.
An angstrom polycrystalline silicon film 63 is formed, and the polycrystalline silicon film 63, the oxide film 62, and the wafer 61 on the region where the element isolation layer is to be formed are etched to form a trench 64 having a depth of about 6000 angstroms.

Subsequently, as shown in FIG. 3B, an oxide film 65 having a film thickness of 10000 angstrom is used as a filling material.
Is formed in the trench and on the surface of the polycrystalline silicon film 63. After that, the wafer 61 is set in the polishing apparatus according to the present invention and operated to flatten the oxide film 65.

In the central portion and the peripheral portion of the wafer after the flattening process, a large amount of the polishing liquid is not accumulated in the central portion of the wafer due to the function of the groove formed in the polishing pad, and the central portion and the peripheral portion of the wafer are prevented. The difference in the amount of polishing is reduced, and flattening can be performed almost uniformly. As shown in FIG. 3C, the wafer is not polished at both the central portion and the peripheral portion of the wafer.

Subsequently, as shown in FIG. 3D, the polycrystalline silicon film 63 and the oxide film 62 are removed by etching,
Impurities are implanted into a predetermined region of the wafer 61 to form the impurity region 6
6 is formed.

In the flattening process of these interlayer films,
By using the polishing apparatus according to the present invention, it is possible to reduce the difference in polishing amount between the peripheral portion and the central portion of the wafer. Therefore, the etching used to remove the polycrystalline silicon film and the oxide film does not damage the wafer, and dislocations do not occur in the wafer, so that a junction leak does not occur even if an impurity region is formed. Further, it is possible to perform highly reliable flattening of the wafer such that a short circuit between wiring layers does not occur.

[0037]

EFFECTS OF THE INVENTION According to the present invention, the polishing cloth adhered on the platen is provided with radial grooves to improve the drainage of the polishing liquid. Therefore, the difference in the polishing amount between the peripheral portion and the central portion of the wafer is small, and it is possible to perform flattening. For example, in the step of flattening the interlayer film, the interlayer film is not excessively polished, and in the step of flattening the element isolation film,
Since the semiconductor wafer is not polished, it is possible to prevent the occurrence of a junction leak current due to a short circuit between wirings and a dislocation of the wafer, and it is possible to suppress a processing variation in a post process due to a variation in a residual film. .

[Brief description of drawings]

FIG. 1 is a top view and a sectional view of an embodiment of a manufacturing apparatus of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing method by the manufacturing apparatus of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing method by the manufacturing apparatus of the present invention.

FIG. 4 is an external view of a polishing device.

FIG. 5 is a sectional view illustrating a manufacturing method using a conventional manufacturing apparatus.

FIG. 6 is a sectional view illustrating a manufacturing method using a conventional manufacturing apparatus.

[Explanation of symbols]

 11, 21 Polyurethane 12, 22 Polishing pad 13, 23 Polishing pad groove 51, 61, 151, 161 Wafer 52, 152 First interlayer film 53, 153 First wiring layer 54, 154 Second interlayer film 55, 155 Second wiring layer 62, 65, 162, 165 Oxide film 63, 163 Polycrystalline silicon film 64, 164 Trench 66, 166 Impurity region 101 Platen 102 Polishing cloth 103 Vacuum hole 104 Wafer 105 Slurry nozzle 106 Pure water nozzle 167 Dislocation

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/3205

Claims (7)

[Claims] 1. A method comprising: preparing a semiconductor substrate having a step on its surface; forming an insulating layer on the surface of the step; and polishing the insulating film with a polishing cloth having grooves radially. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a conductive layer connected to a predetermined conductivity type region in a semiconductor substrate, a step of forming an insulating layer covering the conductive layer, and a step of covering the wiring layer to cover the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating layer thereon; and a step of polishing the insulating film with a polishing cloth having grooves radially. 3. A step of preparing a semiconductor substrate of a predetermined conductivity type, a step of forming a groove in a predetermined region of the semiconductor substrate, and an insulating film formed on the surface of the semiconductor substrate including the inside of the groove. A method of manufacturing a semiconductor device, comprising: a step; and a step of polishing the insulating film with a polishing cloth having radial grooves. 4. The method of manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the radial grooves of the polishing cloth are curved in a direction opposite to a rotation direction of the polishing cloth. Manufacturing method of semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, 2 or 3, wherein the step of polishing the insulating film is performed by chemical polishing with a polishing liquid and mechanical polishing with a polishing liquid and a polishing cloth. A method of manufacturing a semiconductor device, comprising: 6. A substrate supporting part for supporting a substrate having a conductive layer and an insulating layer covering the conductive layer, a polishing cloth for polishing the surface of the substrate, and a surface plate to which the polishing cloth is detachably fixed. A polishing apparatus having a rotating mechanism for relatively rotating and sliding the substrate and the polishing cloth, wherein the polishing cloth has radial grooves. 7. The polishing apparatus according to claim 6, wherein the radial grooves of the polishing cloth are curved in a direction opposite to a rotation direction of the platen.