JPH07301665A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to independently set voltage at the normal action time and at the voltage aging time by connecting the output terminals of MOS transistors commonly to a nodal point between a voltage generating circuit for generating voltage small in external supply voltage dependency and a voltage generating circuit for generating voltage large in external supply voltage dependency. CONSTITUTION:A voltage converting circuit for converting external supply voltage Vcc into output voltage VL is constituted of an amplifier formed of a differential amplifier 60 and an MOS transistor 62, and an amplifier formed of a differential amplifier 61 and an MOS transistor 63. In the case of the input voltage V1 of the differential amplifier 60 being higher than the output voltage VL the transistor 62 becomes conductive, and in the reverse case, the transistor 62 becomes non-conductive. The transistor 63 is the same, and in the case of the output voltage VL being lower than at least one of V1 and V2, at least one of the transistors 62, 63 becomes conductive. A current therefore flows from a power supply Vcc, and the potential of the output voltage VL, rises. Since this potential rise is stabilized in the state of VL being equal to the higher potential of V1 and V2, voltage can be set independently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a voltage conversion circuit for generating an internal power supply voltage used in at least a part of a circuit of the semiconductor device.

[0002]

2. Description of the Related Art In recent years, a decrease in breakdown voltage due to miniaturization of semiconductor elements has become a problem. This problem can be solved by lowering the power supply voltage, but this is not always preferable due to the external interface. Therefore, the power supply voltage applied from the outside is kept as it is (for example, 5 V in the case of TTL compatible) and a voltage lower than that (for example, 3 V).
A method has been proposed in which the internal power supply V) is made in the semiconductor device. A voltage conversion circuit for generating an internal power source from an external power source is disclosed in, for example, Japanese Patent Application No. 57-2200.
83. FIG. 15 (a) shows a circuit proposed in the above patent application. This circuit is a circuit that generates an internal power supply V _L from an external power supply V _cc , R is a resistance element, and BL ₀ and BL ₁ are circuits called “basic circuits” in the above patent application. The “basic circuit” is a circuit in which the BCs are non-conductive when the voltage between the ACs is equal to or lower than a predetermined voltage (hereinafter referred to as ON voltage), and the BCs are conductive when the voltage is equal to or higher than the predetermined voltage. Figure 15 (b)
Is an implementation example of the "basic circuit" described in the above patent application.

The characteristic of this circuit is shown in FIG. When the external power supply voltage V _cc is equal to or lower than V _P0 (V _P0 is the ON voltage of the basic circuit BL ₀ ), both BL ₀ and BL ₁ are in the non-conducting state, so the output voltage V _L is equal to V _cc . When V _cc exceeds V _P0 , BL ₀ becomes conductive, so that V _L becomes the resistance elements R and B.
It is determined by the ratio of L _{0 to} the on-resistance R ₀ . Therefore, V of V _{L
The cc} dependency (slope m) is smaller than 1 as shown in the figure. When V _cc further rises and V _cc -V _L exceeds V _P1 (V _P1 is the ON voltage of the basic circuit BL ₁ ), BL ₁ becomes conductive, and the resistor R has an ON resistance R ₁ of BL _1. Connected in parallel. Therefore, the dependence of V _L on V _cc (slope m ′) becomes larger than m.

That is, the point P is the dependency of V _L on V _cc.
Bending properties are obtained at and P '. Point P,
The value of V _cc in P ′ is V ₀ = V _P0 (1) V ₀ ′ = V _P0 + V _P1 / (1-m) (2) Further, the inclinations m and m ′ are m = R ₀ / (R + R ₀ ) ... (3) m ′ = R ₀ / {RR ₁ / (R + R ₁ ) + R ₀ } (4)

The advantage of this circuit is that the first _Vcc dependence is small.
Of the second voltage and the second voltage having a higher V _cc dependency than the first voltage.
It is possible to generate the voltage of and. As a result, as described below, it becomes possible to perform voltage aging of a circuit (hereinafter, abbreviated as an internal circuit) that operates with the internal power supply V _L. Voltage aging is a method of applying a voltage higher than that during normal operation to a power supply terminal before a semiconductor device is shipped to remove defective products, which is an effective method for reducing initial defects after shipping. . In order to enable the voltage aging of the internal circuit, the external power supply voltage V _cc during normal operation is V _0.
And 'located between, V _cc during aging V _0' V ₀ to be higher than, it is sufficient to design a V _0, V ₀ '. In this case, since the V m dependency of V _L on V _cc is small during normal operation, the operation of the internal circuit is stable even if V _cc fluctuates. Further, since V _cc dependence m 'is large V _L at the time of aging, sufficiently high V _L than in normal operation is applied to the internal circuit, the voltage aging of the internal circuit is performed. At this time, V
_{Since a} voltage sufficiently higher than that during normal operation is applied to the circuits operating in _CC , voltage aging of these circuits is also performed at the same time. Incidentally, regarding voltage aging, there is another invention described in Japanese Patent Laid-Open No. 232155/1987.

[0006]

The problem of the above-mentioned prior art is that the above-mentioned first voltage having a small V _cc dependency and the second voltage having a larger V _cc dependency than the first voltage. There is something that cannot be designed independently. That is, the second voltage depends on the characteristics of the circuit that generates the first voltage. As a result, the voltage during normal operation of the internal power supply and the voltage during voltage aging cannot be set independently. Figure 1
In the circuit of FIG. 5 (a), the first voltage having a small V _cc dependency is B
The second voltage, which is determined by L _{0 and} whose V _cc dependency is larger than the first voltage, is determined by BL ₀ and BL ₁ .
Therefore, if BL ₀ is changed to change the first voltage, the second voltage also changes at the same time. Parameter m ', which determines the characteristic of the second voltage with respect to _Vcc ,
From the formulas (1) to (4), V ₀ ′ is m ′ = (R + R ₁ ) / (R ₁ / m + R) (5) V ₀ ′ = V ₀ + V _P1 / (1-m) (6) Is. As is clear from these equations, the parameters m ′ and V ₀ ′ that determine the characteristic of the second voltage with respect to V _cc .
Depends on m and V ₀ , which are parameters that determine the characteristics of the first voltage with respect to V _cc . Therefore, the first
If the setting of BL ₀ is changed to change the setting value of the voltage of, BL ₁ must be set again. An object of the present invention is to provide a semiconductor device having a voltage conversion circuit capable of independently setting the first voltage and the second voltage.

[0007]

In order to achieve the above object, according to the present invention, the voltage conversion circuit has a first voltage whose external power supply voltage dependence is small when the external power supply voltage is higher than a first predetermined voltage. A first voltage generating circuit for generating
A second voltage generating circuit for generating a second voltage having a greater dependence on the external power supply voltage than the voltage of the second power supply, and a second source / drain path provided between the node and the external power supply voltage.
And a third MOS transistor and its output is the second M
The first differential amplifier connected to the gate of the OS transistor and the second differential amplifier whose output is connected to the gate of the third MOS transistor, and the inversion of the first differential amplifier. The first voltage is input to the input, the second voltage is input to the inverting input of the second differential amplifier, and the non-inverting inputs of the first and second differential amplifiers are the nodes. Connected with.

[0008]

In the voltage conversion circuit, the second MOS transistor which is the output transistor of the first voltage generation circuit and the third MOS transistor which is the output transistor of the second voltage generation circuit are included.
Since the output terminal of the MOS transistor is connected in common, the output is automatically switched in response to the output of each of the first and second voltage generating circuits.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the case where the external power supply voltage V _cc is positive will be described. However, even when V _cc is negative, the present invention can be applied by reversing the polarity of the transistor and the like.

FIG. 1A shows a configuration diagram of a voltage conversion circuit according to a first embodiment of the present invention. In the figure, 1 and 2 are voltage generation circuits, and 3 is a selection circuit. In this circuit, one of the outputs V ₁ and V ₂ of the two voltage generation circuits 1 and 2 is selected by the selection circuit 3 to be the output voltage V _L. Of the outputs of the two voltage generating circuits, V ₁ has little dependence on the external power supply voltage V _cc , that is, is stabilized with respect to V _cc . On the other hand, V ₂ has a relatively large dependence on V _cc . The selection circuit 3 is controlled by a signal TE indicating whether the semiconductor device is in a normal operation state or a test state. In the normal operation state, V ₁ is selected, and in the test state, V ₂ is selected and becomes V _L.

A feature of this circuit is that the dependency of the operation of the internal circuit on the internal power supply voltage can be tested and the voltage aging of the internal circuit can be performed. FIG. 1B shows an example of the V _cc dependency of the voltage of each part of this circuit. This is the external power supply voltage _Vcc = during normal operation.
5 ± 0.5 V (indicated by a in the figure), internal power supply voltage V _L = 3
V, external power supply voltage during aging V _CC = 8V (b in the figure
), And the internal power supply voltage V _L = 4.8V. V ₁ has a small dependency on V _cc and is substantially constant (here, 3 V, but when V _cc <3 V, V ₁ =
_Vcc ). On the other hand, V ₂ monotonically increases in accordance with V _cc (here, V ₂ = 0.6V _cc ). V _L = V ₁ during normal operation
Therefore, the stabilized internal power supply voltage (= 3V) is applied to the internal circuit, and the operation of the internal circuit becomes stable.
Further, since V _L = V ₂ in the test state, V _cc
The internal power supply voltage applied to the internal circuit can be changed by changing In the conventional voltage conversion circuit, it is difficult to test the power supply voltage dependence of the operation of the internal circuit because the stabilized voltage is always applied to the internal circuit. become. In addition, since the internal power supply voltage during normal operation is stabilized, it is possible to design with a margin for fluctuations in the internal power supply voltage. Further, in order to perform the voltage aging of the internal circuit by this circuit, V _cc may be set to the aging voltage (here, 8 V) in the test state. Since it is a test state, V _L =
The voltage becomes V ₂ (= 4.8V), and the internal power supply voltage higher than that in the normal operation is applied to the internal circuit.

As is clear from the above description, the normal operation voltage generation circuit 1 only needs to satisfy the characteristics in the normal operation state, and the test voltage generation circuit 2 only needs to satisfy the characteristics in the test state. That is, 1 and 2 can be designed independently.

In this embodiment, the outputs of the two voltage generating circuits are selected as the internal power supply voltage, but the outputs of three or more voltage generating circuits may be selected. This is effective, for example, when testing the internal circuit under a plurality of conditions.

FIG. 2A is a block diagram of the voltage conversion circuit according to the second embodiment of the present invention. The difference from the embodiment of FIG. 1 is that the selection circuit 3 is controlled by the output of the comparison circuit 4. The comparison circuit 4 compares the output V ₁ of the normal operation voltage generation circuit with the output V ₂ of the aging voltage generation circuit and controls the selection circuit 3 so that the higher voltage is selected.

A characteristic of this circuit is that an internal power supply having a characteristic capable of aging the voltage of the internal circuit can be obtained without adding a control signal such as TE in FIG. Figure 2
An example of the V _cc dependency of the voltage of each part of this circuit is shown in (b). This is the external power supply voltage _Vcc = 5 ± 0 during normal operation.
In this example, 5 V, V _cc = 8 V during aging, internal power supply voltage V _L = 3 V during normal operation, and V _L = 4 V during aging. V ₁ is a stabilized voltage as in the case of FIG. On the other hand, V ₂ monotonically increases according to V _cc (here, V ₂ = V _cc / 2). Thus, <when the 6V V _1> V _cc is V _2, when the V _cc> 6V is V ₁ <V _2. Since V _L is equal to the higher of V ₁ and V ₂ , V _cc <6
When V is V _L = 3V, when V _cc > 6V, V _L = V _cc /
It becomes 2. That is, when _Vcc is a voltage between the normal operating voltage and the aging voltage (6V in this case), a bent characteristic is obtained. When V _cc is within the normal operating voltage range (here 5 ± 0.5 V, indicated by a in the figure),
Since _VL is stabilized (here, 3V), the operation of the internal circuit becomes stable. When V _cc is at the aging voltage (here, 8 V, indicated by b in the figure), V _L
Is higher than that during normal operation (4V in this case), so a voltage higher than that during normal operation is applied to the internal circuit, and voltage aging of the internal circuit is performed.

As is clear from the above description, the normal operation voltage generation circuit 1 has only the characteristics when V _cc is within the normal operation voltage range, and the aging voltage generation circuit 2 has V _cc at the aging voltage. It suffices to satisfy only the characteristics of time. That is, 1 and 2 can be designed independently. The characteristic during normal operation, which has been a problem in the above-mentioned conventional techniques, does not affect the characteristic during aging. Therefore, the circuit design is easier than in the prior art.

FIG. 3A is a block diagram of the voltage conversion circuit according to the third embodiment of the present invention. The difference from the circuit of FIG. 2 is that there are a plurality of output terminals (V _LA , V _LB , V _LC ). Further, a plurality of aging voltage generation circuits, selection circuits, and comparison circuits are also provided. The aging voltage generation circuits 2A, 2B and 2C generate aging voltages V _2A , V _2B and V _2C , respectively. Selection circuit 3
A, 3B, and 3C are V _LA , V _{L B} , and V _LA from the normal operation voltage V ₁ and the aging voltages V _2A , V _2B , and V _2C , respectively.
Generate _LC . At this time, the comparison circuits 4A, 4B, and 4C compare the normal operation voltage and the aging voltage, respectively, and select the higher voltage to obtain V _LA , V _LB , and V _LA .
_{The LC} is the same as in the case of FIG.

The characteristic of this circuit is that voltage aging can be performed under different conditions depending on the circuit.
An example of the V _cc dependency of the output voltage is shown in FIG. V _cc
Is within the normal operating voltage range (indicated by a in the figure), V ₁ is higher than V _2A , V _2B and V _2C .
V _LA , V _LB , and V _LC are all equal to V ₁ . Also, V _cc
Is at the aging voltage (indicated by b in the figure),
Since V _2A , V _2B and V _2C are higher than V ₁ , V _LA and V 2
_LB and _VLC are equal to V _2A , V _2B and V _2C , respectively. That is, V _LA , V _LB , and V _LC are stabilized at the same voltage during normal operation, but have different voltages during aging. Therefore, the internal circuits to which V _LA , V _LB , and V _LC are applied are aged under different conditions.

As described above, it is another feature of the present invention that a circuit capable of performing aging under different conditions for each circuit can be manufactured. In order to do the same with the above-mentioned conventional technique, for example, a plurality of circuits shown in FIG. However, if there are variations in elements among the plurality of circuits, it is difficult to provide the voltage value during normal operation and its V _cc dependency. On the other hand, in the circuit of FIG. 3A, a plurality of internal power supplies are generated based on one stabilizing voltage V ₁ during normal operation, so that it is easy to make their voltage values uniform.

Next, the individual circuits constituting the voltage conversion circuit shown in FIGS. 1 to 3 will be described in detail.

First, the normal operation voltage generating circuit 1 will be described. As the normal operation voltage generation circuit 1, a well-known stabilized voltage generation circuit, for example, a circuit using a breakdown voltage of a Zener diode or a base-emitter voltage of a bipolar transistor as a reference voltage can be used. An example of the circuit is shown in FIG. In the figure, 10 is NP
N transistors, 11 are Zener diodes, and 12 and 13 are resistors. The voltage between the output V ₁ and node 14 and the voltage between node 14 and ground are each 1
The breakdown voltage V _{2 is 1} , the base-emitter voltage V _be is 10, and both are substantially constant regardless of the power supply voltage V _cc . Therefore, the output voltage of this circuit is V ₁ = V ₂
It is constant at + V _be . Moreover, if a bandgap reference as shown in FIG. 4B is used, a stable voltage can be obtained not only with a change in V _cc but also with a change in temperature. In addition, for example, JP-A-62-1237
The circuit proposed in Japanese Patent Publication No. 97 may be used.

Next, the voltage generating circuit 2 will be described. Output V ₂ of the voltage generating circuit 2, when testing the semiconductor device, or from those used during aging, its characteristics should be determined by the test conditions or aging conditions. For example, the aging voltage generating circuit 2 used in the embodiment of FIG. 2 is a circuit for generating a voltage which is half the power supply voltage _Vcc . This can be realized by a circuit as shown in FIG. In the figure, 30 and 32 are n-channel MOS transistors, and 31 and 33.
Is a p-channel MOS transistor, and 34 and 35 are resistors. The on resistance of the MOS transistor is R ₃₄ , R ₃₅
(R ₃₄ and R ₃₅ are resistance values of ₃₄ and ₃₅ respectively), and assuming that R ₃₄ = R ₃₅ , the voltage of the node 36 becomes 1/2 of the power supply voltage V _cc and V _cc / 2. . Therefore, the voltages at the nodes 37 and 38 are _Vcc / 2 + V, respectively.
_{tn, V cc / 2- | V} tp | (V tn, V tp is an n-channel MOS transistors, respectively, the threshold voltages of the p-channel MOS transistor), and the output voltage is V ₂ = V _cc / ₂
Becomes By changing the ratio of R ₃₄ and R ₃₅ , V
It is also possible to generate a voltage that is a constant multiple of _cc (eg, 0.6 V _cc as in the test voltage generating circuit of FIG. 1).

The characteristic of this circuit is that the current consumption is R ₃₄ , R _35.
The current drive capability is determined by the MOS transistors 32 and 33 in the output stage. Therefore, if R ₃₄ and R ₃₅ are made sufficiently large and the channel widths of 32 and 33 are made sufficiently large, it is possible to make a circuit with a small current consumption and a large current drive capability. When the current driving capability may be small (for example, when the circuit of FIG. 8 is used as the selection circuit 3 and the comparison circuit 4 as described later), the circuit of FIG. 5B or 5C may be used. Figure 5
The circuit of (b) is simply _Vcc divided by resistors R ₃₄ and R ₃₅ .

FIG. 5C shows another method of realizing the voltage generating circuit 2. This circuit has a voltage (V ₂ = 3V _cc / V ₂ here) that is offset by a constant multiple of the external power supply voltage V _cc.
4-1.5 (V)). 40 in the figure
Reference numeral 42 denotes a diode, and by connecting three diodes in series, the voltage of the node 43 is set to a voltage lower than the power supply voltage _Vcc by about 2V. The resistance ratio is _R34 : _R35 = 1:
If _{3, V 2 = 3/4} (V cc -2) = 3V cc / 4-
An output voltage of 1.5 (V) can be obtained.

Next, a method of implementing the selection circuit 3 and the comparison circuit 4 used in the embodiments of FIGS. 2 and 3 will be described. A method of realizing the selection circuit 3 and the comparison circuit 4 is shown in FIG. In the figure, 50 and 51 are differential amplifiers, 52 and 5
3 is a NAND gate, 54 and 55 are inverters, 5
6 and 57 are p-channel MOS transistors, and 58 and 59 are n-channel MOS transistors. In this circuit, the higher voltage of the inputs V ₁ and V ₂
It is a circuit connected to the output V _L through the transistors 56, 58 or 57, 59. When V ₁ is higher than V ₂ , the outputs of the differential amplifiers 50 and 51 are high potential and low potential, respectively, and the outputs of the NAND gates 52 and 53 are low potential and high potential, respectively, so that the p-channel MOS transistor 56 is conductive and 57 is non-conductive. Further, since the outputs of the inverters 54 and 55 have high potential and low potential, respectively, the n-channel MOS transistor 58 becomes conductive and 59.
Becomes non-conductive. Therefore, the MOS transistor 56
The input V ₁ and the output V _L are connected through 58 and 58. On the contrary, when V ₂ is higher than V ₁ , the level of the potential is opposite to the above, and the input V ₂ and the output V _L are connected through the MOS transistors 57 and 59.

The characteristic of this circuit is that when V ₁ > V ₂ , the input V
That is, ₁ becomes the output V _L as it is. Therefore, M
If the ON resistances of the OS transistors 56 and 58 are designed to be sufficiently small, the voltage stability of the output V _L can be the same as the voltage stability of the output V ₁ of the normal operation voltage generation circuit 1. .

Another method of realizing the selection circuit 3 and the comparison circuit 4 is shown in FIG. In the figure, 60 and 61 are differential amplifiers, and 62.
And 63 are p-channel MOS transistors, and 64 is a current source. This circuit comprises a voltage amplifier composed of 60 and 62 and a voltage amplifier composed of 61 and 63.
63 are connected in parallel. The current source 64 is for giving a bias current to the output stage. When V ₁ > V _L , the output of the differential amplifier 60 is at a low potential, so that the p-channel MOS transistor 62 becomes conductive, but V ₁
When <V _L , the output of the differential amplifier 60 is at a high potential, and therefore 62 is non-conductive. At the same time, the MOS transistor 63 is conductive when V ₂ > _VL and non-conductive when V ₂ < _VL . Therefore, the output voltage V _L is V ₁ or V
When it is lower than at least one of the _two , at least one of the MOS transistors 62 and 63 is in a conductive state, so that a current flows from the power supply _Vcc to _VL and the potential of _VL rises. This potential increase continues until V _L becomes equal to the higher potential of V ₁ and V ₂ and both MOS transistors 62, 63 are rendered non-conductive. Eventually, V _L stabilizes at a state equal to the higher potential of V ₁ and V ₂ .

The characteristic of this circuit is that the circuit itself has an amplifying function. Therefore, even if the current driving capability of the voltage generating circuits 1, 2, 2A, 2B, 2C of FIGS. 2 and 3 is small, the current driving capability of the output V _L can be increased. Therefore, for example, as the voltage generating circuit 2, a simple circuit shown in FIG. 5B or 5C can be used instead of the circuit shown in FIG.

In the above example, the output voltage V _L is the input voltage V ₁
Alternatively, the voltage is equal to V ₂ , but V _L may be a constant multiple of V ₁ or V ₂ . FIG. 8 shows one method of realizing this. The difference from the circuit of FIG. 7 is that the input of the differential amplifiers 60 and 61 is not V _L itself, but V _L.
Voltage divided by resistors 65 and 66 R _{65 VL} / (R ₆₅ + R
₆₆ ) is included (R ₆₅ and R ₆₆ are each 6
5, 66 resistance value). Therefore, R _{65 VL} / (R ₆₅ + R
₆₆ ) becomes equal to the higher voltage of V ₁ and V ₂ . That is, the output voltage V _L is (R ₁₎ of the higher voltage of V ₁ and V _2.
65 + R ₆₆ ) / R ₆₆ times.

The advantage of this circuit is that by changing the ratio of the resistors R ₆₅ and R ₆₆ , a voltage that is an arbitrary multiple of the input voltage can be obtained. This is particularly effective when only a specific voltage can be obtained as the stabilizing voltage V ₁ . For example, when the aforementioned bandgap reference is used as the voltage generating circuit 1, the output voltage is V ₁ = 1.26V. To obtain the output voltage V _L = 3V from this, for example, R
₆₅ : R ₆₆ = 1.74: 1.26.

The differential amplifier used in the circuits of FIGS. 6 to 8 can be realized by the circuit of FIG. 9, for example. In the figure, reference numeral 70 denotes a main body of a differential amplifier, which includes p-channel MOS transistors 71 and 72 and n-channel MOS transistors 73 and 7.
It consists of 4,75. When the voltage of the input V _in1 is higher than the voltage of V _in2, the output V _out becomes high potential, when the voltage of V _in2 is higher than the voltage of V _in1 is V _out becomes low potential.

Reference numeral 80 is a circuit for operating the MOS transistor 75 as a current source. Reference numeral 81 is a p-channel MOS transistor that acts as a high resistance and determines the current flowing through the n-channel MOS transistor 82. 75
Since and 82 form a current mirror circuit,
A current that is a constant multiple of the current that flows through 82 (the ratio of the conductance between 75 and 82) flows through 75. 6 to 8
As described above, when a plurality of differential amplifiers are used, only one circuit 80 is provided and the gates of 75 of the plurality of differential amplifiers are commonly connected to save the occupied area.

Next, an example in which the present invention is applied to a DRAM (dynamic random access memory) will be described.
FIG. 10 is a block diagram of a DRAM to which the present invention is applied, and FIG. 11 is its operation waveform. In the figure, 100 is a voltage conversion circuit according to the present invention, 200 is a memory array, 201 is a word driver, 202 is a word line booster circuit, 203 is a data line precharge circuit, 204 is a sense amplifier, and 205 is a sense amplifier drive signal generation circuit. , 206 is a data line selection circuit, 207 is a row decoder, 208 is a row address buffer, 209 is a column decoder, 210 is a column address buffer, 211 is a main amplifier, 212 is a Dout buffer, 213 is a write circuit, 214 Din buffer, 21
Reference numeral 5 is a timing generation circuit. In this memory, the memory array 200, which greatly affects the degree of integration, is a fine MOS.
It uses a transistor and operates with an internal power supply V _L (eg 3.3 V) lower than the external power supply V _cc (eg 5 V). On the other hand, the circuits 207-
215 operates directly with the external power supply _Vcc . In order to operate the memory array at V _L , the word line booster circuit 202, the data line precharge circuit 203, the sense amplifier drive signal generation circuit 205, and the data line selection circuit 206 are connected to the internal power supply V _x , from the voltage conversion circuit 100. V _p , V _d , V _y
Is supplied.

Of the voltage conversion circuit 100, the circuit 101 for generating V _L has the same configuration as that shown in FIG. That is, the higher voltage of the normal operation voltage generation circuit 1 and the aging voltage generation circuit 2 is selected by the selection circuit 3, and V
It becomes _L. Buffers 5 to 8 are provided to increase the load driving capability. The buffers 5, 7, and 8 are circuits that generate voltages V _x , V _d , and V _y, which are equal to V _L , respectively. The buffer 6 is a circuit that generates a voltage V _p that is ½ of V _L. As the buffers 5, 7, and 8, for example, the circuit proposed in Japanese Patent Application No. 62-294115 can be used. Further, the buffer 6 can be realized by, for example, the circuit of FIG. This circuit, like the circuit of FIG. 5A, is a circuit that generates a voltage that is half the power supply voltage (here, V _L ). However, only the MOS transistor 32 in the output stage is connected to V _cc instead of V _L. The reason for this is
Since the output stage has to drive the load directly, it is preferable to use V _cc , which has a large current driving capability, but of course V _L can be used.

In the memory array 200, there is a so-called 1 circuit composed of a MOS transistor 220 and a capacitor 221.
A transistor / one-capacitor type dynamic memory cell MC _ij is arranged at the intersection of the word line W _i and the data line D _j . Although only two word lines (W _i , W _{i + 1} ) and one pair of data lines (D _j , −D _j ) are shown in the figure, a large number are arranged vertically and horizontally. Note that one end 222 (plate) of the capacitor 221 is connected to a DC power source. Although its voltage value is arbitrary, it is V in terms of the withstand voltage of the capacitor 221.
It is desirable to connect to _p (= V _L / 2).

The word driver 201 is a row decoder 2
This circuit receives the output of 07 and supplies the word line drive signal φ _x to the selected word line through the MOS transistor 223. φ _x is generated _by the word line boosting circuit 202. This circuit is a circuit for boosting φ _x above the power supply voltage. However, the power supply of this circuit is not the external power supply _Vcc ,
It is the internal power supply V _x made by the voltage conversion circuit. Therefore, φ _x is boosted with reference to V _x , not V _cc . That is, as shown in FIG. 11, the voltage of φ _x is (1 + α) of V _x.
Double (0 <α <1).

A method of realizing the word line boosting circuit 202 is shown in FIG. This is a circuit that generates a signal φ _x after a predetermined time has passed since the input signal φ _in became high potential. The main part of this circuit is inverters 250-253, 260-
263, boosting capacitor 270, precharge circuit 2
Composed of 80. Inverter rows 250-252 and 26
Reference numerals 0 to 262 are circuits for obtaining a predetermined delay time.
Incidentally, these inverters are used the V _cc as the power source, no problem even V _x. The outputs of 252 and 262 change from the high potential to the low potential after a predetermined time has passed since φ _in became the high potential. Therefore, the output of 253 rises. Since it is the power supply V _x of this inverter 253, the voltage of the node 271 changes from 0 V to V _x . As the potential at one end 271 of the capacitor 270 rises, the potential at the other end 272 of the capacitor rises due to capacitive coupling. The voltage of the node 272 is V _x − in advance by the precharge circuit 280 (the precharge signal φ _p has a high potential when the memory is in the standby state).
Since it is set to V _tn (V _tn is the threshold voltage of the n-channel MOS transistor), it is raised to V _x −V _tn + C _b V _x / (C _b + C _p ) ... (7) by capacitive coupling. Here, C _b and C _p are the capacitance of the capacitor 270 and the parasitic capacitance of the node 272, respectively. Inverter 263 (p-channel MOS transistor 264 and n
Channel MOS transistors 265 and 266)
Operates with this voltage as a power supply, the potential of the output φ _x also rises to the above voltage. The MOS transistor 265 of the inverter 263 is provided to prevent an excessive voltage from being applied to 266. 265 gate V
Since it is connected to _cc (which may be V _x ), the drain voltage of 266 never exceeds V _cc -V _tn . Circuit 29
0 is for preventing the electric potential of φ _x from rising too much. Since the diode-connected n-channel MOS transistors 291 and 292 are connected in series, φ _x
Does not exceed V _cc + 2V _tn . The source of this MOS transistor 292 may be connected to V _x . The circuit 300 is a circuit for preventing the potential thereof from lowering due to leakage current or the like when the period in which φ _x is boosted is long. φ ₁ is a signal which becomes high potential while the memory is in an active state, and φ ₂ is a signal which periodically becomes high potential. When φ ₂ becomes a high potential, the potential of the node 305 is boosted to V _x or higher due to the capacitive coupling by the capacitor 304, and the potential drop of φ _x is compensated.

The data line precharge circuit 203 is a circuit for setting each data line to a predetermined voltage (here, the internal power supply voltage V _p ) before reading the memory cell. By applying the precharge signal φ _p , M
OS transistor 224-226 is conductive, the voltage of the data line D _j, ¯D _j is equal to V _p. At this time, sense amplifier drive signals SAN and SAP, which will be described later, are simultaneously set to V _p by the MOS transistors 233 to 235.

When φ _x is applied to the word line, signal charges are read from each memory cell to each data line, and the potential of the data line changes. Operation waveforms of FIG. 11 is an example in which the capacitor in advance the high potential of the memory cell (≒ V _d) is accumulated, the potential of the data line D _j is increased slightly, between D _j There is a potential difference. The sense amplifier 203 is a circuit for amplifying this minute signal,
A flip-flop composed of n-channel MOS transistors 227 and 228, and a p-channel MOS transistor 2
It is composed of a flip-flop composed of 29, 230. The sense amplifier is activated by setting φ _sa to a high potential and −φ _sa to a low potential to make the MOS transistors 231 and 232 conductive. The SAN is grounded through 231 and the SAP is grounded through 232 by the internal power supply V _d.
Connected to. Thereby, the data line D _j, the small potential difference between D _j is amplified, whereas (D _j in the case of FIG. 11)
Becomes V _d , and the other (−D _{j in} the case of FIG. 11) becomes 0 V.

The data line selection circuit 206 receives the output of the column decoder 209 and outputs the selected data line pair to MO.
I / O line I / through S transistors 236 and 237
This is a circuit that connects to O and I / O. When reading,
The data latched in the sense amplifier is the input / output line,
The data is output to the data output terminal Dout via the main amplifier 211 and the Dout buffer 212. When writing, the data input from the data input terminal Din is the Din buffer 2
14, input / output lines I / O and ￣I via the write circuit 213
/ O, and further MOS transistors 236, 2
37, the data line D _j, is written into the memory cell through ¯D _j. Here, 238 is the MOS transistors 236, 2
This is a circuit for limiting the voltage of the signal Y _j ′ applied to the gate of 37 to V _y . For example, as shown in FIG.
It can be realized by a circuit in which the current of the stage is V _y . That is,
The voltage amplitude of the output Y _j of the column decoder is V _cc ,
The voltage amplitude of Y _j 'is V _y . The reason for this is as follows. Since the writing circuit 213 operates at V _cc , the amplitude of the input / output line at the time of writing is V _cc . Therefore, unless the voltage of Y _j 'is limited, the voltage V _cc -V _tn (V _tn is the MOS transistor 2) is applied to the memory array.
36,237 threshold voltage). If the write circuit 213 is operated at V _L , the voltage of Y _j ′ may be V _cc . In this case, the circuit 238 is unnecessary.

The row address buffer 208 and the column address buffer 210 are circuits which receive an address signal A _n input from the outside and generate a row address signal a _rn and a column address signal a _cn , respectively. These address signals are used by the row decoder 207 and the column decoder 209 to select word lines and data lines, respectively. The timing generation circuit 215 is a circuit that generates internal timing signals necessary for the operation of the memory from control signals (row address strobe signal RAS, column address strobe signal CAS, and write enable signal WE) input from the outside. As mentioned above, these circuits operate directly on the external power supply _Vcc . The reason for this is
Since these circuits do not affect the integration degree so much, it is not necessary to use fine MOS transistors, and it is convenient for the interface for receiving external signals.
Of course, you may make it operate _| move by _VL .

[0042] FIG. 14 (a), V _cc of each part of the voltage to (b)
Show dependencies. This is an external power supply voltage V _cc of normal operation
= 5 ± 0.5V, _Vcc during aging = 8V, internal power supply voltage _VL during normal operation = 3.3V, _VL during aging
This is an example in the case of = 4V. It is the same as in the case of FIG. 2 that the bent characteristic is obtained at a voltage (here, 6.6 V) where V _cc is between the normal operating voltage and the aging voltage. Since V _x , V _a , and V _y are equal to V _L, they are 3.3 V during normal operation and 4 V during aging. V _p is V _L
Since it is equal to / 2, it is 1.65V during normal operation and 2V during aging. The voltage of the word line drive signal φ _x is equal to (1 + α) V _x , as described above. In the figure α = 0.6
An example in the case of is shown. In this case, 5.
3V, 6.4V during aging.

[0043]

As described above, according to the present invention,
It is possible to independently design the first voltage having a small dependency on the external power supply voltage and the second voltage having a greater dependency on the external power supply voltage than the first voltage.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a voltage conversion circuit according to an embodiment of the present invention and a graph showing its characteristics.

FIG. 2 is a configuration diagram of a voltage conversion circuit according to an embodiment of the present invention and a graph showing its characteristics.

FIG. 3 is a configuration diagram of a voltage conversion circuit according to an embodiment of the present invention and a graph showing its characteristics.

FIG. 4 is a circuit diagram of an element circuit in the voltage conversion circuit of FIGS.

FIG. 5 is a circuit diagram of an element circuit in the voltage conversion circuit of FIGS.

FIG. 6 is a circuit diagram of an element circuit in the voltage conversion circuit of FIGS.

FIG. 7 is a circuit diagram of an element circuit in the voltage conversion circuit of FIGS.

FIG. 8 is a circuit diagram of element circuits in the voltage conversion circuit of FIGS.

FIG. 9 is a circuit diagram of an element circuit in the voltage conversion circuit shown in FIGS.

FIG. 10 is a block diagram of a DRAM to which the present invention is applied.

11 is an operation waveform of the DRAM of FIG.

12 is a circuit diagram of an element circuit of the DARM shown in FIG.

13 is a circuit diagram of an element circuit of the DARM shown in FIG.

14 is a graph showing the characteristics of the voltage conversion circuit in FIG.

FIG. 15 is a circuit diagram of a conventional voltage conversion circuit and a graph showing its characteristics.

[Explanation of symbols]

1, 2, 2A, 2B, 2C ... Voltage generating circuit, 3, 3A,
3B, 3C ... Selection circuit, 4, 4A, 4B, 4C ... Comparison circuit, 5-8 buffers.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 21/822 (72) Inventor Ryoichi Hori 1-280 Higashi-Kengikubo, Kokubunji-shi, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Yoshinobu Nakanogo, 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. (72) Inventor, Masakazu Aoki Masakazu Aoki, 1-280, Higashikoigokubo, Kokubunji, Tokyo, Ltd. Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Hitoshi Tanaka, 1448, Kamimizuhonmachi, Kodaira, Tokyo・ I Engineering Co., Ltd.

Claims (13)

[Claims] 1. A first MOS transistor, a first wiring connected to a source or a drain of the first MOS transistor, and a second wiring connected to a gate of the first MOS transistor. In a semiconductor device having a voltage conversion circuit which is supplied with an external power supply voltage and supplies the internal power supply voltage to the first wiring, the voltage conversion circuit is configured such that when the external power supply voltage is higher than a first predetermined voltage. A first voltage generating circuit for generating a first voltage having a small dependence, a second voltage generating circuit for generating a second voltage having a larger dependence on the external power supply voltage than the first voltage, and a node Second and third MOS transistors whose source / drain paths are provided between the external power supply voltage and the first differential amplifier whose output is connected to the gate of the second MOS transistor. And a second differential amplifier whose output is connected to the gate of the third MOS transistor, the first voltage being input to the inverting input of the first differential amplifier, The second voltage is input to the inverting input of the second differential amplifier, and the non-inverting inputs of the first and second differential amplifiers are connected to the node. 2. The semiconductor device according to claim 1, further comprising a circuit that operates with the external power supply voltage. 3. The first voltage is higher than the second voltage when the external power supply voltage is lower than the second predetermined voltage, and the external power supply voltage is higher than the second predetermined voltage. 3. The semiconductor device according to claim 1, wherein the first voltage is lower than the second voltage. 4. The semiconductor device according to claim 1, wherein the voltage conversion circuit further includes a current source connected to the node. 5. The semiconductor according to claim 1, wherein the voltage conversion circuit has means for dividing a voltage between the node and the first differential amplifier. apparatus. 6. The semiconductor according to claim 1, wherein the voltage conversion circuit has means for dividing a voltage between the node and the second differential amplifier. apparatus. 7. The first wiring constitutes a data line, the second wiring constitutes a word line, and the first MOS transistor constitutes a memory cell. The semiconductor device according to claim 6. 8. A word line boosting circuit connected between the node and the word line, wherein the word line boosting circuit boosts the internal power supply voltage to a predetermined voltage higher than the internal power supply voltage. The semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 8, further comprising a buffer connected between the node and the word line boosting circuit. 10. The semiconductor device according to claim 7, further comprising a sense amplifier connected between the node and the data line. 11. The semiconductor device according to claim 10, further comprising a buffer connected between the node and the sense amplifier. 12. The semiconductor device according to claim 7, further comprising a precharge circuit connected between the node and the data line. 13. The semiconductor device according to claim 12, further comprising a buffer connected between the node and the precharge circuit.