JPH07295946A - Information processor and data transfer method therefor - Google Patents

Abstract

PURPOSE:To accelerate data transfer between both devices by specifying a using area inside a shared memory shared by a host computer and an external storage device by at least one of both devices. CONSTITUTION:The shared memory 30 is provided between a disk device 12' and the host computer 11' incorporated in the host computer 11. A first shared memory access circuit 31 is provided between the shared memory 30 and the disk controller 23' of the disk device 12', a second shared memory access circuit 32 is installed between the CPU 15' of the host computer 11' and the shared memory 30 and the access circuits 31 and 32 are capable of specifying an area inside the shared memory 30. Also, data buses from the CPU 15' and the disk controller 23' are connected to a bus switching circuit 33 and the bus switching circuit 33 selectively transmits and receives data with the shared memory 30 corresponding to R/W signals from the CPU 15' and the disk controller 23'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a host computer and a storage device such as a hard disk, and to a data transfer method between the host computer and the storage device.

[0002]

2. Description of the Related Art Generally, some information processing apparatuses of this type have a host computer having a main memory and a central processing unit, and an external storage device such as a disk device. There is also a type in which this external storage device is integrated with a host computer in the form of a hard disk. In any case, the external storage device has an internal memory and an input / output control unit for controlling input / output to / from the internal memory in addition to the disk. In this case, the external storage device and the host computer are usually connected via an input / output interface such as an input / output port.

In an information processing apparatus having such an external storage device, it is necessary to transfer data mutually between the external storage device and the main memory of the host computer. In this data transfer, when data is transferred from the disk, which is the storage device of the external storage device, to the main memory of the host computer, the data stored in the disk is first transferred to the internal memory of the disk device and then Data is transferred from the memory to the main memory of the host computer again via the input / output interface. This means that the data transfer is performed in two stages.

On the other hand, when the data is transferred from the main memory of the host computer to the disk, the same path is used.
Staged data transfer is in progress.

On the other hand, Japanese Patent Publication No. 3-40,868 discloses that in order to transfer data to the main memory at high speed,
Disclosed is a computer system that is configured by a semiconductor memory and that has an extended storage device having an address space different from the address space of the main memory, and that directly transfers data between the extended storage device and the main memory. Has been done.

[0006]

The conventional information processing apparatus that transfers data in two stages as described above has a drawback that it takes time to transfer data because the transfer needs to be performed in two stages. Further, such a two-step data transfer has a drawback that a smooth moving image cannot be displayed when a large amount of data needs to be transferred between the main memory and the disk like moving image data.

Further, Japanese Patent Publication No. 3-4 provided with an extended storage device.
In the computer system described in Japanese Patent No. 0,868, address conversion is required at the time of data transfer between the main memory and the extended storage device, which is insufficient for high-speed data transfer. In addition, the CPU of the host computer cannot access the main memory until after the data transfer from the extended storage device or the main memory is completed.

[0008]

According to the present invention, an information processing apparatus including a host computer and an external storage device provided integrally with the host computer is shared by the host computer and the storage device. There is provided an information processing device comprising: a shared memory, and a designating unit that designates a use area in the shared memory by at least one of the host computer and the storage device.

[0009]

In the information processing apparatus having the above-described configuration, the shared memory bus-connected to the external storage device is provided, and the shared memory is divided into areas by using the memory window technique, and each area is divided into areas. On the other hand, the external storage device and the host computer can access each other individually, and by switching each area at high speed, data transfer between the external storage device and the host computer can be performed at high speed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an information processing apparatus according to an embodiment of the present invention, an example of a conventional information processing apparatus will be briefly described to facilitate understanding of the present invention.

The conventional information processing apparatus shown in FIG. 4 comprises a host computer 11 and a disk device 12 as an external storage device. Of these, the host computer 11 includes a central processing unit (CPU) 15 and a main memory 1.
6 and an input / output port 17. On the other hand, the illustrated disk device 12 has a disk 21, a head disk controller (HDC) 22, a disk controller (CPU) 23, a disk built-in memory 24, and an input / output port 25.

In FIG. 4, when data is transferred from the disk 21 of the disk device 12 to the main memory 16 of the host computer 11, the disk internal memory 24 is transferred from the disk 21 to the HDC 22 and the CPU 23 inside the disk device 12. First, the data is transferred.
Next, the data read from the disk built-in memory 24 is transferred to the main memory 16 in the host computer 11 via the input / output ports 25 and 17.

On the other hand, when transferring data from the main memory 16 to the disk 21, the data is once stored in the disk built-in memory 24 in the disk device 12 and then transferred to the disk 21. .

As described above, in the conventional information processing apparatus, since the transfer operation is performed in two stages, there is a drawback that it takes time to transfer the data, as described above.

Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention has a hard disk device as a disk device 12 'built in a host computer 11', and the disk device 12 'and the host shown in FIG. The shared memory 3 is used as an interface with the computer 11 '.
0 is provided. The shared memory 30 may be a part of the main memory in the host computer 11 'or the whole main memory. In any case, the shared memory 30 is the central processing unit (CP) of the host computer 11 '.
U) 15 'and the disk controller 23' of the disk device 12 'are bus-connected. The illustrated disk device 12 'also includes the disk 21 and the HDC 22 as in the case of FIG.

In the configuration shown, the shared memory 30 and
A first shared memory access circuit 31 is provided between the disk device 12 'and the disk controller 23', while the CPU 15 'of the host computer 11' is provided.
And the shared memory 30, the second shared memory access circuit 32 is installed.

Further, in the example of FIG. 1, the data bus from the CPU 15 'of the host computer 11' and the disk controller 23 'of the disk device 12' is the bus switching circuit 3.
3, the bus switching circuit 33 is connected to the CPU 15 '.
And the shared memory 3 selectively according to a read / write (R / W) signal from the disk controller 23 '.
Data shall be sent to and received from 0.

Referring to FIG. 1, the shared memory 30 may be logically or in address space partitioned, for example, into two regions A and B. The first shared memory access circuit 31, as shown by the broken line in FIG.
The two areas A and B are selectively accessible. More specifically, the first shared memory access circuit 31 can move an address on the shared memory 30 used by the disk device 12 ′ by forming a logically partitioned memory window. .

Referring also to FIG. 2, the address signal ad of the shared memory 30 is sent from the disk controller 23 'of the disk device 12' and the area A
Corresponding the start address of B and B to the memory window,
The designated offset address signal oa is supplied to the offset address register 311. The address signal ad and the offset address signal oa are added in the adder 312 and are given to the second shared memory access circuit 32 as the memory address signal adm.

The second shared memory access circuit 32 includes an address switching register 321 and an address switching circuit 322. Of these, the address switching register 321 is supplied with a selection signal from the CPU 15 ′ for instructing whether the shared memory 30 is to be allocated to the disk device 12 ′ or the host computer 11 ′, and on the other hand, to the address switching circuit 322. Is supplied with the address signal ad 'from the CPU 15'.

The address switching circuit 322 is a CPU 15 '.
From the first shared memory access circuit 31 and receives either the address signal ad 'or the memory address signal adm according to the selection signal given from the address switching register 321. Is sent to the shared memory 30.

As is apparent from the above, the first and second shared memory access circuits 31 and 32 operate as means for designating an area in the shared memory 30.

Now, assuming that the memory address signal adm is selected by the address switching circuit 322 and the write signal (W) is issued from the disk controller 23 'to the bus switching circuit 33, the disk device 12 The data from ′ is written to either the area A or B of the shared memory 30 corresponding to the memory address signal adm and designated in the form of the memory window. Disk device 12 'stored in shared memory 30
Since the data from the disk 15 can be directly accessed by the CPU 15 ', an effect substantially similar to that of the data from the disk 21 directly transferred to the main memory of the host computer 11 can be obtained. Also, when the read (R) signal is issued from the disk controller 23 ', the data is directly read from the memory window specified by the memory address signal adm and transferred to the disk device 12'.

On the other hand, the CPU 15 'has a bus switching device 33.
The shared memory 30 can be used in the same manner as the main memory via the, and data can be transferred between the shared memory 30 and the disk 21 as described above. in this case,
If the CPU 15 'and the disk controller 23' are configured to alternately access the shared memory 30 and use the areas A and B alternately, the host computer 11 'and the disk device 12' The data transfer between can be performed smoothly.

In the illustrated example, the bus switching circuit 3
3 and the case where the memory access circuits 31 and 32 are used, a dual port shared memory 30 is used to simultaneously access areas different from the CPU 15 'and the disk controller 23'. Possible configurations can be realized.

Referring to FIG. 3, an application example of the information processing apparatus according to the embodiment of the present invention is shown. Here, a host computer 11a, a disk device 12a, and a shared memory 30a provided between the two are shown. The shared memory 30a is provided with display memory areas V1 and V2 for repeating a large amount of data transfer between the host computer 11a and the disk device 12a. With this configuration,
Instead of rewriting the contents of the display memory frequently, CP
By changing the address of the memory window of U15a and the memory window of the disk controller 23a of the disk device 12a, the display is changed at high speed,
A moving image can be displayed smoothly.

Specifically, while the CPU 15a is writing the display data in the display memory area V1, the disk controller 23a is configured to read the display data from the display memory area V2 so that the disk 21 can be read. In contrast, display data can be transferred at high speed.

[0028]

According to the present invention, the CP of the host computer
Each of U and the disk controller of the disk device directly transfers the data to the shared memory, while the data in the shared memory can be directly read and supplied to the disk in the disk device. Has the advantage that it can be performed at high speed. Further, since the address on the shared memory that can be used by the disk device can be moved by the memory window, there is an advantage that the shared memory can be used flexibly.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an information processing apparatus according to an exemplary embodiment of the present invention.

FIG. 2 is a partial block diagram for explaining the information processing apparatus in FIG. 1 in more detail.

FIG. 3 is a schematic block diagram for explaining an application example of the information processing apparatus according to the present invention.

FIG. 4 is a block diagram for explaining data transfer in a conventional information processing device.

[Explanation of symbols]

11, 11 ', 11a Host computer 12, 12', 12a Disk device 15, 15 ', 15a CPU 16 Main memory 17 Input / output port 21 Disk 22 HDC 23, 23', 23a Disk controller (CPU) 24 Disk built-in memory 25 Input / output port 30 Shared memory 31 First memory access circuit 32 Second memory access circuit 33 Bus switching circuit

Claims (5)

[Claims] 1. An information processing apparatus including a host computer and a storage device provided integrally with the host computer, a shared memory shared by the host computer and the storage device, and use in the shared memory. An information processing apparatus comprising: a specifying unit that specifies an area by at least one of the host computer and the storage device. 2. The method according to claim 1, wherein the designating means moves the logically partitioned memory window by changing the address allocated to the used area in the shared memory. An information processing device characterized by being configured. 3. The display memory area according to claim 1, wherein the shared memory includes a display memory area for storing display data and another area, and the display data is rewritten from the CPU to the display memory area. The information processing apparatus, wherein the CPU and the storage device are stored as much as possible, and the CPU and the storage device alternately access the display memory area by the designating unit. 4. The information processing apparatus according to claim 1, wherein the storage device is a hard disk device. 5. A data transfer method for an information processing apparatus including a host computer and a storage device provided integrally with the host computer, wherein a shared memory shared by the host computer and the storage device is provided, A data transfer method for an information processing apparatus, wherein data is directly transferred between the host computer and the storage device via the shared memory.