JPH07290767A - Image processor - Google Patents

Abstract

PURPOSE:To suppress the deterioration of image quality and multiply addition data on an image so as to be inconspicuous. CONSTITUTION:Input image data are blocked into a 4mu4 pixel unit. The addition data inputted from an input terminal 107 is converted to a bit row and, when the values of respective bits are '0', the feed signal having + or -alpha amplitude from a feed signal generator 110 is not added to image data and, when the values of respective bits are '1', an adder 106 adds the same feed signal from the feed signal generator 110 to the image data corresponding to one block. This addition is performed over the whole of an input image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for superimposing other information on image data and outputting or transmitting it.

[0002]

2. Description of the Related Art When other information is directly multiplexed on an image,
The quality of the original image is greatly deteriorated by the information added by the multiplexing. In order to solve such a problem, for example, as disclosed in Japanese Patent Laid-Open No. 4-294682, human visual characteristics are used, and a specific pattern or specific color that is difficult for the human eye to identify is used. Attempts have been made to multiplex information.

[0003]

However, in the above-mentioned conventional example, in order to stably take out the added information from the recording paper on which the image in which the information is multiplexed is output, a very large modulation amount is applied to the original image. However, even if a pattern or color is difficult to visually recognize, the amount of modulation to be added is large, so that there is a problem that image quality deterioration cannot be avoided.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an image processing apparatus which suppresses image quality deterioration when other information is multiplexed on an image.

[0005]

In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, an image processing device capable of multiplexing additional information on image data, the first input means for inputting the image data,
The second input means for inputting the additional information, the modulating means for modulating the additional information with a predetermined carrier signal, and the modulation signal modulated by the modulating means for the image data input by the first input means. A plurality of pixels as a unit, adding means for adding to the image data signal,
The image processing device is characterized in that the modulation amount represented by the modulation signal is set to a small amount in accordance with the number of gradations that can be expressed in the image data.

[0006]

With the above structure, the input additional information is modulated by a predetermined carrier signal, and a small modulation amount considering the number of gradations that can be expressed in the image data is applied to the image data in units of a plurality of pixels. to add.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[Description of Common Apparatus (FIG. 1)] FIG. 1 is a block diagram showing an outline of the overall configuration of an image processing apparatus which is a typical embodiment of the present invention. In FIG. 1, 10 is an image input unit, which is composed of an image reading device such as an image scanner including a CCD sensor, an interface of an external device such as a host computer, an SV camera, and a video camera. The image data input from the image input unit 10 is
It is supplied to the input terminals 100 and 107 of the image processing unit 11. Reference numeral 12 is an operation unit for the operator to specify an output destination of image data, 13 is an output control unit, the former is for selecting the output destination of the image data, and the latter is a synchronizing signal for reading the image data (the printer engine together with the image output unit. For example, an ITOP signal from an output control unit constituting the unit or output of connection information according to an image output unit (printer resolution) from the image output unit or a manual key input from the operation unit is performed. Reference numeral 104 denotes an output terminal of the image processing unit 11. Reference numeral 14 is an image display unit such as a display, 15 is a communication unit that transmits and receives image data via a public line or LAN, and 16 is, for example, a latent image is formed by irradiating a laser beam on a photoconductor, and this is a visible image. It is an image output unit such as a laser beam printer.

The image output section 16 may be an ink jet printer, a bubble jet printer, a thermal transfer printer, a dot printer, or the like. Image data is input to the input terminal 100, and additional data of the image data input from the input terminal 100 is input to the input terminal 107.

Some embodiments of the image processing unit 11 will be described below.

[First Embodiment (FIGS. 2 to 3)] FIG. 2 is a block diagram showing the schematic arrangement of the image processing unit 11 according to the present embodiment. In FIG. 1, reference numeral 102 denotes an image signal processing circuit that performs predetermined image processing on input image data from the input terminal 101, 103 denotes a switch for switching a signal to the output terminal 104, and 105 denotes image data from the image signal processing circuit 102. A blocker for converting the permutation, 106 is an adder for adding the input data from the blocker 105 and the input data from the multiplier 109, and 108 is additional data (parallel data) from the input terminal 107 to serial data. It is a parallel-to-serial converter that converts. 109 is a multiplier for multiplying the data from the parallel / serial (P / S) converter 108 by the data from the carrier signal generator 110;
Reference numeral 10 is a carrier signal generator for generating a signal for multiplexing the additional data as a spatial spectrum on the original image. The details of this signal will be described later. 111 is an adder 106
It is a rasterizer that converts the permutation of the image data from to the raster scan that is the original data sequence.

Next, the image processing unit 11 having the above configuration
The operation of will be described.

(1) When the additional data is not multiplexed Image data is input from the input terminal 101 to the image signal processing circuit 1
It is input to 02. The image signal processing circuit 102 performs various pre-processing such as color conversion on the image data in accordance with the characteristics of the printer engine (which is composed of the output control unit 13 and the image output unit 16), and outputs it to the a terminal of the switch 103. Output. The output of the image signal processing circuit 102 is also output to the blocker 105 at the same time. The switch 103 has a function of controlling whether or not additional data is added to the image,
When the switch is connected to the a terminal side, the data of the image signal processing circuit 102 is output to the printer engine as an output terminal 104.
Output directly from.

The printer engine forms an image from the input image data and outputs it. Thus, when the additional data is not multiplexed on the image, the switch 103 is always connected to the a terminal side.

(2) When additional data is multiplexed into an image As described above, the output of the image signal processing circuit 102 is also input to the blocker 105, and the blocker 105 outputs from the image signal processing circuit 102. The permutation of the image data is rearranged into blocks of a predetermined size. The blocked image data is output to the a-side input terminal of the adder 106.

On the other hand, the additional data is input as parallel data from the input terminal 107. The input parallel data is converted into a serial data string by the parallel / serial converter 108 and input to the a-side input terminal of the multiplier 109. The output signal from the carrier signal generator 110 is input to the input terminal on the b side of the multiplier 109, and the multiplier 109 multiplies these two signals and outputs it to the input terminal on the b side of the adder 106. A spatial spectrum conversion on the original image is performed by the multiplication by the multiplier 109.

The adder 106 adds the image data from the blocker 105 and the data of the multiplication result from the multiplier 109 and outputs the result to the rasterizer 111. By this addition, the additional data is added to the original image.

In the rasterizer 111, the blocker 10
The permutation of the image data blocked in 5 is returned to the original raster scan order. The output of the rasterizer 111 is connected to the b terminal of the switch 103, and when the additional data is multiplexed, the switch 103 selects the b terminal. As a result, the data from the rasterizer 111 is input to the printer engine and printed out.

The operation of multiplexing the additional data with the image data will be described in detail with reference to FIG. In FIG. 3, one cell represents one pixel of the image, and when the image is formed by the printer engine in the horizontal direction, the main scanning direction of the printer engine is the vertical direction and the sub-scanning direction is the vertical direction. Here, the main scanning direction is, for example, if the printer engine follows the laser beam method,
The scanning direction of the laser light when the laser light whose beam width is controlled by the image data scans the photosensitive drum, and the sub-scanning direction means the rotation direction of the photosensitive drum.

The blocker 105 has 4 pixels in the main scanning direction,
The permutation of the input image data is converted so that a total of 16 pixels of 4 pixels in the sub-scanning direction constitute one block. Therefore, the adder 106 and the multiplier 109 process the image data in units of 4 × 4 pixels, and one bit of additional data is additionally multiplexed for each block.

First, a case where 1 bit of additional data having a bit value of "1" is multiplexed will be described.

In this embodiment, the carrier signal generator 110 is
A signal corresponding to a certain spatial spectrum in the image space, which changes from + α to −α for each pixel (this is called a carrier signal), is generated. The multiplier 109 multiplies the carrier signal by the output data “1” from the P / S converter 108, and inputs the multiplication result to the adder 106. As a result, the adder 10
The output signal from 6 becomes an image signal as shown in block 31 of FIG. Here, “+ α” indicates that + α is added to the pixel value of the original image, and similarly, “−α” indicates that −α is added. When the same process is performed on 1 bit of additional data having a bit value of "0", the image signal as shown in block 32 of FIG. Will be output. Such addition processing is performed over the entire surface of the input image, and as a result, the additional information is periodically multiplexed on the image in the main scanning direction and / or the sub scanning direction.

Although one block has been described as having a 4 × 4 pixel configuration, it goes without saying that the present invention is not limited to this. Of course, it is possible to increase or decrease the number of pixels per block. However,
If the number of pixels per block is reduced, more data can be multiplexed, but since the area (the number of pixels) expressing 1 bit becomes small, if the surface of the print output is damaged or soiled, The data is lost and it becomes difficult to stably decode the multiplexed signal. On the contrary, if the number of pixels per block is increased, the multiplexed signal can be stably decoded, but the amount of data that can be added decreases. Therefore,
It is necessary to take a balanced pixel configuration in consideration of both advantages and disadvantages.

Further, if the value of ± α is increased, the stability at the time of decoding is increased, and conversely, if it is decreased, the stability is decreased, but the deterioration of the image quality can be suppressed accordingly. “± α” is
This is the amount of modulation with respect to the original image, but the gradation that can be expressed by the original image is such that the deterioration of image quality does not become noticeable by this addition, or the modulated signal does not appear noticeably on the original image. It goes without saying that the value is set to a sufficiently small value in consideration of the characteristics such as the number and the printer engine.

In any case, the above-mentioned various values may be optimized in accordance with the characteristics of the printer engine that performs image forming output and the human visual characteristics.

The multiplexing of the additional data obtained by the multiplier 109 into the image data as described above is performed by the multiplier 10
The output of 9 does not have to be input to the adder 106. For example, as in the modified example shown in FIG. 4, the output of the multiplier 109 is input to the rasterizer 111, the data generated on the assumption that the image data is divided into blocks is converted into data of a raster scan format, and By inputting the output to the adder 106 and taking the sum with the image data, the additional data can be directly multiplexed with the original image. In this case, the blocker 105 can be omitted from the image processing unit,
This will contribute to simplification of the device configuration.

Therefore, according to this embodiment, since the additional data is multiplexed on the image data only by adding a minute amount of pixel value of the information of one bit of the additional data to the data of a plurality of pixels, the entire image As a result, it becomes possible to add other information to the image data while suppressing the deterioration of the image quality as much as possible.

[Second Embodiment (FIGS. 5 to 7)] FIG. 5 is a block diagram showing the schematic arrangement of the image processing section 11 according to the present embodiment. In FIG. 5, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 5, 201 is a parallel serial (P /
S) A level converter that inputs a signal from the converter 108, performs level conversion described later, and outputs the level to the multiplier 109.

The operation characteristic of this embodiment will be described below.

The level converter 201 is the P / S converter 10
Each bit of the additional data input from 8 is checked, and if the value is "1", the signal is output to the multiplier 109 as it is, and if the value is "0", the signal is set to "-1". It is converted and output to the multiplier 109. Therefore, the multiplier 109
When the carrier signal generator 110 inputs the carrier signal similar to that of the first embodiment and performs multiplication, the output of the multiplier 109 is output from the carrier signal generator 110 when the value of the additional data is "1". The carrier signal remains as it is, and when the value of the additional data is "0", the inverted signal of the carrier signal from the carrier signal generator 110 is output.

As described above, when the signal output from the multiplier 109 is input to the adder 106 and added to the blocked image data, the output result from the adder 106 is as shown in FIG. Become. In FIG. 6, block 6
1 is the output result when the value of the additional data is "1", and block 62 is the output result when the value of the additional data is "0".
As shown in this figure, it can be seen that the phase of the spatial carrier signal composed of "+ α" and "-α" is different when the value of the additional data is "0" and "1". Note that FIG.
The meaning of one mesh and the main scanning direction and the sub-scanning direction shown in (4) are the same as in the first embodiment.

Therefore, according to this embodiment, when the value of the additional data is "0" in the first embodiment, the original image is output as it is, whereas in this embodiment the carrier signal from the carrier signal generator 110 is output. The phase of can be changed from that of the case where the additional data is "1" and multiplexed with the original image. This makes it possible to add other information to the image data while suppressing the deterioration of the image as much as possible.

A technique for changing the phase of a carrier signal in multiplexing such additional data with image data is shown in FIG.
Not only the configuration shown in FIG. 7 but also an image processing unit having a configuration shown in FIG.

FIG. 7 is a block diagram showing the arrangement of an image processing unit which is a modification of the second embodiment. In FIG. 7, the first
The same components as those in the first to second embodiments are designated by the same reference numerals. Here, only the characteristic components of the modification and the operation thereof will be described.

In FIG. 7, 202 is a carrier signal generator 1.
A phase converter that functions to change the phase of the carrier signal that is the output from 10; specifically, a phase converter that converts + α to −α and −α to + α; 203 denotes a carrier signal from the carrier signal generator 110; The signal from the phase converter 203 and the adder 106 are switched according to the additional data from the P / S converter 108.
It is a switch that outputs to. The switch 203 selects the terminal a when the bit value of the additional data is “1” and outputs the carrier signal from the carrier signal generator 110 to the adder 106, and the bit value of the additional data is “0”. At time, the terminal b is selected, and the carrier signal phase-converted by the phase converter 202 is output to the adder 106.

As a result, the output of the adder 106 becomes as shown in FIG. 6 according to the value of the additional data.

[Third Embodiment] FIG. 8 is a block diagram showing the schematic arrangement of an image processing unit 11 according to this embodiment. 5, the same components as those described in the first and second embodiments are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 8, reference numeral 301 is a carrier signal generator for generating a carrier signal having a cycle different from that of the carrier signal generator 110 used in the first and second embodiments. The period of the carrier signal from carrier signal generator 301 is an integral multiple of that from carrier signal generator 110.

The operation characteristic of this embodiment will be described below.

The switch 203 selects the a terminal when the bit value of the additional data is "1" and the b terminal when the bit value of the additional data is "0". Therefore, the value of the bit of the additional data is selected. Is "1", the carrier signal of the carrier signal generator 110 is added to the original image, while when the bit value of the additional data is "0", the carrier signal of the carrier signal generator 301 is added to the original image. .

The image data to which the carrier signals have been added by the adder 106 in this way is as shown in FIG. As is apparent from blocks 91 and 92 in this figure, the phase of the spatial carrier signal composed of "+ α" and "-α" is different when the value of the additional data is "0" and "1". I understand. It should be noted that the meaning of one mesh and the main scanning direction and the sub scanning direction shown in FIG. 9 is the same as in the first embodiment.

Therefore, according to the present embodiment, two different periods are used.
It is possible to multiplex the additional data with the image data while using one carrier signal to switch the carrier signal according to the value of the additional data. This makes it possible to add other information to the image data while suppressing the deterioration of the image as much as possible.

In this embodiment, two carrier signal generators are used to generate two carrier signals having different periods, but the present invention is not limited to this. For example, as shown in FIG. 10, two carrier signals having different periods are generated by using one carrier signal generator and one frequency divider, and the same operation as that of the present embodiment is performed to obtain the same effect. Obtainable.

FIG. 10 is a block diagram showing the arrangement of an image processing unit which is a modification of the third embodiment. In FIG.
The same components as those in the first to third embodiments are designated by the same reference numerals. Here, only the characteristic components of the modification and the operation thereof will be described.

In FIG. 10, reference numeral 304 is a frequency divider that divides the carrier signal from the carrier signal generator 110 and outputs it to the b terminal of the switch 203. The frequency divider 304 outputs a carrier signal having a cycle obtained by multiplying the cycle of the carrier signal output from the carrier signal generator 110 by n (n is an integer).

In this embodiment, the carrier signal has two spatial frequencies, but the present invention is not limited to this, and it is sufficient if it is two or more. Further, in this embodiment, as is apparent from FIG. 9, the case where the period of the carrier signal in both the main scanning direction and the sub scanning direction is changed has been described, but the period may be changed in only one direction.

[Fourth Embodiment (FIGS. 11 to 13)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. In FIG. 11, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 11, reference numeral 401 denotes a level converter that inputs a signal from the parallel / serial (P / S) converter 108, performs level conversion described later, and outputs the level to the multiplier 109.

The operation characteristic of this embodiment will be described below.

The level converter 401 is a P / S converter 10.
Each bit of the additional data input from 8 is checked, and if the value is "1", the value of the output signal becomes "2",
When the value is “0”, the output signal is level-converted to be “1” and output to the multiplier 109.

Therefore, the multiplier 109 makes the carrier signal generator 1
When a carrier signal similar to that in the first embodiment is input from 10 and multiplication is performed, the output of the multiplier 109 is 2 times the carrier signal from the carrier signal generator 110 when the value of the additional data is "1".
The signal has a doubled amplitude, and when the value of the additional data is "0", the carrier signal from the carrier signal generator 110 is output as it is.

As described above, when the signal output from the multiplier 109 is input to the adder 106 and added to the blocked image data, the output result from the adder 106 is as shown in FIG. Become. In FIG. 12, a block 1201 outputs the result when the value of the additional data is “0”,
A block 1202 is an output result when the value of the additional data is "1". As shown in this figure, when the value of the additional data is “0”, the spatial carrier signal composed of “+ α” and “−α” is “+ 2α” when the value of the additional data is “1”. It can be seen that the spatial carrier signal composed of "-2α" is added to the image data. In addition,
The meanings of one mesh and the main scanning direction and the sub scanning direction shown in FIG. 12 are the same as those in the first embodiment.

Therefore, according to the present embodiment, when the value of the additional data is "0" in the first embodiment, the original image is output as it is, but in the present embodiment, the carrier signal generator according to the value of the additional data. The amplitude of the carrier signal from 110 can be varied and multiplexed onto the original image. This makes it possible to add other information to the image data while suppressing the deterioration of the image as much as possible.

In this embodiment, the change in the amplitude of the carrier signal is realized by the level converter and the adder, but the present invention is not limited to this. For example, in FIG.
As shown in FIG. 3, the carrier signal output from the carrier signal generator is amplified by an amplifier, and the carrier signal amplified according to the value of the additional data and the carrier signal itself are switched by a switch, so that the same effect as the present embodiment is obtained. Can be obtained.

FIG. 13 is a block diagram showing the arrangement of an image processing section which is a modification of the fourth embodiment. In FIG.
The same components as those in the first and second embodiments are designated by the same reference numerals. Here, only the characteristic components of the modification and the operation thereof will be described.

In FIG. 13, reference numeral 403 denotes an amplifier for doubling the amplitude of the carrier signal output from the carrier signal generator 110, specifically, amplifying + α to + 2α and -α to -2α.

Furthermore, in the present embodiment, an example in which the amplitude of the carrier signal is doubled has been described, but the present invention is not limited to this, and the possible values are also 2.
The value is not limited to n and may be n (n is an integer).

[Fifth Embodiment (FIGS. 14 to 16)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. In FIG. 14, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 14, 501 is a bit width converter for inputting additional data and outputting it to the PWM modulator 503.
2 is a frequency divider that divides the carrier signal from the carrier signal generator 110; 503 is a PWM that PWM-modulates the frequency-divided carrier signal that is output from the frequency divider 503 according to the output signal from the bit width converter 501. It is a modulator.

The operation characteristic of this embodiment will be described below.

In the bit width converter 501, for every 2 bits of the input additional data, the signal pulse width representing the 2 bits corresponds to the signal width representing 4 pixels of the image data input from the input terminal 101. The bit width is adjusted so that it is converted into a 4-level level signal according to the value (0, 1, 2, 3) represented by the 2-bit data, and the level signal is output to the PWM modulator 503. On the other hand, the frequency divider 502
Divides the carrier signal output from the carrier signal generator 110 and outputs a triangular wave signal having a cycle corresponding to 2 bits of input additional data to the PWM modulator 503. PWM modulator 5
Reference numeral 03 denotes a pulse signal in which the level signal from the bit width converter 501 and the triangular wave signal from the frequency divider 502 are input to perform PWM modulation, and the value of every 2 bits of input additional data is reflected in the pulse width (the value is 0 or 1) is output to the multiplier 109.

The multiplier 109 multiplies the carrier signal and the pulse signal and outputs the output to the adder 106. Therefore,
The output signal of the multiplier 109 is a signal that reflects the value of every 2 bits of input additional data. That is, the carrier signal is not output while the pulse signal represents "0", and the value (amplitude) as shown in the first embodiment while the pulse signal represents "1". A carrier signal with is output.

As a result, the image signal output from the adder 106 is multiplexed in which the value of each 2 bits of the input additional data is reflected, and the modulation signal as shown in FIG. 15 is added to each block. become.

Therefore, according to the present embodiment, as is apparent from FIG. 15, the carrier signal from the carrier signal generator 110 is area-modulated according to the value of every 2 bits of the additional data, and the carrier signal is generated for the image data of each block. The information represented by the additional data can be multiplexed with the original image by changing the area to be added. By thus adding the additional data to the image data, the addition of the additional data becomes inconspicuous, so that it is possible to add other information to the image data while suppressing the deterioration of the multiplexed image as much as possible. It will be possible.

In this embodiment, as shown in FIG.
The block is composed of 4 pixels in the main scanning direction and 4 pixels in the sub scanning direction for a total of 16 pixels, and the area modulation is performed so that the value of every 2 bits of additional data can be expressed in units of 16 pixels. Is not limited by this. For example, as shown in FIG. 16, one block is composed of 6 pixels in the main scanning direction and 2 pixels in the sub scanning direction, that is, 12 pixels in total, and a value for every 2 bits of additional data can be expressed in units of the 12 pixels. Carrier signals may be added so that area modulation can be performed.

The method of constructing such one block may be determined in consideration of various characteristics of the printer engine and the like as described in the first embodiment.

In the present embodiment, the original image is output as it is when the value of each additional data of 2 bits is "0". However, the present invention is not limited to this and the second to fourth It is also possible to add carrier signals by the method as described in the embodiment.

[Sixth Embodiment (FIGS. 17 to 18)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. In FIG. 17, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 17, reference numeral 601 denotes a bit width converter for inputting additional data and outputting it to the FSK modulator 603.
Reference numeral 2 is a frequency divider for dividing the frequency of the carrier signal from the carrier signal generator 110, and 603 is FSK for performing FSK modulation on the frequency-divided carrier signal output from the frequency divider 603 according to the output signal from the bit width converter 601. It is a modulator.

The operation characteristic of this embodiment will be described below.

The bit width converter 601 converts the signal pulse width representing the value (0, 1) of each bit of the input additional data into the signal width representing 16 pixels of the image data input from the input terminal 101. The bit width is converted so as to be equivalent and output to the FSK modulator 603. On the other hand, the frequency divider 602 divides the frequency of the carrier signal output from the carrier signal generator 110, and a frequency signal (f ₁ ) that has one cycle for 16 pixels of the input image data and a frequency signal (f ₁ ) that has two cycles. f ₂ ) to F
Output to the SK modulator 603. The FSK modulator 603 is
The bit width converted signal from the bit width converter 601 and the two frequency signals from the frequency divider 602 are input to FSK.
Modulation is performed, and a frequency signal (f ₁ or f ₂ ) in which the value of each bit of the input additional data is reflected in the frequency is output to the multiplier 109.

The multiplier 109 multiplies the carrier signal and the frequency signal and outputs the output to the adder 106. Therefore,
The output signal of the multiplier 109 is a signal that reflects the value of each bit of input data. That is, for each bit of the input additional data, if the value is “0”, the carrier signal is turned on / off at the frequency (f ₁ ). On the other hand, if the bit value is “1”, the carrier signal is at the frequency. ON at (f ₂ ).
The signal turns off. As a result, the adder 10
The image signal output from 6 is multiplexed in which the value of each bit of input additional data is reflected in every 16 pixels in the main scanning direction, and each block (1801 to 1803 in FIG. 18).
With respect to, the modulation signals as shown in FIG. 18 are added.

Therefore, according to the present embodiment, as is apparent from FIG. 18, in the multiplexing of the additional data according to the present embodiment, the carrier signal is added to the original image at the frequency reflecting the value of the additional data in the main scanning direction. be able to.

In the present embodiment, the carrier signal is added to the original image at the frequency reflecting the value of the additional data in the main scanning direction, but the present invention is not limited to this, and for example, sub-scanning The above-described multiplexing may be performed in the direction or in both the main / sub-scanning directions.

The method of constructing one block may be determined in consideration of various characteristics of the printer engine and the like as described in the first embodiment.

[Seventh Embodiment (FIGS. 19 to 20)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. In FIG. 19, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 19, reference numeral 701 denotes the carrier signal generator 1
702 is a P / S frequency divider for dividing the carrier signal from 10
PSK for PSK-modulating the frequency-divided carrier signal output from the frequency divider 603 according to the output signal from the converter 108.
It is a modulator.

The operation characteristic of this embodiment will be described below.

The frequency divider 701 divides the frequency of the carrier signal output from the carrier signal generator 110 to generate a frequency signal (f ₀ ) having one cycle for 8 pixels of the input image data, and the PSK modulator 70.
Output to 2. The PSK modulator 702 is the P / S converter 1
The bit data from 08 and the frequency signal from the frequency divider 701 are input for PSK modulation, and the frequency signal in which the value of each bit of the input additional data is reflected in the phase of the signal is output to the multiplier 109.

The multiplier 109 multiplies the carrier signal and the frequency signal and outputs the output to the adder 106. Therefore,
The output signal of the multiplier 109 is a signal that reflects the value of each bit of input data. That is, for each bit of the input additional data, if the value is "0", the carrier signal is turned ON / OFF by the frequency signal (f ₀ ), while if the bit value is "1", the carrier signal is A signal obtained by shifting the phase of the frequency signal (f ₀ ) by 180 ° becomes a signal that is turned on / off. As a result, the image signal output from the adder 106 is multiplexed in which the value of each bit of input additional data is reflected in every 8 pixels in the main scanning direction, and the modulated signal as shown in FIG. (2001 to FIG. 20
2006) will be added.

Therefore, according to the present embodiment, as is apparent from FIG. 20, in the multiplexing of the additional data according to the present embodiment, the carrier signal is added to the original image in the phase reflecting the value of the additional data in the main scanning direction. be able to.

In the present embodiment, the carrier signal is added to the original image in the phase reflecting the value of the additional data in the main scanning direction, but the present invention is not limited to this.
For example, the above multiplexing may be performed in the sub-scanning direction or in both the main / sub-scanning directions.

The method of constructing one block may be determined in consideration of various characteristics of the printer engine and the like as described in the first embodiment.

[Eighth Embodiment (FIGS. 21 to 22)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. 21, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 21, reference numeral 801 denotes a bit width converter for inputting additional data, performing the conversion processing described below, and outputting the converted signal to a level converter 802.
Is a level converter for converting the level of the output signal from the bit width converter 801.

The operation characteristic of this embodiment will be described below.

The bit width converter 801 converts the signal pulse width representing the value (0, 1) of each bit of the input additional data into the signal width representing two pixels of the image data input from the input terminal 101. The bit width is converted so as to be equivalent and output to the level converter 802. On the other hand, the level converter 80
2 is a value (0, 0) represented by the 2-bit data for every 2 bits of the input additional data whose bit width has been converted.
According to 1, 2, 3), four level signal levels (1, -1,
2 and -2) and output to the multiplier 109.

Multiplier 109 multiplies the carrier signal and the level-converted signal and outputs the output to adder 106. Therefore, the output signal of the multiplier 109 is a signal that reflects the value of every 2 bits of input additional data. That is, when the value represented by the 2-bit data is 0, 1, 2, or 3, the output signal of the multiplier 109 is the carrier signal as it is, an inverted carrier signal, a carrier signal having a double amplitude, and The result is an inverted carrier signal with twice the amplitude.

As a result, the image signal output from the adder 106 is multiplexed in which the value of every 2 bits of input additional data is reflected, and the modulated signal as shown in FIG. 2206) will be added.

Therefore, according to this embodiment, as is apparent from FIG. 22, the carrier signal from the carrier signal generator 110 is controlled so as to change its amplitude and phase according to the value of every 2 bits of the additional data, The information represented by the additional data can be multiplexed with the original image. By thus adding the additional data to the image data, the addition of the additional data becomes inconspicuous, so that it is possible to add other information to the image data while suppressing the deterioration of the multiplexed image as much as possible. It will be possible.

The method of constructing such one block may be determined in consideration of various characteristics of the printer engine as described in the first embodiment, and is not limited to the one described in this embodiment. .

[Ninth Embodiment (FIGS. 23 to 24)] FIG.
FIG. 3 is a block diagram showing a schematic configuration of an image processing unit 11 according to the present embodiment. In FIG. 23, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 23, 901 is a data bit map that temporarily stores a bit pattern that reflects each bit value of additional data, and 902 is a modulation bitmap that stores a bit pattern that serves as basic data for modulating the additional data. .

The operation characteristic of this embodiment will be described below.
This will be described with reference to FIG.

The modulation bit map 902 stores a bit pattern having a specific frequency to be modulation data for multiplexing additional data with image data. On the other hand, according to the value of each bit of the input additional data, the data bit map stores a bit pattern reflecting the value. Such two pieces of data are multiplied by the multiplier 109, and the multiplication result is output to the adder 106.

Therefore, if the concept described in the first embodiment is applied, for example, the multiplier 109 can express a bit pattern of modulated data of 10 bits × 10 bits as shown in FIG. For example, if each bit value of the input additional data is “1”, the bit pattern as it is is output to the adder 106, and if the bit value is “0”, all of the modulation data 10 bits × 10 bits are “0”. The resulting bit pattern is output to the adder 106. The output pattern reflecting the value of each bit of the additional data from the multiplier 109 is not limited to the method described here. For example, if the bit value is “0”, the output pattern is inverted when the bit value is “1”. Various methods such as using a pattern as an output pattern can be applied.

Further, when multiplexing with the image data in the adder 106, as shown in FIG. 24, in order to make it easy to detect the additional data at the time of demodulating the image data,
A mark block having a specific pixel value is added at a predetermined cycle in the sub-scanning direction.

By repeating the processing described above in the main scanning direction and the sub scanning direction, the information indicated by the additional data and the mark block are multiplexed over the entire surface of the original image.

As described above, according to the present embodiment as well, by adding the additional data to the image data, the addition of the additional data becomes inconspicuous. Therefore, deterioration of the multiplexed image is suppressed as much as possible, and It is possible to add other information to.

In the first to ninth embodiments described above, the printer engine outputs the multiplexed image information, but the present invention is not limited to this. A device for recording or transmitting an image, such as a still video camera or various VTRs can be used as the output device.

The information to be added is not particularly limited and may be any information. For example, in the case of a full-color printer device, it is effective to add a printed device or a date to prevent forgery of securities and bills. Further, if it is a still video or the like, the date, place, comment, etc. of the image can be added.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0096]

As described above, according to the present invention, the input additional information is modulated by a predetermined carrier signal, and a small modulation amount in consideration of the number of gradations that can be expressed in the image data is set to a plurality of input image data. Since the pixel is added as a unit to the image data, there is an effect that the additional information can be multiplexed in the image without causing a significant deterioration in image quality due to the addition. Further, since the amount of added modulation is small, there is an advantage that the confidentiality of the additional information is high and the data multiplexed by a third party is not known. Further, by multiplexing the additional information on the entire surface of the image, the additional information can be restored from any area of the image.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the overall configuration of an image processing apparatus that is a representative embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an image processing unit 11 according to the first embodiment.

FIG. 3 is a diagram showing an outline of additional data multiplexing processing according to the first embodiment.

FIG. 4 is a block diagram showing a schematic configuration of an image processing unit 11 which is a modified example of the first embodiment.

FIG. 5 is a block diagram showing a schematic configuration of an image processing unit 11 according to a second embodiment.

FIG. 6 is a diagram showing an outline of additional data multiplexing processing according to the second embodiment.

FIG. 7 is a block diagram showing a schematic configuration of an image processing unit 11 which is a modified example of the second embodiment.

FIG. 8 is a block diagram showing a schematic configuration of an image processing unit 11 according to a third embodiment.

FIG. 9 is a diagram showing an outline of multiplexing processing of additional data according to the third embodiment.

FIG. 10 is a block diagram showing a schematic configuration of an image processing unit 11 which is a modified example of the third embodiment.

FIG. 11 is a block diagram showing a schematic configuration of an image processing unit 11 according to a fourth embodiment.

FIG. 12 is a diagram showing an outline of additional data multiplexing processing according to the fourth embodiment.

FIG. 13 is a block diagram showing a schematic configuration of an image processing unit 11 which is a modified example of the fourth embodiment.

FIG. 14 is a diagram showing a schematic configuration of an image processing unit 11 according to a fifth embodiment.

FIG. 15 is a diagram showing an outline of additional data multiplexing processing according to the fifth embodiment.

FIG. 16 is a diagram showing an outline of a multiplexing process of additional data according to a modification of the fifth embodiment.

FIG. 17 is a diagram showing a schematic configuration of an image processing unit 11 according to a sixth embodiment.

FIG. 18 is a diagram showing an outline of a multiplexing process of additional data according to the sixth embodiment.

FIG. 19 is a diagram showing a schematic configuration of an image processing unit 11 according to a seventh embodiment.

FIG. 20 is a diagram showing an outline of additional data multiplexing processing according to the seventh embodiment.

FIG. 21 is a diagram showing a schematic configuration of an image processing unit 11 according to an eighth embodiment.

FIG. 22 is a diagram showing an outline of additional data multiplexing processing according to the eighth embodiment.

FIG. 23 is a diagram showing a schematic configuration of an image processing unit 11 according to a ninth embodiment.

FIG. 24 is a diagram showing a multiplexing process of additional data according to the ninth embodiment.

[Explanation of symbols]

 11 image processing unit 13 output control unit 16 image output unit 100, 107 input terminal 102 image signal processing circuit 103, 203 switch 104 output terminal 105 blocker 106 adder 109 multiplier 110, 301 carrier signal generator 111 rasterizer 201, 401, 802 Level converter 202 Phase converter 304, 502, 602, 701 Frequency divider 403 Amplifier 501, 601, 801 Bit width converter 503 PWM modulator 603 FSK modulator 702 PSK modulator 901 Data bit map 902 Modulation bit map

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location // G06T 5/00 G06F 15/68 320 A

Claims (17)

[Claims] 1. An image processing device capable of multiplexing additional information on image data, comprising: first input means for inputting the image data; second input means for inputting the additional information; Modulating means for modulating with a predetermined carrier signal, and the modulating signal modulated by the modulating means,
A plurality of pixels of the image data input by the input unit as a unit, and an addition unit that adds to the image data signal, and the modulation amount represented by the modulation signal is in accordance with the number of gray scales that can be expressed by the image data. An image processing device characterized by a small amount. 2. The image processing apparatus according to claim 1, further comprising an image forming unit that forms and outputs an image based on an output signal from the adding unit. 3. The image processing apparatus according to claim 2, wherein the image forming unit includes a printer engine of a laser beam system or a printer engine of an inkjet system. 4. The bit string generation means for generating a bit string representing the additional information based on the additional information input by the second input means, and the value of the bit generated by the bit string generation means. The image processing apparatus according to claim 1, further comprising: a modulation control unit that controls the modulation by the predetermined carrier signal. 5. The modulation control means includes an inversion signal generation means for generating an inversion signal of the predetermined carrier signal according to a value of a bit generated by the bit string generation means. The image processing device described. 6. The modulation control means further comprises a selection means for selecting the predetermined carrier signal or an inversion signal of the predetermined carrier signal according to a value of a bit generated by the bit string generation means. The image processing apparatus according to claim 5, characterized in that 7. The modulation control means includes amplification signal generation means for generating a signal in which the amplitude of the predetermined carrier signal is amplified according to the value of the bit generated by the bit string generation means. The image processing apparatus according to claim 4. 8. The selection control means selects the predetermined carrier signal or a signal obtained by amplifying the amplitude of the predetermined carrier signal according to the value of the bit generated by the bit string generation means. The image processing apparatus according to claim 7, further comprising: 9. The modulation control means includes phase shift signal generation means for generating a signal obtained by shifting the phase of the predetermined carrier signal by a predetermined amount according to the value of the bit generated by the bit string generation means. The image processing apparatus according to claim 4, which is characterized in that. 10. The modulation control means selects either the predetermined carrier signal or a signal obtained by shifting the phase of the predetermined carrier signal by a predetermined amount according to the value of the bit generated by the bit string generation means. The image processing apparatus according to claim 9, further comprising means. 11. The modulation control means includes secondary carrier signal generation means for generating another carrier signal having a frequency different from that of the predetermined carrier signal according to the value of the bit generated by the bit string generation means. The image processing device according to claim 4, wherein 12. The modulation control means selects the predetermined carrier signal or another carrier signal having a frequency different from that of the predetermined carrier signal according to a value of a bit generated by the bit string generation means. The image processing apparatus according to claim 11, further comprising selection means for performing the selection. 13. The pulse width modulation means for generating a pulse signal corresponding to a value represented by the plurality of bits in units of a plurality of bits generated by the bit string generation means, and the pulse signal. 5. The image processing apparatus according to claim 4, further comprising: a modulation signal generation unit that generates a modulation signal representing the additional information in units of the plurality of bits in accordance with the predetermined carrier signal. 14. The modulation control means, according to the frequency modulation means for generating a frequency modulation signal corresponding to the value of the bit generated by the bit string generation means, the frequency modulation signal and the predetermined carrier signal,
The image processing apparatus according to claim 4, further comprising a modulation signal generation unit that generates a modulation signal representing the additional information. 15. The modulation control means, in accordance with the phase modulation means for generating a phase modulation signal corresponding to a bit value generated by the bit string generation means, and the phase modulation signal and the predetermined carrier signal. The image processing apparatus according to claim 4, further comprising: a modulation signal generation unit that generates a modulation signal representing additional information. 16. The first input means includes a first storage means for storing the additional information as a bit pattern, and the modulation means stores a basic bit pattern expressing the predetermined carrier signal. Means, and a bit pattern generation means for generating a new pattern from the basic bit pattern according to each bit value of the bit pattern stored in the first storage means, the addition means including the new pattern The image processing apparatus according to claim 1, wherein the image processing apparatus adds the image data signal as a modulation signal. 17. The image processing apparatus according to claim 16, wherein the bit pattern generation means generates a specific pattern that does not depend on the additional information at a predetermined cycle.