JPH07287700A - Computer system - Google Patents

Abstract

PURPOSE: To allow the computer to act like an SIMD mode processor with high floating decimal point precision by decoding an SIMD command in a picket and processing an SIMD with an array of processors able to execute data in parallel. CONSTITUTION: In order to conduct inter-communication of data and instructions, a plurality of array processing elements 406 coupled as a picket 100 are provided. Each picket 100 has a plurality of devices to conduct various execution capability and each picket 100 acquires various modes to execute data in each picket 100 depending on the execution capability. Then each picket 100 decodes an SIMD command to execute SIMD processing by the array 406 of the processor executing data in parallel. Thus, the computer acts like the SIMD mode processor having high floating decimal point precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computers and computer systems, and in particular to SIMIMD herein having an array of processors and an array formed from pickets with local autonomy.
An array of processors that can function as a machine, called a machine, and execute an array of data.

[0002]

2. Description of the Related Art First, terms used in this specification will be described.

ALU ALU is the arithmetic logic unit of the processor.

Array An array refers to an array of elements in one or more dimensions. An array can include an ordered set of data items (array elements), but in languages such as FORTRAN, those data items are identified by a single name. In other languages, the name of an ordered set of data items refers to an ordered set of data elements that all have the same attributes. In program arrays, dimensions are generally specified by number or dimension attributes. In some languages, array declarators specify the size of each dimension of the array, and in some languages the array is an array of elements in a table. In a hardware sense, an array is a collection of structures (functional elements) that are the same in a massively parallel architecture as a whole. An array element in data parallel computer processing is an element to which an operation can be assigned and which can execute a required operation independently and in parallel in a parallel state. In general, an array can be thought of as a grid of processing elements. By assigning partition data to each section of the array, the partition data can be moved in a regular grid pattern. However, it is possible to index the data or assign the data to any location in the array.

Array Director The array director is a unit programmed as an array control program. The array director serves as a master control program for a group of functional elements arranged in an array.

Array Processor Array processors mainly include multiple instruction multiple data scheme (MIMD) and single instruction multiple data scheme (SIM).
There are two types, D). In a MIMD array processor, each processing element in the array uses its own data to execute its own unique instruction stream. SIM
In a D array processor, each processing element in the array is
Limited to the same instruction via a common instruction stream. However, the data associated with each processing element is unique. There are other features of the preferred array processor of this invention. In this specification, this is referred to as APAP, and AP
The abbreviation AP is used.

Asynchronous Asynchronous means that there is no regular time relationship. That is, the relationship between the executions of each function is unpredictable, and there is no regular or predictable time relationship between the executions of each function. In a control situation, the control program addresses the location to which control is passed when data is waiting for the idle element being addressed. This keeps the actions in order even though they do not match the time of any event.

BOPS / GOPS BOPS or GOPS is an abbreviation for the same meaning of 1 billion operations per second. See GOPS.

Circuit Switching / Store-and-Switch These terms refer to two mechanisms for moving data packets through a network of nodes. Store-and-forward is a mechanism by which a data packet is received at each intermediate node, stored in its memory, and then forwarded towards its destination. Circuit switching directs an intermediate node to logically connect its input port to an output port so that data packets can pass directly through the node to their destination without entering the intermediate node's memory. It is a mechanism that enables it.

Cluster A cluster is a control unit (cluster control device),
Hardware connected to it (terminals, functional units,
Or a virtual component) and a station (or functional unit). As used herein, a cluster is a processor memory element (PM), also referred to as a node array.
E) of the array. Normally, a cluster has 512 PM
It has an E element.

The entire PME node array of the present invention consists of a set of clusters each supported by one cluster controller (CC).

Cluster control device A cluster control device is a device that controls the input / output operations of a plurality of devices or functional units connected to it.
The cluster controller is typically under the control of a program stored in, and executing on, the unit, as in the IBM 3601 financial institution communication controller.
It is fully controllable in hardware, as in the 3272 controller.

Cluster Synchronizer A cluster synchronizer manages the operation of all or a portion of a cluster to maintain the synchronized operation of the elements so that each functional unit can maintain a specific time relationship with the execution of the program. It is a functional unit.

Control Device A control device is a device that directs the transmission of data and commands over the links of an interconnection network. The operation of the control device is controlled by a program executed by a processor to which the control device is connected or a program executed in the control device.

CMOS CMOS is an abbreviation for complementary metal oxide semiconductor technology. It is widely used in the manufacture of dynamic random access memory (DRAM). NMOS
Is another technique used in the manufacture of dynamic random access memories. In the present invention, the complementary metal oxide semiconductor is used.
The technology used to manufacture the processor (APAP) does not limit the scope of semiconductor technology used.

Dotting refers to joining three or more lead wires by physical connection. Most backpanel buses use this connection method. This term
Related to the OR DOTS of the past, it is used here to identify multiple data sources that can be coupled onto the bus by a very simple protocol.

The concept of I / O zippers in the present invention can be used to implement the concept that an input port entering a node can be driven by an output port exiting a node or by data coming from the system bus.
Conversely, the data output from one node can be used as an input to another node and system bus. It should be noted that the data output to the system bus and another node are not executed at the same time but in another cycle.

Dotting is used in the discussion of H-DOT, by which it is possible to use a two-port PE or PME or picket in an array of various configurations. Several topologies have been discussed, including 2-D and 3-D meshes, base 2N cubes, sparse base 4N cubes, sparse base 8N cubes.

DRAM DRAM is an abbreviation for dynamic random access memory, which is a common storage device used by a computer as a main storage device. However, the term DRAM is also applicable to use as a cache or memory that is not main memory.

Floating-Point Floating-point numbers are represented in two parts: a fixed-point part, or fractional part, and an exponent part to a radix or base on the promise. The exponent indicates the actual position of the decimal point. In typical floating point notation, the real number 0.0001234 is represented as 0.1234-3. Here, 0.1234 is a decimal part and -3 is an exponent. In this example, the floating point radix or base is 10, representing an implicit fixed integer base greater than one. The exponent represented explicitly in the floating-point representation or represented by the exponent in the floating-point representation is raised to the power of this exponent and then multiplied by the fractional part to obtain the represented real number. Numeric literals can be represented either in floating point notation or in real numbers.

FLOPS This term refers to the number of floating point instructions per second. Floating point operations include ADD (addition), SUB (subtraction),
It involves MPY (multiplication), DIV (division) and often many other operations. The parameter of floating point instructions per second is often calculated using add or multiply instructions and can generally be considered a 50/50 mix. The calculation includes generation of an exponent part and a decimal part, and normalization of a necessary decimal part. The present invention can handle 32-bit or 48-bit floating point formats (though it may be longer, but such formats were not counted in the mix). Multiple instructions are required when performing floating point operations with fixed point instructions (regular or RISC). Some people use a 10: 1 ratio when calculating performance, and a ratio of 6: 1.
Some studies have shown that 25 is more appropriate. Different architectures have different ratios.

Functional Unit A functional unit is a hardware, software, or both entity that can achieve a certain purpose.

G bytes G bytes refer to 1 billion bytes. 1 Gbyte / sec
That's 1 billion bytes per second.

GIGAFLOPS 10 ⁹ floating point instructions per second

GOPS and PETAOPS GOPS or BOPS have the same meaning of 1 billion operations per second. PETAOPS means 1 trillion operations per second, which is the potential of current machines. In the APAP machine of the present invention, these terms are BIP / G which means 1 billion instructions per second.
It is almost the same as IP. While some machines can perform multiple operations (ie, both add and multiply) with a single instruction, the present invention does not. Also, it may take many instructions to perform one operation. For example, the present invention uses multiple instructions to perform 64-bit operations. However, when counting the calculation, the logarithmic calculation was not performed. GO to describe performance
Preference was given to using PS, but it was not used consistently. MIP / MOP, BIP / BOP as units above it, and MegaFLOPS / Giga
FLOPS / TeraFLOPS / PetaFLOPS
Is used.

ISA ISA means a Set Architecture (architecture setting) instruction.

Link A link is a physical or logical element. A physical link is a physical connection for connecting elements or units, while a link in computer programming is an instruction or address that exchanges control and parameters between different parts of a program. In multiple systems, a link is a connection between two systems specified by program code that identifies the link identified by a real or virtual address. Thus, a link typically includes the physical medium, any protocol, and associated equipment and programming. That is, the link is both logical and physical.

MFLOPS MFLOPS means 10 ⁶ floating point instructions per second.

MIMD MIMD is a multiple data arrangement where each processor in the array has its own instruction stream and thus multiple instruction streams, one for each processing element.
Used to refer to the processor array architecture that executes a stream.

Module A module is a discrete and identifiable program unit, or a functional unit of hardware designed for use with other components. An aggregate of PEs included in a single electronic chip is also called a module.

Node In general, a node is a junction of links. In a general-purpose array of PEs, one PE can be a node.
A node can also include a collection of PEs called modules. In the present invention, a node is formed from an array of PMEs, and this set of PMEs is called a node.
The node is preferably 8 PMEs.

Node array A collection of modules composed of PMEs is sometimes called a node array. It is an array of nodes made up of modules. Node arrays are typically
Although there are more than a few PMEs, the term encompasses a plurality.

PDE PDE is a partial differential equation.

PDE relaxation solution process PDE relaxation solution process is PDE (partial differential equation)
Is a method of solving. Solving PDEs uses most of the computational power of supercomputers in the known field, and thus it exemplifies the mitigation process. PD
There are many ways to solve the E equation, and several numerical solutions include the relaxation process. For example, when solving a PDE with the finite element method, most of the time is spent computing the relaxation. Consider the example of the field of heat transfer. Given the hot gas inside the chimney and the cold wind outside, what is the temperature gradient inside the chimney bricks? Considering bricks as small segments and writing an equation that describes how heat flows between the segments as a function of temperature difference, the heat transfer PDE is transformed into a finite element problem. Now, assuming that all elements, except the inner and outer elements, are at room temperature and the boundary segments are the temperature of the hot gas and cold wind, a problem is created to initiate the relaxation.
The computer program then models the time by updating the temperature variable within each segment based on the amount of heat flowing into or out of the segment. In order to relax a set of temperature variables in the chimney to represent the actual temperature distribution that occurs in the physical chimney, it must take many cycles to process all the segments in the model. If the goal is to model gas cooling in a chimney, the elements must be extended to the gas equation, then the inner boundary conditions are linked with another finite element model, and this process continues. Note that the heat flow depends on the temperature difference between adjacent segments. Therefore, the temperature variable is distributed using the communication path between PEs. It is due to this adjacent communication pattern or characteristic that the PDE relationship can be successfully applied to parallel computing.

Picket This is an element within the array of elements that make up the array processor. This element is a data flow (ALU
REGS), memory, controls, and the parts of the communication matrix associated with this element. This unit refers to 1 / n of an array processor that consists of parallel processor elements and memory elements and their control and part of the array intercommunication mechanism. Pickets are a form of processor memory element (PME). The PME chip design processor logic of the present invention may implement the picket logic described in the related application or have the logic for a processor array formed as a node.
The term picket is similar to the commonly used array term PE for processing elements, preferably a combination of processing elements and local memory for processing bit parallel bytes of information in a clock cycle. Consists of,
It is an element of the processing array. The preferred embodiment consists of a byte wide data flow processor, 32 bytes or more of memory, a primitive control mechanism, and a mechanism for communicating with other pickets.

The term "picket" comes from Tom Sawyer and his white fence. However, it will also be understood that, functionally, it is similar to the army's picket line.

Picket Chip A picket chip contains multiple pickets on a single silicon chip.

Picket Processor System (or Subsystem) A picket processor is an array of pickets, a communications network, an input / output system, a microprocessor, a canned routine processor, and a microcontroller that implements the array. It is a total system composed of a SIMD control device composed of

Picket Architecture The picket architecture is the preferred embodiment of the SIMD architecture and has the capability to address a number of diverse problems including: -Set associative processing-Parallel numerical central processing-Image-like physical array processing

Picket Array A picket array is an ordered collection of pickets arranged in a geometrical order.

PME or Processor Memory Element PME stands for Processor Memory Element. The term PME is used herein to refer to a single processor, memory, and I / O capable system element or unit forming one of the parallel array processors of the present invention. PME is a term that encompasses pickets. A PME is a processor, memory associated with it,
1 / n of the processor array that consists of the control interface and part of the array communication network facility. This element can comprise a PME with regular array connectivity, such as in a picket processor, or a PME as part of a sub-array, such as in the multiple PME node described above.

Routing The routing is the allocation of a physical route for delivering a message to a destination. A source and a destination are required for route allocation. These elements or addresses are
Has a temporary relationship or affinity. Message routing is often based on keys obtained by looking up a table of assignments. Within a network, a destination is any station or network addressable unit that is addressed as the destination of information to be transmitted by a routing address that identifies a link. The destination field identifies the destination with the message header destination code.

A processor array architecture in which all processors in a SIMD array are instructed to execute multiple data streams, one arranged per processing element, from a single instruction stream.

SIMDMIMD or SIMD / MI
MD SIMDMIMD or SIMD / MIMD is a term that refers to a machine that has the dual function of being able to switch from MIMD to SIMD for a period of time to process complex instructions, and thus has two modes. Placing a Connection Machine Model CM-2 from Thinking Machines, Inc as the front end or back end of a MIMD machine allows the programmer to configure multiple modes, also known as dual mode. I was able to run different parts of the problem that were running. These machines have been around since ILLIAC and use a bus to interconnect a master CPU with other processors. The master control processor has the ability to interrupt the processing of other CPUs. Other CPUs can execute independent program code. During the interrupt, something needs to be done for the checkpoint function (close and save the current state of the controlled processor).

SIMIMD SIMIMD is a processor array architecture in which all processors in the array are commanded by a single instruction stream to execute multiple data streams arranged one per processing element. Is.
Within this configuration, the data dependent operations within each picket that mimic instruction execution are controlled by the SIMD instruction stream.

This uses the SIMD instruction stream to order multiple instruction streams (one per picket) and multiple data streams (one per picket).
A single instruction stream machine capable of executing SIMIMD can be performed by the PME system.

SISD SISD is an abbreviation for single instruction single data.

Swapping Swapping refers to the interchange of the data content of one storage area with the data content of another storage area.

Synchronous Operation Synchronous operation in MIMD machines is an operational mode in which each action is associated with some event (usually a clock). This event can be a specified event that occurs regularly in the program sequence.
Actions are dispatched to a number of processing elements, each of which performs its function independently. Control is not returned to the controller until the operation is complete.

If the request is for an array of functional units, a request is made by the controller to an element in the array, which element must complete operation before control is returned to the controller.

TERAFLOPS TERAFLOPS means 10 ¹² floating point instructions per second.

VLSI VLSI is an abbreviation for very large scale integration (applied to integrated circuits).

Zipper A zipper is a newly provided function for establishing a link from a device external to the normal interconnect of an array configuration.

The prior art as the background of the present invention will be described below. As engineers strive to speed up computers, hundreds, sometimes thousands, of low-cost microprocessors are linked in parallel to create super
They are building supercomputers and trying to solve complex problems that today's machines can't handle. Such machines are called massively parallel machines. The inventors have developed a new method for building a massively parallel system. The numerous improvements we have made should be considered against the background of numerous studies by others.
A summary of the art is made in other referenced patent applications. In this regard, US Patent Application No. 60159, relating to our parallel associative processor system, is discussed in this regard.
See No. 4 and related U.S. patent application for the Advanced Parallel Array Processor (APAP). System trade-offs are necessary to choose the architecture that best fits a particular application, but no single satisfactory solution has been available. Using the inventive concept, the solution is easy to implement.

The first description of the picket was made in a related patent, US Pat. No. 6,111,594. In that same document and in the related patent application mentioned above, numerous references are considered to be background art. The concept of the present invention provides for intercommunication between the pickets of a processor array within the array of processors, each of data flow (ALU and REG), memory, control logic, and the communication matrix associated with the picket. It is desirable to provide a picket, including the enabling part. For convenience, reference is made to the "Prior Art" section of the related patent application.

The present specification is directed to the use of processing elements or pickets in the conventional sense within an array of SIMD machines. SIMD machines have been around for many years, but one such machine that is prior art is shown in FIG. 1 herein. Related US patent application Ser. No. 07 / 51,933, a continuation of US patent application Ser. No. 07 / 250,595.
In the prior art described in the specification No. 2, an expensive and complicated MIM is used.
In order to better utilize parallel processing power without resorting to D processors, multidimensional arrays of processing elements with increased flexibility have been described. The above application was originally 198 as European Patent Application No. 88/307885 / 88-A.
It was first announced on May 3, 1997. The system described in this specification sends global instructions for local bit serial execution along a bus connecting control logic in various parallel processing elements, where local bits are decoded and local bits are decoded. Programmatically modify selected bits of the global instruction for use on the bit line.

Next, another array system in this technical field which can be considered as a background art will be described.

In US Pat. No. 4,736,291,
Array variant processors are discussed which perform high speed processing of arrays of data. This is F in the area of seismic analysis
It is specifically optimized for the implementation of the FT algorithm.
The focus of this patent is on bulk memory and system control buses shared by as many as 15 different devices. Each device has a writable control store, a program memory, a control unit and a device dependent unit that gives each of the 15 devices unique characteristics. This patent relates to an array variant processor, but such a processor itself does not necessarily have to utilize a processor parallel array, and the above patent does not describe that. Note that array modifications can be made by the systems described herein and in the related patent applications.
However, the processor described in this patent instead has multiple subunits (or stages) that process an array of data in a complex, iterative manner. This differs from the SIMD processor array of the present invention, where each subunit takes one element of the array of data and processes the data in parallel within multiple processors.

In US Pat. No. 4,831,519,
A SIMD array processor with left-right inter-processor connections, so that 16-bit processor elements (PEs) can be connected side-by-side to effectively adapt to various data formats. Arguing. For example, a 64-bit floating point word is
, Where the higher PEs process the exponent and the other three are interlocked to process the 48-bit fraction. This can be achieved by connecting control and carry / borrow between PEs. 16 16-bit PEs for data, 2 PEs for address generation, and 2 spare Ps in 1 chip
E can be included. The input / output of this patent uses a four-level signaling technique to combine two logic signals into one pin to generate one of four different voltages depending on the logic state of the two signal lines. be able to.

In this patent, control or controller functions must be provided, but little is said about it. However, this array has a global MASK (mask) that defines how PEs are grouped to operate on data of various sizes, and a local NEST (propagating from a master PE of a nest to a slave PE on the right). Nest control is provided. Obviously, this PE cannot determine which group it belongs to, nor does any process have local autonomy in the sense that it is based on data being processed by the PE other than NEST control. This patent specification contemplates that SI can be extended horizontally within a chip to handle 16-bit, 32-bit and 64-bit data widths by concatenating adjacent PEs to operate as a single processor.
Possible designs for MD chips are described. Therefore, it can also be considered applicable to any concept that can be implemented after the development of the picket machine of the present invention having memory and logic on the same chip, thus extending the inventive concept. become. It is possible to provide parallel processing elements on one chip. However, this patent specification does not show how to combine the processing elements so that the processing element can know or judge whether or not the processing element is a participating element. In this patent specification, grouping is dictated by the global control MASK. A review of this patent after understanding the invention will reveal the lack of local autonomy capabilities.

US Pat. No. 4,748,585 discusses a mechanism for assigning parallel processor elements to segments to accommodate varying lengths of data. This is similar to US Pat. No. 4,831,519. However, this specification relates to groups of uniprocessors that are linked together to obtain longer word length processing. Each single processor is complete in that it has a microprocessor, ALU, registers (REG), etc. The obvious teaching of this patent is that multiple single processors can be lockstepped together to operate on a wide data word. The control of segmentation seems to be done by the global control using the combination code and the global condition code. MI
As an MD array, this patent cannot provide the capabilities of a SIMD array. The improvement provided by the present invention relates to an unprecedented concatenation of pickets, which is the central subject of this patent, a MIMD array for combining arrays into a wider processor. It's not about controlling.

In US Pat. No. 4,825,359,
It discusses a processor for processing an array of data, the calculation of which is likely to be a Fast Fourier Transform (FFT). The processors can each be programmed to perform one step of the calculation,
It contains multiple processing operators. It could be categorized as a complex single processor with multiple processing operators, which acts as a pipeline in performing complex processing. In this patent neither grouping nor autonomy is discussed, but rather the purpose seems to be to make some improvements to accommodate a wide range of operators.

US Pat. No. 4,905,143 describes 2
Discusses an array processor for performing the computation of all combinations of variables of one type and the use of these computations to compute recursive equations with local dependence of the data. It features matching calculations based on dynamic time warp theory or dynamic programming theory used in pattern matching for speech recognition. Although difficult to understand, this processor appears to be intended to function as some sort of systolic MIMD tube. The PE is expected to be placed in the ring and pass the intermediate result to the next PE in the ring. Each P
E has its own instruction memory and other features. This patent does not discuss the autonomy of PEs within a SIMD array, and further, the PEs appear to be ungrouped except by physical placement in a ring.

US Pat. No. 4,910,665 discusses a two-dimensional SIMD array processor interconnect scheme in which each PE has direct access to its eight adjacent PEs. The communication medium is a dotted network that interconnects four adjacent PEs in the corner. Although SIMD machines are disclosed, there is still no idea that local autonomy or grouping of PEs can or should be provided, much less in the manner described herein. .

US Pat. No. 4,925,311 discloses that
A multiprocessor system is disclosed in which the processors within a multiprocessor can be assigned to act together as a group for a problem. Further, each processor can add itself to the group and remove itself from the group, as well as passing messages, semaphores and other controls between the processors. However, this patent is essentially a MIMD
Therefore, there is no suggestion of having the PEs in the SIMD array have local autonomy as described herein. Instead, each processor in the multiprocessor system has a network interface controller that includes RAM, a microprocessor, and some functional unit (disk controller). Grouping is controlled by the network interface of each processor. The present invention does not require such elaborate task divisions and grouping is controlled within each picket.

In US Pat. No. 4,943,912,
Connected by the NEWS network, where the array controller loads the program into the memory of each PE in the array and then issues a start procedure command to the PEs that identifies where they should start executing. MIM
Discussing D arrays. Each PE includes a register that stores the task pattern and a comparison mechanism for matching the PE's task pattern with the global task pattern command. The result of this comparison is used to select a program start point within the PE or to transition the PE to the idle state. The MIMD patent does not suggest autonomy at the PE in the SIMD array as described herein. The comparison mechanism and the results it produces can be used to classify or group PEs for different concurrent tasks. In this specification, in the SIMD environment, P
Details how E becomes able to classify or group itself. As a result, during execution of a portion of SIMD code, a portion of the picket of the present invention becomes detached and active. The machine of the present invention can then proceed with the process and activate another group for the process.

US Pat. No. 4,967,340 discusses a systolic array processor where each element consists of two registers, one adder, one multiplier and three programmable switches. . The array is constructed by the controller setting switches on each stage or element of the array. The data is then fed into these stages to get the desired result. Such a processor does not suggest the system of the present invention.

US Pat. No. 5,005,120 relates to arrays in the sense that there are multiple processors. However, this patent discusses a time compensation circuit for use in data alignment within a bit serial signal processor array. Each element of this array consists of a 4-bit serial register feeding the ALU. A time compensation circuit is placed before the first register.
This array has no similarities to SIMD machines.

US Pat. No. 5020059 is used in an array of processors where the array can be reconfigured around a failed PE and a tree or other topology can be realized in a basic two-dimensional mesh. It relates to a generalized interconnection scheme. There is no mention or suggestion of any aspect of the array control architecture, grouping, or PE, and thus no discussion of autonomy within the PE is included.

However, in the present invention, processing elements or pickets within an array of SIMD machines have traditionally performed exactly the same operations within all pickets. 1
Selectively disable one or more pickets,
The present inventors recognized that it was necessary and developed to enable local autonomy.

US Pat. No. 4,783,782 describes S
It discusses testing and adaptation to fault diversion on IMD array processors. This is not related to the subject of the discussion herein. U.S. Pat. No. 4,783,782 discusses a manufacturing test chip configuration for isolating up to two defective PEs in a SIMD array previously discussed in U.S. Pat. No. 4,831,519.
The chip contains a PRO section where defective data is stored. It can be read by the controller and used for dynamic allocation of on-chip resources.
Therefore, this chip has limited processor autonomy.

Notwithstanding all the efforts so far set forth above, a parallel associative processor system or dynamic multimode parallel array system as described above for performing SIMD, MIMD and SIMIMD processing on a single machine.
There seems to be no analog to the architecture.
In fact, the mechanisms required for SIMIMD processing, floating point, etc. have not been fully developed in the prior art.

US Pat. No. 4,783,738 is one of the patents covering the aspect of autonomy. The system described therein allows the SIMD controller to issue commands to all elements (PEs) in the array, with each PE in the command as a result of spatial or data dependent properties. One bit of can be changed or modified. Examples include ADD / SUB (addition / subtraction), SEND / RECEIVE (send / receive)
And a generalization to OPA / OPB is included. This feature should be used for line image processing and image boundary processing. Although similar to one of the autonomous functions described herein (particularly causing the ALU to perform data-dependent operations), the present invention does not specifically focus on changing one operation bit. . The present invention is an ALU
It is irrelevant that the function is position-specific (spatial) in the array. This patent is similar to some of the features of the present invention in the area of data-dependent functions, but the present invention allows the data-dependent portion of an instruction sequence (such as signs and condition codes) to simply be something else in the ALU. If you want to force the DWIM (Do what I mean) function.
This patent apparently uses 1-bit modification or insertion in operation in the area of data-dependent autonomous functions.

US Pat. No. 5,045,995 discloses that each PE in a SIMD array is based on the data conditions in each PE.
Is a mechanism for enabling or disabling. A global instruction directs all PEs to extract the state within that PE and accordingly enable or disable itself by the status register bits. Another global command
Effectively exchange PE condition. Using these features, the IF / THEN / ELSE structure and WHILE
A / DO structure can be implemented. In addition, situations can be stacked to support nested enable conditions. Therefore, this patent relates to the enable / disable function described herein. However, this U.S. Pat. No. 5,045,995 discloses: (1) initial test, loading of status bits, and enabling or disabling based on status bits;
This requires three conditions: (2) an instruction that inverts all disable / enable bits to enable another set of PEs, and (3) storage to achieve nesting. The device described in 1. is unnecessarily complicated. In the present invention, the conditions (1) and (2) of the present invention are
It will be apparent later that a mechanism for enabling and disabling features is provided without coupling all of (3) together. The mechanism of the present invention is described in US Pat.
No inversion function described in 5995 is required,
It will be apparent that it provides a wider range of system capabilities than that provided by the devices described in this patent. In the SIMD machine of the present invention, this function is used for IF instruction and EL
It need not be tied to SE instructions as well as other features related to video processing.

Regarding the floating point aspect of the present invention, other patents are referenced in the related patent specifications, one of which is:
There is U.S. Pat. No. 4,933,895 to a two-dimensional cellular array of SIMD controlled bit serial processing elements. Using the processing elements of this disclosure, adjustments of the bit-serial machine can shift one of the fractions, one bit at a time, until the condition is met, as is usually considered. This feature is based on the data itself and adjacent processing elements and should apply to the operation of arrays designed for image processing. U.S. Pat. No. 49338
In the '95 patent, bit-serial floating point operations are discussed in detail, but there is no discussion of what happens, may happen, or should occur in byte wide conditions. In this specification, as expected for serial machines,
It describes what happens in the implementation of the floating point addition regulator. First, the difference between the two exponents is taken, then the selected fractional part is shifted until the difference between the exponents is zero.

From this study, various types of parallel arrays
It will be seen that there were machines and SIMD machines. In addition, floating point machines have been invented. However, none have been successful in providing an implementation for floating point on SIMD machines that processes data by executing an array of processors in byte parallel. Such floating point computing power is required. In processors such as our "parallel associative processor system" and other parallel array machines that can execute data within an array of processors, floating point arithmetic
Contains all of D's nightmare material. Each processing element (P
E) or each picket has different data, different operations,
And can include different levels of complexity. All of these differences S where each element does the same
It increases the difficulty of running floating point on IMD machines. One example is floating point. "Float
Using the floating point math referred to in the above-referenced related patent entitled "ING Point Implementation on a SIMD Machine", local autonomy in accordance with the present invention can be exploited.

Floating point execution is important to the system of the present invention, but lists some other important computational aids. Implementation of these computational aids within the array processor would benefit from the local autonomy features that are the object of the present invention. Picket grouping, local table indexing and local execution of instructions are three important areas.

If the picket can evaluate itself and place itself in various groups, each of which can in turn be selected for processing, a significant amount over the capabilities currently used. Subtasks within a task running on an array of functional processors can be partitioned. This ability is called "Grouping of SIMD
It is discussed in a related patent entitled "Pickets".

Execution of transcendental functions and many other important functions is most efficiently performed by using tables. If each processor in the array of processors had the ability to independently pull the value in its own memory based on the data (angle value), a significant performance benefit would result.

Executing instructions from the local memory of each processor in an array of processors with SIMD implementations should increase the flexibility of such arrays. This is the basis for the SIMIMD mode described in related patent application 798788.

Therefore, there is a need for the present invention.

[0082]

The purpose of picket autonomy is to provide a parallel array machine that can operate in various modes including SIMD and SIMIMD. Thus, each element in the SIMD array of processors provided by the present invention receives a stream of commands from the array controller. In this case, multiple mechanisms allow the array machine with individual processing elements called pickets to
It allows some of the IMD commands to be interpreted in their own form, giving each picket some degree of local autonomy. The resulting capability allows the picket to execute instructions in a mode called SIMIMD. Another resulting capability greatly enhances floating point instruction execution performance.
Yet another capability groups pickets in various useful ways so that one group is executing a SIMD instruction while another group is dozing. Other capabilities include table lookups, locally supplied opcodes, and execution defined by data content.
SIMD and SIMIMD modes allow floating point representations of data and computations using the data within an array of processors executing the data in multi-byte wide data flows.

[0083]

SUMMARY OF THE INVENTION In a preferred embodiment of the present invention, a parallel array comprising a plurality of interacting picket units or PMEs (pickets) on the same chip.
It should be appreciated that within the processor, the implementations developed by the present invention for parallel array processors may be used. Such a system has multiple picket units (processing elements with memory). These units are arranged as an array, and an array of pickets with memory can be used as a set associative memory. The processing of such systems with multiple data streams is sometimes referred to as single instruction multiple data (SIMD).
Performance may be better if executed on the system. A processing system with floating point becomes part of a system that integrates computer memory and control logic on a single chip, which allows the combination to be replicated within the chip and the processor system from a single chip replication. Can be built. Within this chip, each processing memory element (PME) can operate as an autonomous processor, provides control of an external control processor, and when implemented with the preferred embodiment of the present invention, the processor of the present invention provides a higher floating point number. SIMD mode with accuracy
It can operate as a processor.

Using the single-chip set-associative parallel processing system of the present invention, it is possible to retrieve a small set of "data" from a large set from a memory on which associative operations can be performed. This associative operation, which is typically an exact comparison, is performed in parallel on the entire set of data utilizing the picket's memory and execution units.
Within the picket array, each picket has a portion of the data from the large set. In addition, each picket selects a piece of data from that part. Therefore, a piece of data contained in each of the set of pickets is associated with all the pickets in parallel, and the associative operation is performed.
Construct a set of data.

This specification discusses a number of implementation techniques that, when applied to the design of a picket in a SIMD array of pickets, facilitate the operation of tasks that were previously difficult or impossible to perform. . This gives each picket a degree of local autonomy.

All of the local autonomous features described herein are presented to all participating pickets simultaneously.
It is implemented as a local variant of the D command or SIMD command. Some of these commands are
Bring local autonomy directly. Command "LOA
The D OP FROM MEMORY BUS (load instruction code from memory bus) has no associated local variant, but it ensures that the locally selected command is recalled. REG PER STAT "
Store in register A (depending on circumstances) makes storage in register A dependent on local status bits.

In the preferred system of the present invention, each picket is enabled by a group or mechanisms.
This allows each picket to have different performance capabilities. These capabilities allow each picket to acquire various modes for executing data within the picket and interpreting SIMD commands within the picket rather than being sent from an external SIMD controller. This capability extends to several modes in which each processor of a SIMD array can and does perform different operations based on local conditions.

Combining some of these local autonomous functions allows pickets to have SIMD command
The ability to execute the picket's own local program segment for a short time under the control of a stream can be provided. This allows M in the SIMD array.
IMD capabilities are provided. SIM this architecture
Although referred to as IMD, the mechanism that supports SIMIMD and contributes to additional capabilities is described below. Some of these features participate in the mechanics of picket grouping and support fairly complex tools for selecting and grouping pickets for discrete computations. Although this function is called grouping, the mechanism that supports adding grouping to the system of the present invention will be discussed later. For a more detailed description of SIMIMD and grouping, see the related patent specifications referenced above.

Some of these features participate in the mechanics of efficient floating point techniques discussed in related patent specifications directed to floating point implementations on SIMD machines. A mechanism that supports floating point is added to the system described herein.

The functions for local autonomy provided by the present invention are classified into the following three categories. 1. Local operation controlled by situation 1. Local operation controlled by data Processor-to-microcontroller status distribution, each of which provides additional capabilities to the systems described herein.

The picket can turn itself on or off based on the previous situation. Picket is S
When given a command from the IMD controller, it can put itself in the doze mode by loading the appropriate value from the picket memory into the dose latch in the picket. This provides "local join" autonomy that provides the functionality for internal control of individual pickets within the picket chip.

As a result of the development of the invention described in detail below, the SIM of the processor of the computer system
D-arrays can execute data in parallel. The computer system has a plurality of array processing elements coupled as pickets for communicating data and instructions with each other. Each picket allows each picket to have different execution capabilities that allow it to acquire different modes for executing data within the picket and allow SIMD commands to be interpreted within the picket. It has the mechanism of.

Further, each picket has a plurality of mechanisms that allow each processor of the SIMD array to perform different operations based on local conditions, and to allow each picket to operate in multiple modes of actual execution.

As a result of the development of the present invention, each array processor can operate as being in SIMIMD array processor mode, and at least one of the plurality of array processors can operate in SIMIMD mode. . One element in the processor array
Receives and executes commands from the controller on each clock cycle. Some of these commands can be interpreted within each picket to generate different actions.

The inventors have developed a new method of creating massively parallel processors and other computer systems by creating new "chips" and systems designed using this new concept. The present invention and methods of related applications can be viewed as representing various concepts taught herein and related applications. The components described in each application can be combined in the system to create a new system.
It can also be combined with existing technology.

In this specification and related applications, the picket processor and the so-called enhanced parallel array processor (A
PAP) will be described in detail. Note that the picket processor can use the PME. Picket processors are particularly useful in military applications, where extremely small array processors are preferred. In this respect, the picket processor differs slightly from APAP, the preferred embodiment associated with the enhanced parallel array processor of the present invention. However, there is a commonality and the aspects and features provided in the present invention can be used in different machines.

The term picket refers to the 1 / nth element of an array processor, which consists of the processor and memory, and the communication elements that are incorporated therein and applied to array intercommunication.

The picket concept also applies to the 1 / nth of an APAP processing array.

The picket concept may differ from APAP in terms of data width, memory size, and number of registers, but in a massively parallel alternative to APAP,
Although configured to have 1 / nth the connectivity of a regular array, the APME's PME is different in that it is part of a secondary array. Both systems are capable of performing SIMIMD. However, the picket processor
SIMIMD can be executed directly because it is configured as a SIMD machine with MIMD in it.
The MD APAP configuration implements IMIMD with MIMD PEs controlled to emulate SIMD. Both machines use PME.

Either system can be configured as a parallel array processor with an array processing unit of an array with N elements interconnected by an array communication network. Where the processor
One-Nth of the array is part of the processing element, its associated memory, control bus interface, and array communication network.

The parallel array processor can instruct the processing unit to operate in one or both of two modes, where the processing unit has SIMD operation and M
It has a dual operating mode capability that allows it to move freely between these two modes for IMD operation. In doing so, when the SIMD is in its mode of organization, the processing unit can instruct each element to execute its own instructions in SIMIMD mode.
When is an implementation mode of processing unit organization, the processing unit can synchronize selected elements of the array to simulate MIMD execution. In this specification, this is called MIMD-SIMD.

In both systems, the parallel array processor provides an array communication network with paths for exchanging information between the elements of the array. The movement of information can be instructed by either of the following two methods. In the first scheme, the array controller directs all messages to move in the same direction at the same time, so the data being moved does not define its destination. In the second scheme, each message routes itself and the header at the beginning of the message defines the destination.

A segment of a parallel array processor array has multiple copies of processing units provided on a single semiconductor chip. Each copy of a segment of the array is for connecting the portion of the array communication network associated with that segment and that segment of the array to other segments of the array so that the array communication network can be expanded. Includes buffers, drivers, multiplexers, and control mechanisms.

A control bus or control path from the controller is provided for each processing unit such that a control bus extends to each element of the array to control its activity.

Each processing element segment of the parallel array contains multiple copies of the processor memory elements. A processor memory element is contained within a single semiconductor chip, has a segment of the array, and includes a portion of an array control bus to support communication of control to array segments contained within the chip. Includes register buffer.

Both systems can implement mesh movement and routing movement. Usually APAP
Are interrelated in a way that there are 8 elements on the chip,
The chips implement a dual interconnect structure that is otherwise interrelated. As mentioned above, programmable routing is generally established on-chip to establish a link between PMEs, although nodes can and typically are associated in different ways. In general, the regular APAP structure on chip is a 2x4 mesh and the node interconnects can be routed sparse octal N-cubes. Both systems have PE-PE intercommunication paths between PEs and can form a matrix from point-to-point paths.

With this background and perspective in mind, the features and aspects of the present invention relating to the preferred embodiments of the present invention will be described in detail with reference to the drawings. Additional details of this system can be found in the following description and related patents.

[0108]

The preferred embodiments of the present invention will be described below. We will start with a general discussion of the preferred floating point implementation. This embodiment of the floating point implementation is preferably used with a parallel array of processing elements (formed as pickets), but can be used with prior art parallel array processors. Therefore, it would be appropriate to consider such a system in order to provide a more appropriate orientation.

Referring to the drawings, FIG. 1 represents a typical prior art SIMD system of the type generally described in European Patent Application No. 8830755 / 88-A and British Patent Application No. 1445714. I want you to understand. In such prior art devices, SIM
Each D computer has multiple SIMD memory
A single-instruction, multiple-data computer having a parallel array processor, including a plurality of parallel-link bit-serial processors associated with one of the devices. The I / O system acts as a staging system to the SIMD unit and provides temporary storage for bidirectional two-dimensional data transfer between the host computer (which may be a mainframe or a microprocessor) and the SIMD computer. The input / output system controls the flow of data between the host computer and the temporary storage means, the temporary storage area,
It includes input / output processing means for controlling the flow of data to and from a plurality of SIMD memory devices, usually organized as buffer sections or large memory partitions. Thus, the input operation of the I / O system involves the transfer of data from the host computer memory to the temporary storage and the transfer of the data from the temporary storage to the SIMD memory device in the second step. For output,
A two-step process is performed in which data is transferred between the host computer and the SIMD computer via the two-dimensional bus. The I / O system for I / O transfers can be a separate unit, or a sub-unit in the host, but is often a unit in a SIMD computer, with a SIMD controller providing temporary I / O buffer storage. Acts as a control mechanism for.

The SIMD computer itself includes multiple processing elements, individual processing elements and multiple conventional separate SIMDs.
A network connecting the memory devices,
Contains a processor array. SIMD computers are parallel array processors that have many individual processing elements that are linked and operate in parallel. SIMD
The computer includes a control unit that generates the instruction stream for the processing elements and provides the computer with the necessary timing signals. Networks interconnecting various processing elements include some form of interconnection scheme for individual processing elements. The interconnect can employ numerous topologies such as mesh, polymorphic torus, hypercube, and so on. The multiple memory devices are for immediate storage of bit data for individual processing elements. There is a one-to-one correspondence between the number of processing elements and the number of memory devices that can be said buffer partition of large memory.

For example, as shown in FIG. 1, a host processor 28 is provided. Array controller 14 (including temporary storage buffers) using this processor
A microcode program to exchange data with the array controller 14 and monitor the status of the array controller 14 via the data bus 30 and address / control bus 31 between the host and controller. The host processor in this example may be any suitable general purpose computer such as a mainframe or personal computer. In this prior art example, there are two array processors in the array.
Although shown dimensionally, the arrays can be organized differently, such as a three-dimensional cluster array or a four-dimensional cluster array. The SIMD array processor uses the processing element P (i,
j) array 12 and array controller 14 for issuing a stream of global instructions to processing element P (i, j). Although not shown in FIG. 1, this prior art example has a processing element that operates on one bit at a time and is associated with a block of storage that is a partition in memory associated with that processing element. ing. The processing element is NEWS
A (North, East, West, South) network connects bidirectional bit lines to each adjacent processing element. That is,
Processing element P (i, j) is processing element P (i−1, j), P (i, j + 1), in each direction of north, east, west, and south.
It is connected to P (i, j-1) and P (i + 1, j).

In this typical example, a NEWS network is toroidally connected at its edges, with the north and south edges interconnected in both directions, and the west and east edges interconnected as well. It A data bus 26 between the controller and the array is connected to the NEWS network to allow data to be input to and output from the array of processors. As shown, this data bus 26 is connected to the east and west boundaries of the array. Toroidal east-west N
With a bi-directional 3-state driver connected to the EWS connection,
You can connect to the north-south boundary instead of the east-west direction, or to both the east-west boundary and the north-south boundary. The number of processing elements in this example is 3 instead of 16 × 16 as in this example.
If it were 2 × 32, then 1024 processing elements would be realized in the prior art, as in the preferred embodiment described below. In the figures, a single line represents a single bit line and double lines connecting functional elements are used to represent multiple connection lines or buses.

In this prior art example, the array controller issues an instruction in parallel to the processing elements via the instruction bus 18 and the row select signal and the column select line 20 and the column select line 22, respectively. Issue a signal. These instructions cause the processing element to load data from storage, process it, and then store it back in storage. For this purpose, each processing element can access a bit slice (section or buffer) of main memory. Thus, logically, the array processor's main memory is divided into 1024 partitioned slices for an array of 1024 processing elements. That is,
Up to 32 32-bit words can be transferred to or from storage at one time in one transfer step. To perform a read or write operation, the memory is addressed by the index address provided on the memory address lines via the address bus 24 and each processing element is provided with a read or write instruction in parallel. It During a read operation, the row select signal on the row select line and the column select signal on the column select line identify which processing element should perform the operation. Therefore, in this example, when the array is 32 × 32, from the memory, 3 of the selected rows are
It is possible to read a single 32-bit word into two processing elements. A processing element is associated with a slice or 1-bit wide memory block (i, j).
This slice or block memory is logically associated one-to-one with the individual processing elements involved, but can be, and usually is, physically separated on another chip. With this prior art architecture it is unclear how the above array processor could be manufactured on a single chip. The pickets of the present invention can be manufactured with an array of processors and suitable memory on a single chip of the type described below.

Processing element P (i, j) of this prior art example
It is to be understood that it comprises an ALU and input and output registers, including carry, each capable of storing a single bit of information. A multiplexer is connected to the I / O of the ALU and to the bidirectional data port of the slice (i, j) of memory associated with each processing element P (i, j).

With the instruction and data buses separate, the array controller causes the host 28 to use the data bus 30 and the address / control bus 31 to load microcode that defines the processing performed by the array. Have microcode storage for After the array controller operation is initiated by the host 28, the microcode order is controlled by the microcode controller connected to the microcode storage within the array controller 14. The array controller's ALUs and register banks are used to generate array memory addresses, count loops, calculate jump addresses, and operate general registers on the address bus. The array controller also has a row mask code and a column mask
It also has a mask register for decoding the code.
A particular instruction code is passed to the processing element via the instruction bus. In this example, the array controller has a data buffer that is within the controller but functionally between the host-controller bus and the controller-array data bus. You can Data is loaded from this buffer into the array of processors under the control of microcode in control storage. The reverse direction is also the same. For this purpose, the buffer is arranged as a bidirectional FIFO buffer under the control of the microcode controller in the array controller. Details of such prior art systems can be found in the examples cited above, in particular in European Patent Application No. 88.
See 307855 / 88-A.

A summary of prior attempts can be compared with the preferred embodiment of the present invention. A basic picket unit 100 is shown in FIG. Basic picket unit 10
0 comprises a combination of a processing element ALU 101 and a local memory 102 coupled to the processing element for processing one byte of information in one clock cycle. As shown, a picket unit is formed with a linear array of pickets on a silicon base or picket tip with adjacent pickets on both sides (right and left in the figure), resulting in a silicon base. -On the chip, a picket processing array with multiple local memories is formed. There is one local memory for each byte wide processed data flow, arranged as a logical row or linear array with adjacent picket communication buses for passing data in both left and right directions. The set of pickets in a picket chip are arranged in geometric order, preferably horizontally on the chip. Figure 2
Shows a typical implementation of two pickets in a picket array on a picket chip with multiple memories and data flows, with a communication path between the processing elements of each picket and the memory. In the preferred embodiment of the present invention, the data communication path between the memory and the processing elements in a one-to-one relationship in the array is byte wide and extends left and right to adjacent pickets or even remote picket processors. Is in contact with the "slide" for communication.

[0117] A "slide" is the closest active neighbor to which a message actually receives a message if the picket, which would otherwise be able to receive the information, is not transparent to the incoming message. It can be defined as a means for transferring information in a single cycle through a picket address location to a non-adjacent location until it arrives at the picket and is received there. Therefore,
Slides work by sending information across non-adjacent locations across "off" pickets. picket"
Assume that A "is trying to transfer information to a remote picket" G. "Intervening" B "before the cycle.
By turning off the picket or "F" picket,
Keep these pickets transparent. In the next single cycle, "A" sends its message to the right, passing "B" to "F" which is transparent because it is off. "G" remains on, so you receive the message. In the usual use of "slides", information is transferred linearly across a grid, but sliding techniques can work well with two-dimensional meshes or multidimensional arrays.

In the preferred embodiment of the present invention, the processing element access is a byte serial operation rather than a bit serial operation. Each processor does not access a block of local memory or its associated partition or page, but rather memory associated with itself. 1
A character width or character multiple width bus is provided rather than a bit bus. 1 byte instead of 1 bit per clock cycle (future systems plan to double the performance of character bytes into multiple bytes)
Information is processed. Thus, between each picket processing element, 8 bits, 16 bits, or 32 bits can be flowed to fit the width of the associated memory. In the preferred embodiment of the invention, each picket tip is 32K.
It is preferable to have 16 pickets having an 8 (9) bit wide memory of bytes, one for each 32 Kbyte of storage per picket node of the linear array. In an embodiment of the present invention, CMOS as DRAM is provided with each associated memory and the character byte is 9 bits (acts as an 8-bit character with self-checking function).

The parallel path byte-width bus data flow between pickets and between processing elements and their memory is a significant improvement over the serial bit structure of prior art systems. Evaluating this important achievement will recognize that increasing parallelism creates another problem that must be resolved. As the understanding of the implications of the newly realized architecture grows, the value of other important solutions described below will be appreciated.

In addition to the transfer and slide mechanism to the left and right adjacent pickets described with reference to the drawings, another evaluated feature is the provision of a double byte wide broadcast bus to ensure that all pickets are There is a point that the same data can be viewed at the same time. Picket control and address propagation are also transferred on this broadcast bus.
It is this bus that supplies the comparison data when performing set-related operations and other comparison or synchronous operation operations.

Picket under control of a single instruction stream
Tasks with highly parallel data structures useful for processing within the data processing element include artificial intelligence pattern matching, sensor and track fusion in multi-sensor optimal allocation, context search, and image processing applications. However, many of these currently available applications were not used in the SIMD process. This is because the SIMD process is serial bit processing in a single clock time. For example, SI
The conventional serial processing element of the MD machine performs a 1-bit ADD operation every processor cycle, but 32
The bit parallel machine can execute 32-bit ADD in one cycle.

With the 32K byte configuration per processing element, the amount of memory that each processing element can logically use is much greater than in a conventional SIMD machine.

The number of pins on the chip is small because the amount of data to be taken in and out of the chip is minimized. DRAM memory is a conventional memory CMOS array, by eliminating the demultiplexing of the rows behind the memory array and providing the row address to read the rows of the memory array into the data flow in parallel,
Supports "row / column" access.

Since this memory includes "tribit" or "trit" in addition to data, the logic mechanism is not a conventional binary number, but has three states of logic 1, logic 0 and "don ^ t care". recognize. "Don ^ tc in the match field
are "matches either a logical 1 or a logical 0. The trits are stored in consecutive storage locations within the storage array. The mask is another form of data stored in memory, the picket processing element. Sent to the mask register of.

Since the storage array can store commands,
Allows one picket to behave differently than another. On-chip control of individual pickets during operation associated with most, but not necessarily all pickets, allows for implementations specific to SIMD operation. One of the simple control functions provided is the ability to control the break action in any picket whose status output meets certain conditions. That is, the non-zero condition is
Doze (drowsiness), that is, a command condition that interrupts an action and puts the picket in an inactive but conscious state. Another command provided is to inhibit or enable writing to memory based on conditions in the picket or based on the command provided to the bus prior to the sliding action.

1 with 32 Kbytes of memory each
Applying 6 powerful pickets to a picket chip provides 1024 processors and 32768K bytes of memory with only 64 chips. This array of pickets has a set associative memory. INDUSTRIAL APPLICABILITY The present invention is useful for image analysis and vector processing, which are numerical calculation-intensive processing. This powerful picket processing array can now be packaged on just two small cards. It will be appreciated that thousands of pickets can be properly packaged in more potential low power packages to run image processing applications with minimal delay or within video frame time.
For example, it is possible to run an application while the aircraft is flying, with little concern for payload issues.

The power of this picket allows the use of large, associated memory systems packed in a small area, and uses the processing power in various applications after the system designer has become accustomed to using the new system. Will be possible.

FIG. 3 illustrates a mechanism that can be said to be a fully associative memory, because when an association is requested, all memory locations are presented with comparison values and all memory locations respond simultaneously on their match lines. . Associative memory itself is well known in the art. In the system of the present invention, memory and
Using a parallel picket consisting of processing elements with byte transfers to do the search, there is an input of data and a search mask to find word K out of N words in memory. After all matching pickets have brought the status line high, another action reads or selects the first matching K. This action is commonly called set-associative, but picket
You can repeat up in memory. Similarly, writing is done via a broadcast operation with the select line going high indicating join, and the broadcast data is copied to all selected pickets.

Although not preferred, another embodiment reduces the amount of DRAM memory available so that each picket can include a section of fully associative memory of the type shown in FIG. For example, if you include 512 bytes of fully associative memory, every picket can store a set of search indexes, and 512 1024 pickets in a single operation, 512 comparisons per operation, or 1 With a speed of 1 microsecond per operation, 512 gigasecond comparisons per second are possible. With expandability, this concept can be extended to a range of tera-times comparisons. This example provides associative tasks that require extensive exploration of information with capabilities that far exceed the computing power currently available.

As shown in FIG. 2, when using memory and byte-width coupled processing elements in the association operation, the individual algorithms and operations, artificial intelligence, and SI
In addition to applications such as parallel programming that are tried in MD situations, there are many applications currently available for machines with the above chip configurations in SIMD environments. An example is shown below.

Simple parallelizable computing task. Includes matrix multiplication and other tasks that can be performed on dedicated memory machines.

Image matching tasks and image processing tasks that can be performed on von Neumann machines, but can be significantly accelerated by applications that can accommodate extreme parallelism. For example, pattern matching of 3D images.

・ Data-based inquiry function

Pattern matching in the field of artificial intelligence

Network control at the bridge to quickly identify messages sent to users on the other side of the bridge of the network

Gate-level simulation

Inspection program for checking for violation of VLSI ground rules

Application programmers will come up with processing tasks that utilize banks of memory and associated processing elements when developing applications that utilize the capabilities of this new system architecture.

In utilizing the novel architecture of the present invention, process changes enhance normal applications. The process of maintaining a description of a digital system can be enhanced by using this array to describe one gate or logic element for every 100 pickets. In such a system, the process begins by assigning a description of each gate as a list of signals that the gate accepts as input and naming the signals it produces. The present invention will include the step of broadcasting the name via the bus 103 to all pickets each time the signal changes and comparing this name in parallel with the name of the expected input signal. . If a match is found, a subsequent step records the new value of the signal in the dataflow register bits within that picket. Once all signal changes have been recorded, in such an expansion process all pickets read in parallel control words that tell the data flow how to calculate the output using the set of current inputs. These operations are then performed in parallel and the result is compared with the old value from the local gate. The improved process then records all picket gates whose outputs have changed as dataflow status bits. The external controller then queries all pickets for the next modified gate. The system then broadcasts the appropriate signal name and value from that picket to all other pickets, as described earlier, and repeats this cycle until no signal changes occur or the process stops.

Another process that can be developed to use the system is searching for dictionary names. When searching for dictionary names, the first letter of all names is the broadcast data address bus 10
The name is stored in picket memory 102 so that it can be compared with the first letter of the desired broadcast name on # 3. All non-matching pickets are turned off due to the control characteristics provided by the present invention. The second letter is then compared and the procedure of turning off after this comparison is repeated for successive letters (letter) until no more picket units are active or the end of the word is reached. When there are no active picket units or the end of the word is reached, the remaining picket units are queried and the sequencer reads the index of the desired data.

FIG. 4 shows the basic picket configuration of multiple parallel processors and memories, or picket units, arranged in rows on a single silicon chip as part of a parallel array that can be configured as a SIMD subsystem. , And illustrates the control structure of such a system. Also shown in FIG. 4 is a control processor and a supervisory microprocessor. In FIG. 4, memory and parallel processing element logic on the same chip are shown in the section labeled Array of Pickets. Each memory is n bits wide, and is preferably one character wide or 8 (9) bits as described above. However, it is also possible to have the word width of a multi-byte wide memory conceptually. Therefore, the memory portion of the parallel picket processing element is preferably 8 (9) bits wide, otherwise 16 or 32 bits wide. When using current CMOS foundry technology, it is preferred to use 8-bit or 1-character wide associative memory (9-bit wide bytes including self-test) with each picket processing element. The memory includes an ALU, a mask register (used for question and answer or mask operations) and a latch 104 (S in FIG. 4).
R), as well as a direct one-to-one correspondence with the combined processing elements, including status register 107 and dataflow registers A 105 and Q 106 (DF in FIG. 4). These elements are detailed in the picket view of FIG.
The DRAM and logic of each picket processor does not have the burden of competing with the interconnect network. This is because the multi-bit wide DRAM memory and its processing elements have a direct one-to-one correspondence on the chip itself.

In FIG. 4, there is a slide B register latch (SR) between the memory and the associated logic of the ALU of the processing element.
104 is logically arranged and the latch is basically
Note that this will be the coupling port for each processing element along the picket array. Each picket chip comprises a plurality of parallel picket processing elements arranged in a line (shown as a straight bus) for communication with a picket control mechanism. The vector address bus is common to the memories and the data vector address registers control which data is passed to each memory.

FIG. 4 also shows the interconnection between the main processor card or microprocessor card and the subsystem controller. The main processor card or microprocessor card is
In the preferred embodiment of the invention, it is a 386 microprocessor configured as a PS / 2 system. Global instructions are sent to the canned routine processor (CRP) via the subsystem controller. This canning routine
A processor is provided in the present invention and is an instruction sequencer 40.
2 and the execution control mechanism 403 that executes the specific microcode required by the instruction sequencer.
The instruction sequencer may be functionally similar to the controller. However, the present invention also provides a local register 405 within the canned routine processor. This local register 405 is a local register ALU.
Together (not shown), it provides the basis for all addressing that is broadcast to all pickets in the picket array 406. In this way, address calculations are performed for all pickets in one ALU without using picket resources, or perhaps using picket run cycles. This important additional feature gives the picket array control flexibility and allows it to perform dose functions, inhibit functions, and other control functions for performing special tasks, allowing pickets to be broadcast in any manner. It can also be separated from the instruction and data functions.

The instruction sequencer 402, loaded with microcode 407, broadcasts to an array of pickets to the main program microprocessor (M
P) and the canning routine run-time library 408 canning routine to determine under the SIMD instruction sequence determined to enable SIMD processing of the data contained in the array of pickets.

The instructions provided to the microprocessor (MP) through the subsystem interface are passed to the microprocessor from the subsystem controller of the microprocessor (MP), and the start process is started.
(Processing start), Write Obser. It is considered to be a high-level processing command including (write monitoring) and Read Result (read result). This microprocessor is shown in FIG. 4, FIG. 5, FIG. 6, and FIG.
It can be considered as the main system or control processor in the subsystem array shown in. It should be appreciated that this unit may be a stand-alone unit with the addition of peripheral input devices (not shown) such as a keyboard and display device. In this stand-alone configuration, the system MP is a commercial PS / 2 in which a card including a sequencer card (which constitutes a canned routine processor) and a processor array card is inserted along the line shown in FIG. Can be considered The routine library 411 includes CALL (,), Kalman, Conv
olve, Nav. It may include a routine sequence for overall control of the process such as Update. Selection of these routines is done through the user program, and thus the entire process can be done under the control of the external host or under the control of the user program 412 within the MP. A data buffer 413 is provided in MP memory for data transfer to and from the parallel picket processor system. Instruction sequencer 402
Is configured to execute the control stream from the MP and the canning routine resident in the canning routine runtime library memory 408. These routines include
CALL (,) of the canning routine provided by the canning routine runtime library 408, Load Bl
ock, Sin, Cos, Find, Min, Rang
e Comp is included.

In the CRP, microcode 4 for controlling execution of low-level functions such as a Load function, a Read function, an Add function, a Multiply function, and a Match function.
There is also 07.

External FOR / NEX for each processing unit
It is preferable and practical to provide a T-control. It also implements deterministic floating point byte normalization.

The use of the deterministic approach provided by the present invention for system macro development enables picket grouping and group control. A local dose function is provided to handle individual picket processing variations.

When a user program needs to be executed by the processor array, the array of picket processors is provided with source commands, addresses, and broadcast data.

Which function each part of the system uses depends on the task to be performed and is assigned when the user program is compiled.

The flexibility of this subsystem can be illustrated with a fairly general problem. Matrix multiplication problem. ． ． Take | x | * | y | = | z | as an example.

This is described as the following problem.

[Equation 1]

This is solved, for example, by the statement Next to each statement,
The number of clock cycles per path is shown.

Number of cycles / number of passes Path 01 Call Matrix Mult Fx 1 c (R, M, C, Xaddr, Yaddr, Zaddr) 02 xSUB = ySUB = zSUB = 1 1 3 03 DO I = 1 to c 1 3 04 DO J = 1 to RC 3 05 z = 0 C × R 5/6 ^* 06 DO K = 1 to MC × R 3 07 *** Assign to associative parallel processor *** 08 Zz = Xx × Yy + Zz C × R × M 204/345 ^* 09 *** Return result *** 10 xSUB = xSUB + RC × R × M 2 11 ySUB = ySUB + 1 C × R × M 2 12 NEXT KC × R × M 3 13 xSUB = xSUB − M × R + 1 C × R 2 14 ySUB = ySUB − MC × R 2 15 zSUB = zSUB + 1 C × R 2 16 NEXT JC × R 3 17 xSUB = 1 C 2 18 NEXT z C 3 19 END Call 1 1 Note ^* Fixed point (4 bytes) / Floating point (1 + 4 bytes) --- See below

From the above example, statement 08 above
It will be appreciated that the task identified by will take approximately 98% of the cycle time. Therefore, this task is assigned to the SIMD organization of parallel picket processors. Other processes take only 2% of the cycle time and these processes are maintained in the architecture within the microprocessor.

Thus, considering this matrix multiplication example, it is assigned to either MP, CRP, a local register (LR) or a picket array for execution (each statement: Trigger execution at a particular system location).

In the above matrix multiplication example, statement 0
1 is assigned to the main processor MP and statements 02, 05, 10, 11, 13, 14, 15, 1
7 is assigned to the local register (LR). Statements 03, 04, 06, 12, 16, 18, 1
9 is assigned to be executed in the canned routine processor. Matrix processing, which normally takes time,
Assigned to the array of pickets to be executed under a single instruction, statement 08 is also assigned to the array of pickets.

FIG. 5 shows a multiple parallel picket processor system 51 with multiple parallel picket processors.
0 is shown. For applications such as multi-target tracking, sensor and data fusion, signal processing, artificial intelligence, satellite image processing, pattern / target recognition, Reed-Solomon encoding / decoding operations, the preferred embodiment has 1024 parallel processors. 102-4 with 2-4 (each represented here as 4 cards per system) SEM E cards 511
A system was constructed that can be configured as a SIMD system with four parallel processors. Individual cards 512
Can be inserted into a rack mounting system storage feature 513 with a wedge lock slide 514. The card is equipped with an insertion / removal lever 516 and a cover 51
If you close 7, you will have 32 to 64 Mbytes of storage and about 2 per second.
A mountable system with a performance of 100 million operations is effectively stored in the rack. The system is compact and an array of multiple pickets is inserted into a back panel board that contains the logic and allows the interconnection of multiple cards.

A processor with 32 Mbytes of storage is formed on four SEM E cards, and the system weighs only about 13.6 kg (30 lbs). Electric power is supplied by the power supply 519 shown. The required power of the air-cooled processor for such power is estimated to be only about 280W. Each SIMD system has two I / O ports 520 for channel adapter communication with the associated mainframe or other parts of the world. Bus structures for standard modular avionics packaging and connections to external memory (eg, PI bus, TM bus, and IE), each consisting of 4 logical pages.
In the illustrated multiple parallel picket processor using the EE 488 bus), the processor can be connected to the mission processor memory bus through an I / O port, providing an extension of the mission processor memory space. Can be considered

In the illustrated multiple parallel picket processor, which contains 1024 parallel processing elements, each processor has 32
With K bytes of local memory, the associated path to the picket parallel processor is parallel 8 bits wide or 1 character wide (9 bits).

The processors in each picket exchange data with other adjacent processors and between pages via the backplane interconnect network. A crossbar is preferable as the network, but a slide crossbar, a shuffle network, a base 3N cube, or a base 8N cube may be used.

The individual processors of the system are housed in a pack of 2 out of 4 cards.
A PS / 2 microprocessor is housed on a single card. On the other hand, a canning routine processor sequencer is accommodated in the remaining one of the four cards constituting the system outlined in FIGS. The individual picket 100 or picket card 512 includes a latch 104 architecture and a sequencer card 7.
On-the-fly with a canned routine processor based on a data condition controlled by a local register coupled to the CRP execution control mechanism of 03 and can be put into or out of operation. You can also Therefore, the picket processor
Alignment and normalization operations associated with floating point operations can be performed independently.

The processors are controlled in parallel by a common sequencer. The sequencer card 703 contains the picket processor controller CRP and executes a single thread of instructions coded to execute on an array of SIMD processors in a byte-sequential manner similar to conventional bit-serial processing. Can be picked by the picket process. The controller has three layers. The picket micro-control is microcoded like current processors and transferred to all pickets in parallel. The microcontroller and picket are synchronized to the same clock system CLK so that the functions controlled by the sequencer can perform the same clock time. It is the responsibility of the canned routine processor to supply commands to the micro-controlled sequencer. The sequencer card 703 is a hardwired controller that executes loop control commands and iteratively starts a new micro-control sequence during execution of most functions. The control unit uses the canning routine runtime library 40.
8 and the looping feature keep the picket well-fed and command-unbound. The canned routine processor controller contains a large set of macros that are called by the main system. The canned routine processor controller acts as the primary supervisory picket controller within the subsystem. This is the highest level picket array control system. It is the 386 microprocessor that manages the activity of the picket array. At any given moment, all pickets in the array can execute the same instruction. However, some of the processors can respond individually to the control flow.

There are several variations on individual responses, but the byte autonomy (dose, inhibit, etc.) for each picket provides local autonomy. This local autonomy is available for programming and can be provided at program compile time and placed under system control.

In addition, as mentioned above, there is also autonomy of local memory addressing. The SIMD controller sequencer provides a common address that all pickets use. Each picket can locally augment its address to enhance its ability to make data-dependent memory accesses.

Further, pickets may or may not participate in array activities, depending on local conditions.

Due to this property, each picket is now provided with means for assigning itself to one or several groups of a plurality of groups.
The concept of groups can be introduced into the D process. Processing can proceed based on these groupings, where configuration changes can basically be done on the fly. In some embodiments, only one group or one group at a time
Only one combination can be active, each executing the same SIMD instruction stream. Some actions only require work by a subset or group of pickets. You can take advantage of this ability in programming. Local participation autonomy is coordinated to allow such work. Obviously, the more pickets that perform the calculations, the better the local participation autonomy.

One way to increase the number of participating pickets is
Allowing each picket to execute its own instruction stream. This is basically M in SIMD
It is IMD. Currently, the same SIMD machine is MIMD
It is basically possible to configure it as a system or another configured machine. The picket can be programmed to work with its own sequence of instructions.

Since each picket can have its own sequence, it is possible to decode a very simple set of instructions at the picket level, and thus
A wider range of local processing can be performed. The first area where this feature is likely to be applied is in complex decision making. But simple fixed-point processing will also be an area of programmer interest.

Such a simple program would, for example, load a block of picket program that does not exceed 2K bytes into picket memory. SIMD
These blocks may be executed when the controller card 703 begins local execution from the specified xyz address via execution control. The control unit
Execution of the block continues when testing for the task complete signal when counting too many clocks or by monitoring the status funnel (SF) register shown in FIG.

The status funnel (SF in FIG. 4) utilizes a latch 104 for each picket. Each picket has a latch 104 that can be loaded to reflect the picket's status conditions. The SIMD controller can test the aggregate values in these latches (one per picket) by monitoring the array status line. This array status line is a logical combination of the values in each picket status latch.

In the following example, values greater than 250 are 500>
It is assumed that the user wants to adjust the range of x ≧ 250. The routine below uses the status funnel to detect that this task has been performed.

If VALUE <500 then TURN YOUR PICKET OFF STAT <-PICKET OFF CONDITION IF STAT FUNNEL = OFF then finished .... VALUE <-VALUE-250 Repeat

Therefore, this multiple parallel picket processor can be configured as a SIMD processor in various ways. Such a SIMD machine in the preferred embodiment is a SIMD controller or SIMD
Under the overall control of the sequencer, a single thread of instructions is programmed to execute in a conventional manner and is coded to execute on an array of SIMD processors in a sequential manner similar to conventional processors. At the application level, this is done by vector instructions and vector type instructions, which allow vectors to be processed within and between processors. Usually, 6 to 10 micro-instructions can be added to the vector instruction.

In such a preferred embodiment, the system diagrammatically appears as shown in the functional block diagram of the parallel processor subsystem of FIG. sub-system·
The sequencer, via the system I / O port controlled by the host interface control mechanism of FIG.
SIM with high-performance macros that control the functions of processing elements
Functions the same as the D program. Memory addressing allows 8-bit byte wide data flow, and modulo 8 arithmetic logic is used for each function (logic, add, multiply, and divide). Floating point format is provided for individual sleep modes and dose
Allows autonomous picket operation with modes as well as separate addressing.

The array of subsystem controllers is shown in FIG. Each processor array card 512 (two SEM Es, although there are four in this subsystem diagram)
Can be reduced to cards) sequencer CRP
703 and the sequencer CRP 703 is coupled to the subsystem controller 702. Subsystem controller 702 is ported to the main memory system or is coupled to another subsystem in the configuration via the interface of chip 705 to the associated Micro Channel bus 706. In the preferred embodiment, the subsystem controller is an IBM PS / 2 (a trademark of IBM) general purpose microprocessor unit, an Intel 3
Uses 86 processor chips and 4 Mbytes of memory. The personal computer microprocessor 702 is ported to the sequencer card via a chip 705 in the subsystem and a microchannel bus 706.

Local Autonomy Preferred Embodiments for SIMD All local autonomy functions described herein are implemented as SIMD commands or local variants of SIMD commands that are presented to all of the participating pickets simultaneously.
Some of these commands directly provide local autonomy functionality. Command "LOAD OP FR
OM MEMORY BUS "has no associated local variant, but this ensures that the locally selected command is invoked. On the other hand, the command" ST
ORE TO A REG PERSTAT "makes storage in register A dependent on local status bits.
From now on, each characteristic of local autonomy will be examined.

FIG. 8 illustrates a preferred embodiment of the present invention.
It shows how the array controller disables the picket and how the picket activates and deactivates itself to provide local autonomy. The selective disabling of one or more pickets provides more freedom in executing the problem. This is classified as a local autonomous function in this specification. The ability to issue SIMD commands to all pickets and the ability to have the picket perform different actions depending on the data in the picket can be expanded in several ways. One is a mode identified as SIMIMD mode, which causes each picket to execute an instruction. The other is to dynamically group pickets for separate execution. The other is to allow the floating point adjustment and normalization operations to be performed efficiently within the picket.

For example, some pickets have data that is already positive and does not require modification, and some pickets have data that requires complement arithmetic. ABSOLUTE VA
Picket selection is required to perform common simple tasks such as LUE. This task can be performed by complementing the data into the temporary position while setting the mask with the sign of the result. Then, the next instruction can suspend the picket activity that originally contained a positive value. In addition, the next instruction moves the complemented (currently positive) value from the temporary position to the original position. Now all pickets will contain positive values. All that is left is to reactivate the suspended pickets.

The applicable local autonomous function is STAT.
Store operation is performed only when the latch is set,
STORE per STAT (memorized depending on the situation). In the operation described above, this feature saves two steps.

The suspend / reactivate approach presents several problems in the following respects.

1. Machine efficiency drops due to idle processor effects.

2. The act of setting and resetting masks can be a significant part of a complex task and its program.

3. For tasks such as data transfer between processors, individual unit operations need to be completely different compared to simple run / stop mask operations.

The preferred embodiment of the present invention, using the structure described in connection with FIGS. 2-8, addresses the problem of local autonomy.

SIMIMD General Considerations The present invention, when applied to the design of pickets within a SIMD array of pickets, facilitates performing operations that were previously difficult or impossible to perform tasks. Provide some. As a result, each picket will have some degree of local autonomy.

These concepts are described in US Pat. No. 478373.
It is an extension of the run / stop selection described in the prior art, such as No. 8 and No. 5045995.
In the preferred system of the present invention, each picket may be enabled by a collection of mechanisms or multiple mechanisms that allow each picket to have different execution capabilities. These execution capabilities allow each picket to acquire different modes for executing data within the picket, allowing for interpretation of SIMD commands within the picket rather than being sent from an external SIMD controller. . This capability spans multiple modes, in which each processor in the SIMD array can and does perform different operations based on local conditions.

Combining some of these local autonomous functions can give a picket the ability to execute its own local program segment for a short period of time. This allows MI in the SIMD array.
MD ability is given. This architecture is SIMI
Call it MD. Mechanisms that support SIMIMD enable the SIMIMD array processing system of the present invention.

Some of these functions participate in the formation of picket grouping mechanisms to support complex tools for selecting pickets to form groups for separate computations. This function is called grouping, and a mechanism supporting grouping is included in the system of the present invention. Grouping is also described in a related application entitled "Grouping of SIMD Pickets".

Some of these features are "Floating-Po
Participate in the formation of mechanisms for efficient floating-point techniques, described in a related application entitled "int Implementation on a SIMD Machine." It is preferred that these mechanisms support floating-point.

Consideration of System Mechanism Various items of “local autonomy” to be discussed below can be classified into the following three categories. 1. Situation-controlled local operation 2. Data controlled local operation 3. Distribution of status from the processor to the microcontroller

Context Generation Considerations Contexts are set based on previous activity in the instruction stream. The loading of the status register is controlled by the instruction stream. The status register contains the instruction streams Zero Detect, Sign, Equal, Gr.
eater than, Less Than, carr
y out is loaded.

Add with carry is a common use case for the status function to extend the accuracy of operations. Includes more subtle uses of the situation.

The status can be stored in memory as a data word for later use. The situation can also be used in logical and arithmetic operations to produce fairly complex combinations of other stored values. These calculated values can be used to change the value of the picket's dose latch and suspend its operation until the picket becomes available again with other calculated information.

Situations associated with subroutine calls or context switches executing within the array controller can be saved. These values can then be recalled and used by "pop" or "return." Of course, a selected group or subset of pickets can participate in the subroutine operation,
There will be more pickets activated on return from the subroutine.

Context-Controlled Local Operations Each of the following “local autonomous” functions, when selected from the SIMD subsystem controller by a SIMD instruction:
Controlled by the situation. The status can be updated with a command to transfer one or all of the status conditions to the status latch of FIG. 8 or the status latch can be loaded from a memory location. The latter method is called "Group
Used in the grouping of pickets described in the patent application entitled "ing of SIMD Pickets". The status of each local picket is grouped into a status funnel SF.
Can be sent to the SIMD controller via
The controller is provided with a clever way to react clearly to picket activity without having to read the status word from each picket individually.

Local Participation A picket can turn itself on or off based on immediate circumstances. The picket can enter the dose mode by loading the dose latch of FIG. 8 in the picket with the appropriate value. This can be called "local participation" autonomy. Local participation autonomy provides a mechanism for internal control of individual pickets within the picket chip. Doze mode pickets
It does not write to its own memory and does not change the contents of some registers, so it does not change state, but can monitor all test operations and turn it back on again based on the selected result. FIG. 8 shows the relationship between the two "off" modes: dose and disable. In disabled mode, the subsystem controller
Individual pickets that do not actually participate in the process can be disabled. Disable instructions in SIMD controller situations, such as US Pat. No. 5,045,995, can effectively work to disable individual processing elements. However, in the present invention, the controller enables the selected picket when it needs to activate another set of data in the process.

Example: All pickets with values greater than 0 do not participate in the next set of operations.

FIG. 8 shows the relationship between dose and disable in the preferred embodiment of the present invention.

Carry-In by Situation Also, in the present invention, each picket can add carry-in to the current action based on the immediately preceding situation.
This is a common operation in Neumann machines where the data length is a multiple of the hardware register length. However, when multiple pickets are performing the same operation on different data, each picket must generate a carry-in based on the data of the previous operation. this is,
It is a unique action for each picket and is therefore an important local autonomous action.

Example: Search for leading zero in floating point normalization operation.

Prohibition of Storing Depending on the Situation Further, according to the present invention, the packet can be prohibited from being stored in the memory based on the immediately preceding situation. With this selective write operation, picket
Restoring of data to memory can be controlled. This operation can be used as an effective prohibiting mechanism when the operations performed on all pickets do not produce useful results for some individual pickets.

Example: When the absolute value is calculated and the immediately preceding situation is negative, the complement is stored and returned.

Register Source Selection by Context Picket can select one of two data sources and load hardware registers based on the context. The situation is used to switch the multiplexer used to select one of the two data sources. The data source can be two hardware registers, or a broadcast bus and one hardware register.

Example: If the data on the broadcast bus is useful to the picket, read from it. Otherwise, the data in the internal register is used. This example
It represents a dictionary function in which streams of letters and words travel over a broadcast bus and pickets containing potential matches capture the data.

Example: If the content is smaller than the data read from memory, Load Reg from register
To do.

Reading from Alternate Memory Locations, Depending on Context Picket can read data from one of two memory locations, depending on the context (stride is 2n). Usually, there is more than one byte of data in a record. Also, there are typically multiple data records per data set. This select function allows you to select one of two records of data in a local picket situation. Suppose you are looking for a maximum and have tested it to find it.
In that case, this feature should be able to capture selected records for future use.

Example: In a floating point adjust operation, two values are matched and one value is scaled so that the exponent of one matches the other. Deciding which one to scale is determined by comparing the exponents and loading the context value.

Situation Stores to Alternate Memory Locations Pickets can store data in one of two memory locations depending on the situation (the stride is 2
N-th power). This is similar to a read operation.

Choice of Transfers to Adjacent Pickets, Depending on the Situation Pickets can make transfers to adjacent pickets via the sliding action of the present invention. The source data for this operation can be either the A register or the B register depending on the situation. A good example is when comparing data across all pickets. The goal is to identify the maximum. Therefore, all odd pickets move data to the right where it is stored in registers. The receiving picket transfers the larger of the two by comparing the new data word with the data word it has, saving the situation, and selecting the appropriate source.

Data Controlled Local Operations There are several local autonomous functions that are based on the data in each picket. These data-dependent functions use the contents of the data register to determine independent activity within the picket,
Enabled by SIMW controller microwords. Data controlled local operation will be described with some examples.

Reading from Alternate Memory Locations with Data Each picket can address its own memory using the data contained in one of its registers as part of the memory address. Addressable memory fields are powers of two and range from 2 to all picket memories. The current appropriate and practical design point is 4K. Another feature is the introduction of strides in addressing to allow the controller to address the picket every other word, every fourth word, or the like. The base of this field of memory (the other bits of the picket address) is provided by the SIMD controller.

Examples: The main applications of these ideas are 0-
It is a table for obtaining one of a set of values such as a trigonometric function and a transcendental function from a table containing the value of sin for an angle of 90 degrees.

Conditional Indexing to Memory Fields This idea combines the two ideas by conditionally indexing and determining the index depth based on the data in the picket register.

Adder Operation Based on Data from Memory Picket memory can store "instructions" specific to the task of the picket. These instructions are read from memory and stored in the picket's registers.
Dataflow register, multiplexer, and AL
Can be executed by U.

Example: If the SIMD array is performing a simulation of a logic design, each picket can be assigned a logic function. If it is stored in a register, it can be used to command this function in the picket's ALU.

Masking Based on Data from Memory Each picket provides local autonomy by mixing data and masks in memory so that the logical combination of data and mask produces different results for each picket. Can be achieved. Pairing the data with its associated mask forms a unit called a trit.

Distribution of Context from Picket to Microcontroller The third category of local autonomy determines the conditions associated with an event, which can be SIMD via the Context Funnel.
It is about pickets reporting to the controller. The status funnel is basically the overall disjunction of the conditions supplied to the controller from each active picket. The status funnel indicates whether at least one picket contains the requested condition. This idea can be repeated for other conditions so that the controller can possibly be notified of more than three conditions simultaneously.
Therefore, it is possible to make control decisions based on the individual tests performed within the picket and communicate them to the array controller via the STAT reporting funnel.

Example: This function can be used by the controller in determining if a motion is complete, or if there are no more active pickets participating in the motion.

Example: The picket array can perform a search by mask operation on all active pickets that are simultaneously participating. In a mask operation, a matching picket will raise the match line high to indicate a match. Match conditions are sent to the controller via the status funnel for later determination in the active process.

Example: A picket array can hold a collection of information, comparing one character at a time and looking for specific information by turning the picket off when the pickets no longer match. it can. By this, 1
A powerful parallel association feature is provided that handles all active pickets in one simultaneous broadcast comparison.

Multi-Level Situations and Saving Situations Two capabilities for managing iterative generation and control of situations are described. That is, when entering different levels of a program, the situation can be more complex and / or processor-bound. The ability to save and restore a complete picket situation under software control, CALL / RETUR
Allows N levels to be used to cascade levels of software. Each picket saves its status in a separate memory when commanded by the array controller.

Situation Generation Situations are generated as a result of ALU operations. The instruction stream shows the conditions to be tested and how to combine them with existing situations. You have the following options: Ignore test results. Setting a whole new situation. Use OR or XOR of new and existing situations. Conditions that can be used to generate a situation include Zero result, Equal, Greater
than, Less than, Not equal, Equal or greater tha
There are n, Equalor less than, Overflow, and Underflow.

Instruction-Used Situation Usage Each instruction provides a command to each picket as to how to collect and save the situation. Commands are provided for all pickets that show how to use status locally on the picket. These usage commands specify several things. They are all related to the idea of local autonomy, and include picket participation, no restores, contextual data source selection, and control of inter-picket communication. Commands are also provided to the controller of the array of pickets to instruct them how to collect the status of individual pickets to the controller and how to use this status to manage global operation. Basically, the status of each picket is ORed and ANDed with the status of every other picket, and the result is presented to the array controller for use.

General Considerations for the Preferred Floating Point Embodiments It is especially preferred to provide SIMD machines with local autonomy for floating point arithmetic applications. "F
SIMD array as detailed in the above-referenced related application entitled "loating-Point for SIMD Array Machine".
The excellence of the present invention can be understood by adding a description of a new method for providing a machine with floating point capabilities.

The floating point format for the above system allows an array SIMD machine to perform floating point operations. For convenience of explanation, FIG. 9 shows the floating point format of the present invention. The fractional part count is shifted by 1 byte with respect to the exponent part count 1. FIG. 10 illustrates the steps of making a floating point adjustment by shifting the fractional part by one byte and incrementing the floating point exponent by one. With this particular array, the memory can be used to perform adjustment shifts. FIG. 11 illustrates the use of adjusted shifts by using byte wide memory to advantageously perform the shifts that are part of the floating point adjust operation.

Floating Point Format The key to the successful implementation of floating point on SIMD machines is the appropriate format shown in FIG. A suitable format means that the format is compatible with some aspect of the architecture and not necessarily with one of the existing floating point standards.

The present invention provides a format that runs on byte wide data flows and has several times the performance of conventional implementations.

This format is at least IEEE
It produces answers as accurate as the 32-bit floating point standard. This format has an accuracy of about 2 bits higher on average.

Since this format is used by the user, it can be easily converted to and from the existing standard.

Therefore, this format can be regarded as a standard from the outside. Floating point can be efficiently implemented in this proposed format inside a picket, and the format of the data can be converted as needed when loading or deleting data from a parallel processor.

This floating point format was chosen for implementation efficiency on multibyte wide data flows. This format provides implementation efficiency while providing greater computational accuracy than the IEEE 32-bit floating point format.

The format shown in FIG. 9 is IEEE32.
It is a representative of formats suitable for obtaining higher precision than bit floating point formats and is intended to be implemented on machines with byte wide (8 bit) data streams. The preferred format consists of a 1-bit sign, a 7-bit exponent part, and an 8-bit 4-byte fractional part, for a total of 40 bits.

Note that this same style of computation can be extended to extend the precision of floating point calculations by extending the fraction length by an integral number of bytes.

Each count of the exponent part is 8 bits of the decimal part.
Since it represents a shift, the normalized number can have up to 7 leading zeros. If there are 8 or more leading zeros, it is necessary to adjust the value and normalize it.

FIG. 10 illustrates a method of making floating point adjustments using adjustment shifts. In this system, the data words are organized in the format of FIG. To make a floating point adjustment, the fractional part is shifted left by 8 bits and the exponent part is decremented by 1. In a byte wide data flow typical of the system described above, this shift operation is
This can be performed by setting the next byte as the first byte and truncating the first byte of all zeros. The implementation of this shift can be done in various ways.

In the byte width data flow, 1 clock
Data is shifted by 1 byte width in a cycle. Up to 3 shifts are required. This can be combined with a leading zero test.

Another approach, shown in FIG. 11, can be implemented for parallel arrays, which is particularly advantageous for machines where the processing elements of the array have their own memory. In this case, it is assumed that the data is in memory. The machine first determines the number of leading zero bytes. The machine then uses the count of leading 0 bytes to adjust the fetch address used to obtain the data. Then, as part of the data move operation, the normalization process can be performed in 4 clocks.

In a SIMD machine, it is preferable that all operations are executed in a fixed predetermined number of cycles. If a conventional floating point is used where one count in the exponent represents one bit in the fraction, then one shift and count process is performed for each leading 0 in the fraction. Performing normalization requires 0 to 32 cycles. Each picket should perform the appropriate number of cycles for its fraction in its hardware, and the number of cycles will vary from picket to picket. The entire SIMD machine has a maximum (32) to make this process deterministic.
Must be performed for a number of cycles, resulting in a large amount of idle time for many pickets.

The idea described here is decisive and is implemented in 12 cycles as follows.

1. The fractional part is moved from the memory to the register (in the memory), one byte at a time from the most significant side, and whether or not each byte is all 0 is recorded. If all zeros, count the number of bytes that are. This operation requires 4 cycles.

2. Suppose the pointer contains the "address" of the most significant byte of the fraction. The number of 0 bytes (0-4) is added to this pointer so that it points to the most significant non-zero byte of the fractional part. This operation requires one cycle.

3. The pointer is used to store the fractional part back into memory, padding the bytes containing 0s at the least significant side, in order from the most significant non-zero bit. This operation requires 4 cycles.

4. Next, decrement the exponent part by the count number,
Store it back in memory. This operation requires 3 cycles.

This operation is shown in the figure as performed in the picket.

In order to perform normalization by the above method, it is necessary to give a certain degree of local autonomy to a plurality of functions of picket design. Features that provide limited PME or picket autonomy include:

Test for a 1.0 and enter the situation.

2. If the status is set, increment the counter.

3. Use the pointer value in the register as the memory index to provide data-dependent access to memory. While the preferred embodiment of the invention has been described, it will be appreciated that those skilled in the art, both now and in the future, may make various modifications and enhancements that fall within the scope of the claims of the invention. The claims of the present invention should be construed to maintain the proper protection for the invention first disclosed.

[Brief description of drawings]

1 is a recent S that can be regarded as representative of the prior art.
FIG. 6 is a schematic diagram of an IMD processor.

FIG. 2 shows a pair of basic picket units configured on a silicon base with a processor, memory, control logic, and associative memory capable of byte communication with other pickets in the array. Is.

FIG. 3 is a diagram showing a process of an associative memory.

FIG. 4 shows a basic 16 (n) picket configuration for a SIMD subsystem using a microprocessor controller, a hardwired sequencing controller for a canning routine, and a picket array. picket·
This basic parallel picket processor formed by the array
The system may be a stand alone unit.

5 illustrates a multiple picket processor system incorporating the multiple picket processors of FIG.

FIG. 6 is a functional block diagram of a subsystem.

7 is a diagram showing a layout configuration of a subsystem control device including the card of FIG. 5;

FIG. 8 illustrates the relationship between dose and disable instructions for picket local autonomy in a SIMD machine according to a preferred embodiment of the present invention.

FIG. 9 illustrates a particular floating point format of the preferred embodiment of the present invention.

FIG. 10 illustrates steps for making floating point adjustments.

FIG. 11 illustrates how a memory may be used to make shift adjustments in accordance with the present invention.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Thomas Norman Barker, USA 13850, Sunset Avenue, Vestal, NY 136 (72) Inventor James Warren Diefendelfer USA 13827, Owego, NY, Front Street 396 (72) Inventor Peter Michael Coghe Dorchester Drive, Endicott, NY 13760, USA 7

Claims (10)

[Claims] 1. A plurality of array processing elements coupled as pickets for communicating data and instructions with each other,
Each picket has multiple mechanisms that allow it to have different execution capabilities, which enable each picket to acquire different modes for executing data within the picket, SIMD in the picket
A computer system capable of processing SIMD by an array of processors capable of executing data in parallel, which allows the commands to be interpreted. 2. Each picket has the plurality of mechanisms that allow each picket to operate in multiple modes, in which each processor of a SIMD array performs different operations based on local conditions. The computer according to claim 1, which is capable of and actually executes.
system. 3. A SIMIMD array processor mode is provided to allow at least one of the plurality of array processors to operate in SIMIMD mode, with elements in the processor array controlling each clock cycle. The computer system of claim 1, wherein commands are received and executed from a device, some of the commands being capable of being interpreted within each picket to result in different actions. 4. The computer system of claim 2, wherein the interpretation of SIMD commands within each picket can be controlled by one or more status latches or register bits within each picket. 5. The computer system of claim 2 wherein the interpretation of SIMD commands within each picket can be controlled by the data in one or more registers within each picket. 6. The computer system of claim 2, wherein the result status can be collected and sent to a controller of an array of processors. 7. The interpretation of SIMD commands based on picket status results in the picket being able to select one of two data sources for a portion of its operation, the data source being a picket register or a picket. Computer system according to claim 4, characterized in that it can be one or more external data buses. 8. The picket status-based interpretation of SIMD commands results in the picket having one of two picket memory locations for storing the result of an action within the picket.
5. It is possible to select one of them.
The computer system described in. 9. The interpretation of SIMD commands based on picket status results in the picket being able to select one of two data sources within the picket for transfer to an adjacent picket. A computer system according to claim 4. 10. An array of pickets can handle floating point calculations to handle a range of possible floating point numbers, the floating point processing array including a plurality of picket units, each picket. Combined with a local memory coupled to the processing elements for parallel processing of information within all picket units, such that the units are each adapted to perform one element of the processing utilizing the memory Computer according to claim 3, characterized in that it comprises a bit-parallel processing element.
system.